Pub Date : 2008-06-11DOI: 10.1109/SIES.2008.4577706
Marta Beltrán, A. Guzmán
New high performance architectures combining high and low level techniques are widely used today, and FPGA-based designs offer excellent platforms for this kind of systems. There are a lot of multiprocessor systems implemented on FPGApsilas but they are very often application and platform specific. This paper describes the HIPAOC (high performance architecture on chip) system, a general purpose and reconfigurable high performance architecture implemented on a single FPGA. The proposed design is application and platform independent and furthermore, two different memory models, shared or distributed memory, can be used depending on the designer requirements. Therefore it is not only a multiprocessor on chip, it can be a multicomputer on chip too.
{"title":"Designing HIPAOC: High Performance Architecture On Chip","authors":"Marta Beltrán, A. Guzmán","doi":"10.1109/SIES.2008.4577706","DOIUrl":"https://doi.org/10.1109/SIES.2008.4577706","url":null,"abstract":"New high performance architectures combining high and low level techniques are widely used today, and FPGA-based designs offer excellent platforms for this kind of systems. There are a lot of multiprocessor systems implemented on FPGApsilas but they are very often application and platform specific. This paper describes the HIPAOC (high performance architecture on chip) system, a general purpose and reconfigurable high performance architecture implemented on a single FPGA. The proposed design is application and platform independent and furthermore, two different memory models, shared or distributed memory, can be used depending on the designer requirements. Therefore it is not only a multiprocessor on chip, it can be a multicomputer on chip too.","PeriodicalId":438401,"journal":{"name":"2008 International Symposium on Industrial Embedded Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124418894","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-06-11DOI: 10.1109/SIES.2008.4577688
J. Metrôlho, C. Couto, Carlos Alberto Silva, A. Tavares
This paper presents a novel architecture description language, MiADL. This language is capable of specifying a wide class of ISAs by exploring the common features found in instructions, obtaining compact descriptions. Descriptionpsilas efficiency and expressiveness is demonstrated with examples that compare MiADL with other related works, using complex ISAs of contemporary processors. The semantics of new constructs of the language is also presented. These permit smaller descriptions over other ADLs. Results achieved with simulators generated from this language revealed a speed-up over other contributions. A comparison in terms of description effectiveness and simulator performance is presented.
{"title":"A language for automatic generation of fast instruction-set compiled simulators","authors":"J. Metrôlho, C. Couto, Carlos Alberto Silva, A. Tavares","doi":"10.1109/SIES.2008.4577688","DOIUrl":"https://doi.org/10.1109/SIES.2008.4577688","url":null,"abstract":"This paper presents a novel architecture description language, MiADL. This language is capable of specifying a wide class of ISAs by exploring the common features found in instructions, obtaining compact descriptions. Descriptionpsilas efficiency and expressiveness is demonstrated with examples that compare MiADL with other related works, using complex ISAs of contemporary processors. The semantics of new constructs of the language is also presented. These permit smaller descriptions over other ADLs. Results achieved with simulators generated from this language revealed a speed-up over other contributions. A comparison in terms of description effectiveness and simulator performance is presented.","PeriodicalId":438401,"journal":{"name":"2008 International Symposium on Industrial Embedded Systems","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132559620","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-06-11DOI: 10.1109/SIES.2008.4577707
P. Schmidt, S. Frenz, S. Gerhold, P. Schulthess
This paper examines the feasibility of a distributed shared memory in an automotive environment with respect to communication and resource consumption. We briefly present the Plurix cluster operating system and its compiler demonstrating the advantages of a distributed shared memory concept for medium scale computation scenarios. We then apply the DSM concept to a specific use-case from the area of automotive embedded systems. A prototype system was implemented and shown to offer higher bandwidth and lower resource utilisation than conventionally layered designs.
{"title":"Transactional consistency in the automotive environment","authors":"P. Schmidt, S. Frenz, S. Gerhold, P. Schulthess","doi":"10.1109/SIES.2008.4577707","DOIUrl":"https://doi.org/10.1109/SIES.2008.4577707","url":null,"abstract":"This paper examines the feasibility of a distributed shared memory in an automotive environment with respect to communication and resource consumption. We briefly present the Plurix cluster operating system and its compiler demonstrating the advantages of a distributed shared memory concept for medium scale computation scenarios. We then apply the DSM concept to a specific use-case from the area of automotive embedded systems. A prototype system was implemented and shown to offer higher bandwidth and lower resource utilisation than conventionally layered designs.","PeriodicalId":438401,"journal":{"name":"2008 International Symposium on Industrial Embedded Systems","volume":"328 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122827686","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-06-11DOI: 10.1109/SIES.2008.4577712
E. Armengaud, D. Watzenig, C. Steger, H. Berger, Harald Gall, F. Pfister, M. Pistauer
Cars are forming complex distributed architectures implementing optimized networks. Evidently, the communication plays a central role for the dependability and the performance of the system. This document presents the challenges and vision of the newly started TEODACS research project. Our aim is to consider the communication services as a whole and to study the internal (e.g. configuration) and external (e.g. EMC) effects that influence the network and further the system performances. We discuss how our consortium ideally supports this approach and we introduce the projectpsilas vision based on the close development of a laboratory setup as well as a simulation framework.
{"title":"TEODACS : A new vision for testing dependable automotive communication systems","authors":"E. Armengaud, D. Watzenig, C. Steger, H. Berger, Harald Gall, F. Pfister, M. Pistauer","doi":"10.1109/SIES.2008.4577712","DOIUrl":"https://doi.org/10.1109/SIES.2008.4577712","url":null,"abstract":"Cars are forming complex distributed architectures implementing optimized networks. Evidently, the communication plays a central role for the dependability and the performance of the system. This document presents the challenges and vision of the newly started TEODACS research project. Our aim is to consider the communication services as a whole and to study the internal (e.g. configuration) and external (e.g. EMC) effects that influence the network and further the system performances. We discuss how our consortium ideally supports this approach and we introduce the projectpsilas vision based on the close development of a laboratory setup as well as a simulation framework.","PeriodicalId":438401,"journal":{"name":"2008 International Symposium on Industrial Embedded Systems","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123683542","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-06-11DOI: 10.1109/SIES.2008.4577699
R. Barbosa, J. Karlsson
This paper proposes a membership protocol for fault-tolerant distributed systems and describes the usage of formal verification methods to ascertain its correctness. The protocol allows nodes in a synchronous system to maintain consensus on the set of operational nodes, i.e., the membership, in the presence of omission failures and node restarts. It relies on nodes observing the transmissions of other nodes to detect failures. Consensus is maintained by exchanging a configurable number of acknowledgements for each nodepsilas message. Increasing this number makes the protocol resilient to a greater number of simultaneous or near-coincident failures.We used the SPIN model checker to formally verify the correctness of the membership protocol. This paper describes how we modeled the protocol and presents the results of the exhaustively verified model instances.
{"title":"Formal specification and verification of a protocol for consistent diagnosis in real-time embedded systems","authors":"R. Barbosa, J. Karlsson","doi":"10.1109/SIES.2008.4577699","DOIUrl":"https://doi.org/10.1109/SIES.2008.4577699","url":null,"abstract":"This paper proposes a membership protocol for fault-tolerant distributed systems and describes the usage of formal verification methods to ascertain its correctness. The protocol allows nodes in a synchronous system to maintain consensus on the set of operational nodes, i.e., the membership, in the presence of omission failures and node restarts. It relies on nodes observing the transmissions of other nodes to detect failures. Consensus is maintained by exchanging a configurable number of acknowledgements for each nodepsilas message. Increasing this number makes the protocol resilient to a greater number of simultaneous or near-coincident failures.We used the SPIN model checker to formally verify the correctness of the membership protocol. This paper describes how we modeled the protocol and presents the results of the exhaustively verified model instances.","PeriodicalId":438401,"journal":{"name":"2008 International Symposium on Industrial Embedded Systems","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121800748","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-06-11DOI: 10.1109/SIES.2008.4577687
Hehua Zhang, M. Gu, Xiaoyu Song
This paper presents an approach and successful experience of applying timed colored Petri nets on modeling and analyzing a stage machinery control system. The programmable logic controllers (PLCs) based system is modeled with timing constraints. The compositionality is incorporated in the modeling process of the entire design. The PLC synchronization problem with the interactions of environment is analyzed by the state space analysis method. The case studies demonstrate the effectiveness of the approach.
{"title":"Modeling and analysis of stage machinery control systems by timed colored Petri nets","authors":"Hehua Zhang, M. Gu, Xiaoyu Song","doi":"10.1109/SIES.2008.4577687","DOIUrl":"https://doi.org/10.1109/SIES.2008.4577687","url":null,"abstract":"This paper presents an approach and successful experience of applying timed colored Petri nets on modeling and analyzing a stage machinery control system. The programmable logic controllers (PLCs) based system is modeled with timing constraints. The compositionality is incorporated in the modeling process of the entire design. The PLC synchronization problem with the interactions of environment is analyzed by the state space analysis method. The case studies demonstrate the effectiveness of the approach.","PeriodicalId":438401,"journal":{"name":"2008 International Symposium on Industrial Embedded Systems","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124725401","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-06-11DOI: 10.1109/SIES.2008.4577714
B. Nilsson, L. Bengtsson, B. Svensson
Active radio frequency identification (A-RFID) is a technology where the tags (transponders) carry an on board energy source for powering the radio, processor circuits, and sensors. Besides offering longer working distance between RFID-reader and tag than passive RFID, this also enables the tags to do sensor measurements, calculations and storage even when no RFID-reader is in the vicinity of the tags. In this paper we study the effect on tag energy cost and read out delay incurred by some typical back-off algorithms (constant, linear, and exponential) used in a contention based CSMA/CA (carrier sense multiple access/collision avoidance) protocol for A-RFID communication.
{"title":"Selecting back off algorithm in active RFID CSMA/CA based medium-access protocols","authors":"B. Nilsson, L. Bengtsson, B. Svensson","doi":"10.1109/SIES.2008.4577714","DOIUrl":"https://doi.org/10.1109/SIES.2008.4577714","url":null,"abstract":"Active radio frequency identification (A-RFID) is a technology where the tags (transponders) carry an on board energy source for powering the radio, processor circuits, and sensors. Besides offering longer working distance between RFID-reader and tag than passive RFID, this also enables the tags to do sensor measurements, calculations and storage even when no RFID-reader is in the vicinity of the tags. In this paper we study the effect on tag energy cost and read out delay incurred by some typical back-off algorithms (constant, linear, and exponential) used in a contention based CSMA/CA (carrier sense multiple access/collision avoidance) protocol for A-RFID communication.","PeriodicalId":438401,"journal":{"name":"2008 International Symposium on Industrial Embedded Systems","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121927376","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-06-11DOI: 10.1109/SIES.2008.4577675
Ioannis Riakiotakis, G. Papakonstantinou, Anthony T. Chronopoulos
Dynamic scheduling algorithms have been successfully used for parallel computations of nested loops in traditional parallel computers and clusters. In this paper we propose a new architecture, implementing a coarse grain dynamic loop scheduling, suitable for reconfigurable hardware platforms. We use an analytical model and a case study to evaluate the performance of the proposed architecture. This approach makes efficient memory and processing elements use and thus gives better results than previous approaches.
{"title":"Implementation of dynamic loop scheduling in reconfigurable platforms","authors":"Ioannis Riakiotakis, G. Papakonstantinou, Anthony T. Chronopoulos","doi":"10.1109/SIES.2008.4577675","DOIUrl":"https://doi.org/10.1109/SIES.2008.4577675","url":null,"abstract":"Dynamic scheduling algorithms have been successfully used for parallel computations of nested loops in traditional parallel computers and clusters. In this paper we propose a new architecture, implementing a coarse grain dynamic loop scheduling, suitable for reconfigurable hardware platforms. We use an analytical model and a case study to evaluate the performance of the proposed architecture. This approach makes efficient memory and processing elements use and thus gives better results than previous approaches.","PeriodicalId":438401,"journal":{"name":"2008 International Symposium on Industrial Embedded Systems","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123155433","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-06-11DOI: 10.1109/SIES.2008.4577686
Alena Simalatsar, R. Passerone, D. Densmore
The implementation of service-rich, highly interconnected applications and the increasing demand for performance, requires the development of highly optimized and flexible computing platforms. However, the tight real-time requirements of such systems, together with constraints on cost and physical size of the devices, results in increased design complexity and system heterogeneity. This creates a large design space. In this paper, we propose a structured approach based on system level specification languages that supports the rapid exploration and performance evaluation of computing platforms, including their middleware components, through simulation of abstract models. Accuracy is achieved through an off-line rapid architecture profiling procedure. We focus on a process network model, which is more suitable to the description of concurrent functions and data-dominated applications than a traditional sequential programming model. We describe the structure of our simulation framework, and use it to evaluate the performance of the lower layers of the UMTS protocol when mapped on software defined radio oriented architectures.
{"title":"A methodology for architecture exploration and performance analysis using system level design languages and rapid architecture profiling","authors":"Alena Simalatsar, R. Passerone, D. Densmore","doi":"10.1109/SIES.2008.4577686","DOIUrl":"https://doi.org/10.1109/SIES.2008.4577686","url":null,"abstract":"The implementation of service-rich, highly interconnected applications and the increasing demand for performance, requires the development of highly optimized and flexible computing platforms. However, the tight real-time requirements of such systems, together with constraints on cost and physical size of the devices, results in increased design complexity and system heterogeneity. This creates a large design space. In this paper, we propose a structured approach based on system level specification languages that supports the rapid exploration and performance evaluation of computing platforms, including their middleware components, through simulation of abstract models. Accuracy is achieved through an off-line rapid architecture profiling procedure. We focus on a process network model, which is more suitable to the description of concurrent functions and data-dominated applications than a traditional sequential programming model. We describe the structure of our simulation framework, and use it to evaluate the performance of the lower layers of the UMTS protocol when mapped on software defined radio oriented architectures.","PeriodicalId":438401,"journal":{"name":"2008 International Symposium on Industrial Embedded Systems","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128854782","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-06-11DOI: 10.1109/SIES.2008.4577697
Kaj Hänninen, Jukka Mäki-Turja, Mikael Nolin, M. Lindberg, John Lundbäck, Kurt-Lennart Lundbäck
In this paper we present a component model for development of distributed real-time systems. The model is developed to support development of embedded control systems for ground vehicles. The model aims at supporting three important activities in real-time development, (i) design, (ii) analysis and (iii) synthesis. These activities emphasise different and sometimes conflicting requirements that need to be balanced. For example, developers desire freedom in designing to solve complex tasks, analysis tools require the design to be formal enough for analysis and synthesis need to be efficient for low run-time footprint. We have considered industrial requirements for these activities and developed the RubusCMv3 component model. The model has been developed in close cooperation with industrial partners and it is currently being evaluated on real systems.
{"title":"The Rubus component model for resource constrained real-time systems","authors":"Kaj Hänninen, Jukka Mäki-Turja, Mikael Nolin, M. Lindberg, John Lundbäck, Kurt-Lennart Lundbäck","doi":"10.1109/SIES.2008.4577697","DOIUrl":"https://doi.org/10.1109/SIES.2008.4577697","url":null,"abstract":"In this paper we present a component model for development of distributed real-time systems. The model is developed to support development of embedded control systems for ground vehicles. The model aims at supporting three important activities in real-time development, (i) design, (ii) analysis and (iii) synthesis. These activities emphasise different and sometimes conflicting requirements that need to be balanced. For example, developers desire freedom in designing to solve complex tasks, analysis tools require the design to be formal enough for analysis and synthesis need to be efficient for low run-time footprint. We have considered industrial requirements for these activities and developed the RubusCMv3 component model. The model has been developed in close cooperation with industrial partners and it is currently being evaluated on real systems.","PeriodicalId":438401,"journal":{"name":"2008 International Symposium on Industrial Embedded Systems","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125547306","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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