Pub Date : 2008-06-11DOI: 10.1109/SIES.2008.4577701
C. Rodriguez-Donate, R. Romero-Troncoso, A. García-Perez, Daniel A. Razo-Montes
Accurate monitoring on induction motors is mandatory for modern industry in order to guarantee the overall process quality. The common practice for monitoring is performed by third party enterprises that test the electrical machines with general-purpose instrumentation equipment, which do not allow on-line operation with the subsequent increase in production costs. Several methodologies have been proposed in recent years for detection of failures in induction motors; however, these methodologies perform the analysis offline. The contribution of this work is the development of an online monitoring of induction motor failures by measuring the vibration transient signals at the start-up with discrete wavelet transform, and its implementation as an embedded system with FPGA for SOC approach. Experimentation is realized to test the system functionality. From results it is demonstrated that the proposed methodology accurately determinates the motor condition in the presence of broken rotor bars.
{"title":"FPGA based embedded system for induction motor failure monitoring at the start-up transient vibrations with wavelets","authors":"C. Rodriguez-Donate, R. Romero-Troncoso, A. García-Perez, Daniel A. Razo-Montes","doi":"10.1109/SIES.2008.4577701","DOIUrl":"https://doi.org/10.1109/SIES.2008.4577701","url":null,"abstract":"Accurate monitoring on induction motors is mandatory for modern industry in order to guarantee the overall process quality. The common practice for monitoring is performed by third party enterprises that test the electrical machines with general-purpose instrumentation equipment, which do not allow on-line operation with the subsequent increase in production costs. Several methodologies have been proposed in recent years for detection of failures in induction motors; however, these methodologies perform the analysis offline. The contribution of this work is the development of an online monitoring of induction motor failures by measuring the vibration transient signals at the start-up with discrete wavelet transform, and its implementation as an embedded system with FPGA for SOC approach. Experimentation is realized to test the system functionality. From results it is demonstrated that the proposed methodology accurately determinates the motor condition in the presence of broken rotor bars.","PeriodicalId":438401,"journal":{"name":"2008 International Symposium on Industrial Embedded Systems","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126078883","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-06-11DOI: 10.1109/SIES.2008.4577704
R. Wang, M. Gu, Xiaoyu Song, Hehua Zhang
Functional and nonfunctional validation is an important task in complex embedded system developments. This paper proposes a method of applying model checking techniques to validate programable logic controllers (PLCs). Abstraction is used to ameliorate the state explosion problem. The experiment results of an industry application demonstrate the effectiveness of our approach.
{"title":"Verifying programmable logic controllers with abstraction","authors":"R. Wang, M. Gu, Xiaoyu Song, Hehua Zhang","doi":"10.1109/SIES.2008.4577704","DOIUrl":"https://doi.org/10.1109/SIES.2008.4577704","url":null,"abstract":"Functional and nonfunctional validation is an important task in complex embedded system developments. This paper proposes a method of applying model checking techniques to validate programable logic controllers (PLCs). Abstraction is used to ameliorate the state explosion problem. The experiment results of an industry application demonstrate the effectiveness of our approach.","PeriodicalId":438401,"journal":{"name":"2008 International Symposium on Industrial Embedded Systems","volume":"104 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115690596","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-06-11DOI: 10.1109/SIES.2008.4577705
L. M. Contreras-Medina, R. Romero-Troncoso, J. R. Millán-Almaraz, C. Rodriguez-Donate
Machine monitoring is one of the major concerns in modern industry in order to guarantee the overall efficiency during the production process. Several monitoring techniques for machinery failure detection have been developed, being vibration analysis one of the most important techniques. The typical equipment used for vibration analysis is a general purpose single channel spectrum analyzer that most of the cases is not well suited for the specific task and lacks from the capability of simultaneous multiple channel analysis. The contribution of this work is to present the development of a low-cost FPGA based 3-axis simultaneous vibration analyzer for embedded machinery monitoring with the novelty of a post-processing stage that can be designed and implemented into the same FPGA for automatic online detection of specific machinery failures. Two cases of study are presented to show the development performance and capabilities of the system where specific post-processing units are designed. From the results it can be seen that several mechanical failures can be automatically detected by reconfiguring the postprocessing algorithm, embedded in the system.
{"title":"FPGA based multiple-channel vibration analyzer embedded system for industrial applications in automatic failure detection","authors":"L. M. Contreras-Medina, R. Romero-Troncoso, J. R. Millán-Almaraz, C. Rodriguez-Donate","doi":"10.1109/SIES.2008.4577705","DOIUrl":"https://doi.org/10.1109/SIES.2008.4577705","url":null,"abstract":"Machine monitoring is one of the major concerns in modern industry in order to guarantee the overall efficiency during the production process. Several monitoring techniques for machinery failure detection have been developed, being vibration analysis one of the most important techniques. The typical equipment used for vibration analysis is a general purpose single channel spectrum analyzer that most of the cases is not well suited for the specific task and lacks from the capability of simultaneous multiple channel analysis. The contribution of this work is to present the development of a low-cost FPGA based 3-axis simultaneous vibration analyzer for embedded machinery monitoring with the novelty of a post-processing stage that can be designed and implemented into the same FPGA for automatic online detection of specific machinery failures. Two cases of study are presented to show the development performance and capabilities of the system where specific post-processing units are designed. From the results it can be seen that several mechanical failures can be automatically detected by reconfiguring the postprocessing algorithm, embedded in the system.","PeriodicalId":438401,"journal":{"name":"2008 International Symposium on Industrial Embedded Systems","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125354126","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-06-11DOI: 10.1109/SIES.2008.4577690
Francisco Afonso, C. Silva, A. Tavares, S. Montenegro
Critical real-time embedded systems need to make use of fault tolerance techniques to cope with operation time errors, either in hardware or software. Fault tolerance is usually applied by means of redundancy and diversity. Redundant hardware implies the establishment of a distributed system executing a set of fault tolerance strategies by software, and may also employ some form of diversity, by using different variants or versions for the same processing. This work proposes and evaluates a fault tolerance framework for supporting the development of dependable applications. This framework is build upon basic operating system services and middleware communications and brings flexible and transparent support for application threads. A case study involving radar filtering is described and the framework advantages and drawbacks are discussed.
{"title":"Application-level fault tolerance in real-time embedded systems","authors":"Francisco Afonso, C. Silva, A. Tavares, S. Montenegro","doi":"10.1109/SIES.2008.4577690","DOIUrl":"https://doi.org/10.1109/SIES.2008.4577690","url":null,"abstract":"Critical real-time embedded systems need to make use of fault tolerance techniques to cope with operation time errors, either in hardware or software. Fault tolerance is usually applied by means of redundancy and diversity. Redundant hardware implies the establishment of a distributed system executing a set of fault tolerance strategies by software, and may also employ some form of diversity, by using different variants or versions for the same processing. This work proposes and evaluates a fault tolerance framework for supporting the development of dependable applications. This framework is build upon basic operating system services and middleware communications and brings flexible and transparent support for application threads. A case study involving radar filtering is described and the framework advantages and drawbacks are discussed.","PeriodicalId":438401,"journal":{"name":"2008 International Symposium on Industrial Embedded Systems","volume":"104 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122550190","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-06-11DOI: 10.1109/SIES.2008.4577674
M. Khalgui, H. Hanisch
This paper deals with the development of Safety Reconfigurable Embedded Systems following the International Industrial Component-based Standard IEC61499. To handle all possible reconfiguration forms, we propose at first time an Agent-based Architecture where the Agent applies automatic reconfigurations to adapt the system according to well defined conditions. We model this agent with nested state machines according to the formalism Net Condition Event Systems which is an extension of the Petri net formalism. In order to satisfy user requirements, we specify functional and temporal properties with the temporal logic CTL (as well as its extensions ECTL and TCTL) and we apply the Model Checker SESA to check the whole system correctness.
{"title":"NCES-based modelling and CTL-based verification of reconfigurable Benchmark Production Systems","authors":"M. Khalgui, H. Hanisch","doi":"10.1109/SIES.2008.4577674","DOIUrl":"https://doi.org/10.1109/SIES.2008.4577674","url":null,"abstract":"This paper deals with the development of Safety Reconfigurable Embedded Systems following the International Industrial Component-based Standard IEC61499. To handle all possible reconfiguration forms, we propose at first time an Agent-based Architecture where the Agent applies automatic reconfigurations to adapt the system according to well defined conditions. We model this agent with nested state machines according to the formalism Net Condition Event Systems which is an extension of the Petri net formalism. In order to satisfy user requirements, we specify functional and temporal properties with the temporal logic CTL (as well as its extensions ECTL and TCTL) and we apply the Model Checker SESA to check the whole system correctness.","PeriodicalId":438401,"journal":{"name":"2008 International Symposium on Industrial Embedded Systems","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133834897","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-06-11DOI: 10.1109/SIES.2008.4577678
Christof Pitter, Martin Schoeberl
Chip multiprocessing design is an emerging trend for embedded systems. In this paper, we introduce a Java multiprocessor system-on-chip called JopCMP. It is a symmetric shared-memory multiprocessor and consists of up to 8 Java Optimized Processor (JOP) cores, an arbitration control device, and a global shared memory. All components are interconnected with a system-on-chip bus. This paper focuses on the performance evaluation of different hardware configurations of the multicore system. Therefore, we vary the instruction cache sizes, the number of processors and the memory bandwidth. Within our experiments, we measure the performance by running three benchmarks on real hardware: an embedded application from industry, a computationally intensive matrix multiplication and a synthetic benchmark that continuously accesses a shared data structure. Two different field-programmable gate arrays are used for the presented experiments. Our results illustrate the promises and limits of the proposed multiprocessor architecture concerning synchronization, memory bandwidth and caching. Furthermore, we compare the performance and size of JopCMP with a complex Java processor.
{"title":"Performance evaluation of a java chip-multiprocessor","authors":"Christof Pitter, Martin Schoeberl","doi":"10.1109/SIES.2008.4577678","DOIUrl":"https://doi.org/10.1109/SIES.2008.4577678","url":null,"abstract":"Chip multiprocessing design is an emerging trend for embedded systems. In this paper, we introduce a Java multiprocessor system-on-chip called JopCMP. It is a symmetric shared-memory multiprocessor and consists of up to 8 Java Optimized Processor (JOP) cores, an arbitration control device, and a global shared memory. All components are interconnected with a system-on-chip bus. This paper focuses on the performance evaluation of different hardware configurations of the multicore system. Therefore, we vary the instruction cache sizes, the number of processors and the memory bandwidth. Within our experiments, we measure the performance by running three benchmarks on real hardware: an embedded application from industry, a computationally intensive matrix multiplication and a synthetic benchmark that continuously accesses a shared data structure. Two different field-programmable gate arrays are used for the presented experiments. Our results illustrate the promises and limits of the proposed multiprocessor architecture concerning synchronization, memory bandwidth and caching. Furthermore, we compare the performance and size of JopCMP with a complex Java processor.","PeriodicalId":438401,"journal":{"name":"2008 International Symposium on Industrial Embedded Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131274746","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-06-11DOI: 10.1109/SIES.2008.4577710
I. Hegny, O. Hummer, Alois Zoitl, G. Koppensteiner, M. Merdan
The need for agility in manufacturing systems is continuously growing. This is caused by increasing complexity and decreasing life cycles of the produced goods. This paper proposes a modular, reconfigurable manufacturing system, based on a distributed three layer architecture, consisting of mechatronic components, an IEC 61499 based distributed low level control and on top a multi agent system as high level control. Adaptivity to new demands is added by the inclusion of knowledge in the top layer. Agents are able to understand the structure of the manufacturing system and the produced goods. This enables the high level control to reconfigure the underlying system. To gain most value of this combination, agents and the low level control have to work together in an integrated environment. An interface for connecting distributed low level control and the multi agent system is presented.
{"title":"Integrating software agents and IEC 61499 realtime control for reconfigurable distributed manufacturing systems","authors":"I. Hegny, O. Hummer, Alois Zoitl, G. Koppensteiner, M. Merdan","doi":"10.1109/SIES.2008.4577710","DOIUrl":"https://doi.org/10.1109/SIES.2008.4577710","url":null,"abstract":"The need for agility in manufacturing systems is continuously growing. This is caused by increasing complexity and decreasing life cycles of the produced goods. This paper proposes a modular, reconfigurable manufacturing system, based on a distributed three layer architecture, consisting of mechatronic components, an IEC 61499 based distributed low level control and on top a multi agent system as high level control. Adaptivity to new demands is added by the inclusion of knowledge in the top layer. Agents are able to understand the structure of the manufacturing system and the produced goods. This enables the high level control to reconfigure the underlying system. To gain most value of this combination, agents and the low level control have to work together in an integrated environment. An interface for connecting distributed low level control and the multi agent system is presented.","PeriodicalId":438401,"journal":{"name":"2008 International Symposium on Industrial Embedded Systems","volume":"139 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122841545","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-06-11DOI: 10.1109/SIES.2008.4577681
Gordon Meiser, T. Eisenbarth, Kerstin Lemke-Rust, C. Paar
This work is motivated by the question of how efficient modern stream ciphers in the eSTREAM project (Profile I) can be implemented on small embedded microcontrollers that are also constrained in memory resources. In response to this question, we present the first implementation results for Dragon, HC-128, LEX, Salsa20, Salsa20/12, and Sosemanuk on 8-bit microcontrollers. These ciphers are definitively free for any use, i.e., their use is not covered by intellectual property rights. For the evaluation process, we follow a two-stage approach and compare with efficient implementations of the AES block cipher. First, the C code implementation provided by the cipherspsila designers was ported to an 8-bit AVR microcontroller and the suitability of these stream ciphers for the use in embedded systems was assessed. In the second stage we implemented Dragon, LEX, Salsa20, Salsa20/12, and Sosemanuk in assembler to tap the full potential of an embedded implementation. Our efficiency metrics are memory usage in flash and SRAM and performance of keystream generation, key setup, and IV setup. Regarding encryption speed, all stream ciphers except for Salsa20 turned out to outperform AES. In terms of memory needs, Salsa20, Salsa20/12, and LEX are almost as compact as AES. In view of the final eSTREAM portfolio (Profile I), Salsa20/12 is the only promising alternative for the AES cipher on memory constrained 8-bit embedded microcontrollers. For embedded applications with high throughput requirements, Sosemanuk is the most suitable cipher if its considerable higher memory needs can be tolerated.
{"title":"Efficient implementation of eSTREAM ciphers on 8-bit AVR microcontrollers","authors":"Gordon Meiser, T. Eisenbarth, Kerstin Lemke-Rust, C. Paar","doi":"10.1109/SIES.2008.4577681","DOIUrl":"https://doi.org/10.1109/SIES.2008.4577681","url":null,"abstract":"This work is motivated by the question of how efficient modern stream ciphers in the eSTREAM project (Profile I) can be implemented on small embedded microcontrollers that are also constrained in memory resources. In response to this question, we present the first implementation results for Dragon, HC-128, LEX, Salsa20, Salsa20/12, and Sosemanuk on 8-bit microcontrollers. These ciphers are definitively free for any use, i.e., their use is not covered by intellectual property rights. For the evaluation process, we follow a two-stage approach and compare with efficient implementations of the AES block cipher. First, the C code implementation provided by the cipherspsila designers was ported to an 8-bit AVR microcontroller and the suitability of these stream ciphers for the use in embedded systems was assessed. In the second stage we implemented Dragon, LEX, Salsa20, Salsa20/12, and Sosemanuk in assembler to tap the full potential of an embedded implementation. Our efficiency metrics are memory usage in flash and SRAM and performance of keystream generation, key setup, and IV setup. Regarding encryption speed, all stream ciphers except for Salsa20 turned out to outperform AES. In terms of memory needs, Salsa20, Salsa20/12, and LEX are almost as compact as AES. In view of the final eSTREAM portfolio (Profile I), Salsa20/12 is the only promising alternative for the AES cipher on memory constrained 8-bit embedded microcontrollers. For embedded applications with high throughput requirements, Sosemanuk is the most suitable cipher if its considerable higher memory needs can be tolerated.","PeriodicalId":438401,"journal":{"name":"2008 International Symposium on Industrial Embedded Systems","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115334480","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-06-11DOI: 10.1109/SIES.2008.4577696
Fadia Nemer, H. Cassé, P. Sainrat, J. Bahsoun
In hard real-time applications, Worst Case Execution Time (WCET) is used to check time constraints of the whole system but is only computed at the task level. As most WCET computation methods assume a conservative approach to handle the processor state before the execution of a task, the inter-task analysis of long effect hardware features should improve the accuracy of the result. As an example, we propose to analyze the behavior of an A-way associative instruction cache, by combining inter-and intra-task instruction cache analysis. The aim is to estimate more accurately the number of cache misses due to task chaining by considering task Entry and Exit states along the inter-task analysis. The initial tasks WCETs can be computed by any existing single-task approach that models the instruction cache behavior. A second method is also introduced in this paper which consists in injecting the inter-task cache states in the intra-task WCET analysis, to get more precise numbers.
{"title":"Inter-task WCET computation for a-way instruction caches","authors":"Fadia Nemer, H. Cassé, P. Sainrat, J. Bahsoun","doi":"10.1109/SIES.2008.4577696","DOIUrl":"https://doi.org/10.1109/SIES.2008.4577696","url":null,"abstract":"In hard real-time applications, Worst Case Execution Time (WCET) is used to check time constraints of the whole system but is only computed at the task level. As most WCET computation methods assume a conservative approach to handle the processor state before the execution of a task, the inter-task analysis of long effect hardware features should improve the accuracy of the result. As an example, we propose to analyze the behavior of an A-way associative instruction cache, by combining inter-and intra-task instruction cache analysis. The aim is to estimate more accurately the number of cache misses due to task chaining by considering task Entry and Exit states along the inter-task analysis. The initial tasks WCETs can be computed by any existing single-task approach that models the instruction cache behavior. A second method is also introduced in this paper which consists in injecting the inter-task cache states in the intra-task WCET analysis, to get more precise numbers.","PeriodicalId":438401,"journal":{"name":"2008 International Symposium on Industrial Embedded Systems","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131214872","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-06-11DOI: 10.1109/SIES.2008.4577708
A. Gargantini, E. Riccobene, P. Scandurra
This paper presents a validation and verification tool component, based on the abstract state machine formal method, that we are developing to support high level formal analysis of embedded system model-driven design. This component is integrated into a model-driven environment for HW/SW co-design that provides a graphical high-level representation of HW and SW components by means of UML profiles for SystemC/multi-thread C, and allows C/C++/SystemC code generation/back-annotation from/to graphical UML models.
本文提出了一个基于抽象状态机形式化方法的验证和验证工具组件，以支持嵌入式系统模型驱动设计的高级形式化分析。该组件被集成到一个模型驱动的环境中，用于HW/SW协同设计，该环境通过SystemC/多线程C的UML概要文件提供了HW和SW组件的图形高级表示，并允许C/ c++ /SystemC代码生成/从/到图形UML模型的反向注释。
{"title":"A model-driven validation & verification environment for embedded systems","authors":"A. Gargantini, E. Riccobene, P. Scandurra","doi":"10.1109/SIES.2008.4577708","DOIUrl":"https://doi.org/10.1109/SIES.2008.4577708","url":null,"abstract":"This paper presents a validation and verification tool component, based on the abstract state machine formal method, that we are developing to support high level formal analysis of embedded system model-driven design. This component is integrated into a model-driven environment for HW/SW co-design that provides a graphical high-level representation of HW and SW components by means of UML profiles for SystemC/multi-thread C, and allows C/C++/SystemC code generation/back-annotation from/to graphical UML models.","PeriodicalId":438401,"journal":{"name":"2008 International Symposium on Industrial Embedded Systems","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130766590","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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