With the continuous dimension shrinkage, the communication channels of networks-on-chip (NoCs) are often vulnerable to many logic level manufacturing faults resulting in miscellaneous system-level failures. Correspondingly, their effects on the system performance are widely visible. A new distributed, online, test solution that addresses stuck-at and open faults in NoC channels in view of maintaining system reliability and yield, is presented here. Considering a suitable test scheduling scheme, the test time and associated performance overhead are lowered. The evaluation of the proposed scheme on a 33 mesh NoC details its runtime performance. It is observed that the proposed solution saves up to 125% test time. Further, average packet latency is improved by 31.93% while energy consumption is reduced by 27.88%.
{"title":"Heaping of Sorrow Upon Sorrow","authors":"B. Bhowmik","doi":"10.1109/ISES.2018.00046","DOIUrl":"https://doi.org/10.1109/ISES.2018.00046","url":null,"abstract":"With the continuous dimension shrinkage, the communication channels of networks-on-chip (NoCs) are often vulnerable to many logic level manufacturing faults resulting in miscellaneous system-level failures. Correspondingly, their effects on the system performance are widely visible. A new distributed, online, test solution that addresses stuck-at and open faults in NoC channels in view of maintaining system reliability and yield, is presented here. Considering a suitable test scheduling scheme, the test time and associated performance overhead are lowered. The evaluation of the proposed scheme on a 33 mesh NoC details its runtime performance. It is observed that the proposed solution saves up to 125% test time. Further, average packet latency is improved by 31.93% while energy consumption is reduced by 27.88%.","PeriodicalId":447663,"journal":{"name":"2018 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127183192","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
H. Thapliyal, Nathan Ratajczak, O. Wendroth, Carson Labrado
Ever-driven by technological innovation, the Internet of Things (IoT) is continuing its exceptional evolution and growth into the common consumer space. In the wake of these developments, this paper proposes a framework for an IoT home security system that is secure, expandable, and accessible. Congruent with the ideals of the IoT, we are proposing a system utilizing an ultra-low-power wireless sensor network which would interface with a central hub via Bluetooth 4, commonly referred to as Bluetooth Low Energy (BLE), to monitor the home. Additionally, the system would interface with an Amazon Echo to accept user voice commands. The aforementioned central hub would also act as a web server and host an internet accessible configuration page from which users could monitor and customize their system. An internet-connected system would carry the capability to notify the users of system alarms via SMS or email. Finally, this proof of concept is intended to demonstrate expandability into other areas of home automation or building monitoring functions in general.
{"title":"Amazon Echo Enabled IoT Home Security System for Smart Home Environment","authors":"H. Thapliyal, Nathan Ratajczak, O. Wendroth, Carson Labrado","doi":"10.1109/ises.2018.00017","DOIUrl":"https://doi.org/10.1109/ises.2018.00017","url":null,"abstract":"Ever-driven by technological innovation, the Internet of Things (IoT) is continuing its exceptional evolution and growth into the common consumer space. In the wake of these developments, this paper proposes a framework for an IoT home security system that is secure, expandable, and accessible. Congruent with the ideals of the IoT, we are proposing a system utilizing an ultra-low-power wireless sensor network which would interface with a central hub via Bluetooth 4, commonly referred to as Bluetooth Low Energy (BLE), to monitor the home. Additionally, the system would interface with an Amazon Echo to accept user voice commands. The aforementioned central hub would also act as a web server and host an internet accessible configuration page from which users could monitor and customize their system. An internet-connected system would carry the capability to notify the users of system alarms via SMS or email. Finally, this proof of concept is intended to demonstrate expandability into other areas of home automation or building monitoring functions in general.","PeriodicalId":447663,"journal":{"name":"2018 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116797930","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Harsha Keerthan Samudrala, Dr Shaik A. Qadeer, Syed Azeemuddin, Zafar Khan
In this paper we discuss the VLSI implementation of the new radix-2 Decimation In Time (DIT) Fast Fourier Transform (FFT) algorithm with reduced arithmetic complexity which is based on scaling the twiddle factor. Some signal processing require high performance FFT processors and to meet these performance requirements, the processor needs to be pipelined and parallelized. An optimized ASIC design is derived from this new radix-2 algorithm with fewer multipliers and adopted a complete parallel and pipelined architecture for hardware implementation of a 64 point FFT. The implementation results show that the proposed architecture significantly reduces the hardware area by 13.74 percent and power consumption by 16 percent when compared to the standard FFT architecture. Simulation of design units is done in Xilinx ISE WebPack 13.1 and synthesized using Cadence Encounter RTL Compiler.
在本文中，我们讨论了基于缩放旋转因子的新的基数-2十进制(DIT)快速傅立叶变换(FFT)算法的VLSI实现，该算法降低了算法复杂度。一些信号处理需要高性能FFT处理器，为了满足这些性能要求，处理器需要被流水线化和并行化。基于这种新的基数-2算法，采用了更少乘数的优化ASIC设计，并采用完整的并行和流水线架构实现了64点FFT的硬件实现。实现结果表明，与标准FFT体系结构相比，所提出的体系结构显著减少了13.74%的硬件面积和16%的功耗。设计单元的仿真在Xilinx ISE WebPack 13.1中完成，并使用Cadence Encounter RTL Compiler进行合成。
{"title":"Parallel and Pipelined VLSI Implementation of the New Radix-2 DIT FFT Algorithm","authors":"Harsha Keerthan Samudrala, Dr Shaik A. Qadeer, Syed Azeemuddin, Zafar Khan","doi":"10.1109/ISES.2018.00015","DOIUrl":"https://doi.org/10.1109/ISES.2018.00015","url":null,"abstract":"In this paper we discuss the VLSI implementation of the new radix-2 Decimation In Time (DIT) Fast Fourier Transform (FFT) algorithm with reduced arithmetic complexity which is based on scaling the twiddle factor. Some signal processing require high performance FFT processors and to meet these performance requirements, the processor needs to be pipelined and parallelized. An optimized ASIC design is derived from this new radix-2 algorithm with fewer multipliers and adopted a complete parallel and pipelined architecture for hardware implementation of a 64 point FFT. The implementation results show that the proposed architecture significantly reduces the hardware area by 13.74 percent and power consumption by 16 percent when compared to the standard FFT architecture. Simulation of design units is done in Xilinx ISE WebPack 13.1 and synthesized using Cadence Encounter RTL Compiler.","PeriodicalId":447663,"journal":{"name":"2018 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116660811","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"[Copyright notice]","authors":"","doi":"10.1109/ises.2018.00003","DOIUrl":"https://doi.org/10.1109/ises.2018.00003","url":null,"abstract":"","PeriodicalId":447663,"journal":{"name":"2018 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133960791","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"[Title page i]","authors":"","doi":"10.1109/ises.2018.00001","DOIUrl":"https://doi.org/10.1109/ises.2018.00001","url":null,"abstract":"","PeriodicalId":447663,"journal":{"name":"2018 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116617156","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Mobile ad hoc networks (MANETs) are self-configuring, dynamic networks in which nodes are free to move. These nodes are susceptible to various malicious attacks. In this paper, we propose a distributed trust-based security scheme to prevent multiple attacks such as Probe, Denial-of-Service (DoS), Vampire, User-to-Root (U2R) occurring simultaneously. We report above 95% accuracy in data transmission and reception by applying the proposed scheme. The simulation has been carried out using network simulator ns-2 in a AODV routing protocol environment. To the best of the authors' knowledge, this is the first work reporting a distributed trust-based prevention scheme for preventing multiple attacks. We also check the scalability of the technique using variable node densities in the network.
{"title":"Distributed Trust-Based Multiple Attack Prevention for Secure MANETs","authors":"Gurveen Vaseer, Garima Ghai, D. Ghai","doi":"10.1109/ISES.2018.00032","DOIUrl":"https://doi.org/10.1109/ISES.2018.00032","url":null,"abstract":"Mobile ad hoc networks (MANETs) are self-configuring, dynamic networks in which nodes are free to move. These nodes are susceptible to various malicious attacks. In this paper, we propose a distributed trust-based security scheme to prevent multiple attacks such as Probe, Denial-of-Service (DoS), Vampire, User-to-Root (U2R) occurring simultaneously. We report above 95% accuracy in data transmission and reception by applying the proposed scheme. The simulation has been carried out using network simulator ns-2 in a AODV routing protocol environment. To the best of the authors' knowledge, this is the first work reporting a distributed trust-based prevention scheme for preventing multiple attacks. We also check the scalability of the technique using variable node densities in the network.","PeriodicalId":447663,"journal":{"name":"2018 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128264896","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
With the rapid advancement of communication technology, secure data transfer has become the primary concern for every communication system. Advanced Encryption Standard (AES) has been proved to be useful and effective for providing high security to the image processing applications. In this paper, Active Fixed Hardware Obfuscation based secure 128-bit AES algorithm is proposed for improving the security aspects of image data transfer. The proposed method adopts the classic framework of Xilinx System Generator (XSG) which uses Vivado 2016.2 and MATLAB 2015b. Hardware Software Co-simulation is done using XSG on Xilinx 7000 SoC FPGA ZedBoard. Extensive simulation results using various test cases demonstrate the effectiveness and robustness of the proposed method. Security analysis results in terms of Histogram analysis, Adjacent Pixel Auto-Correlation Test and Information Entropy Test show that the encryption quality of the proposed method reaches the current state of the arts. Simulation results show that the proposed method offers 1.49% of area overhead with respect to original AES design. The proposed method exhibits throughput of 5.48Gbps.
{"title":"Hardware Software Co-Simulation of Obfuscated 128-Bit AES Algorithm for Image Processing Applications","authors":"Surbhi Chhabra, K. Lata","doi":"10.1109/ISES.2018.00049","DOIUrl":"https://doi.org/10.1109/ISES.2018.00049","url":null,"abstract":"With the rapid advancement of communication technology, secure data transfer has become the primary concern for every communication system. Advanced Encryption Standard (AES) has been proved to be useful and effective for providing high security to the image processing applications. In this paper, Active Fixed Hardware Obfuscation based secure 128-bit AES algorithm is proposed for improving the security aspects of image data transfer. The proposed method adopts the classic framework of Xilinx System Generator (XSG) which uses Vivado 2016.2 and MATLAB 2015b. Hardware Software Co-simulation is done using XSG on Xilinx 7000 SoC FPGA ZedBoard. Extensive simulation results using various test cases demonstrate the effectiveness and robustness of the proposed method. Security analysis results in terms of Histogram analysis, Adjacent Pixel Auto-Correlation Test and Information Entropy Test show that the encryption quality of the proposed method reaches the current state of the arts. Simulation results show that the proposed method offers 1.49% of area overhead with respect to original AES design. The proposed method exhibits throughput of 5.48Gbps.","PeriodicalId":447663,"journal":{"name":"2018 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120832731","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Laavanya Rachakonda, P. Sundaravadivel, S. Mohanty, E. Kougianos, M. Ganapathiraju
Psychological stress is a sense of pressure which affects the physiological parameters in a person. In this paper a novel stress detection system, iStress is proposed which monitors stress levels through body temperature, rate of motion and sweat during physical activity. The implementation of the iStress system uses a neural network approach utilizing a Mamdani-type fuzzy logic controller with more than 150 instances as the model. The collected data are sent and stored in the cloud, which can help in real time monitoring of the person's stress level thereby reducing risks to health. This system consumes low energy although operating in real time. The proposed system has an ability to produce results with 97% accuracy, low system complexity and moderate cost.
{"title":"A Smart Sensor in the IoMT for Stress Level Detection","authors":"Laavanya Rachakonda, P. Sundaravadivel, S. Mohanty, E. Kougianos, M. Ganapathiraju","doi":"10.1109/ISES.2018.00039","DOIUrl":"https://doi.org/10.1109/ISES.2018.00039","url":null,"abstract":"Psychological stress is a sense of pressure which affects the physiological parameters in a person. In this paper a novel stress detection system, iStress is proposed which monitors stress levels through body temperature, rate of motion and sweat during physical activity. The implementation of the iStress system uses a neural network approach utilizing a Mamdani-type fuzzy logic controller with more than 150 instances as the model. The collected data are sent and stored in the cloud, which can help in real time monitoring of the person's stress level thereby reducing risks to health. This system consumes low energy although operating in real time. The proposed system has an ability to produce results with 97% accuracy, low system complexity and moderate cost.","PeriodicalId":447663,"journal":{"name":"2018 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123516213","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Towards designing an on-chip harvesting system design for IoT, an inductor free methodology is proposed. The solar system behavior is analyzed and proper control algorithm for maximum power point tracking (MPPT) is adopted. The control section monitors the computational circuit and recharging of the battery. Capacitor value modulation (CVM) is used for impedance matching. The conversion efficiency of the DC-DC converter is from 87% to 97%. The resulting output is in the range of 3-3.55V.
{"title":"Energy Efficient Ultra Low Power Solar Harvesting System Design with MPPT for IOT Edge Node Devices","authors":"S. K. Ram, S. Sahoo, S. K., Kamalakanta Mahapatra","doi":"10.1109/ISES.2018.00036","DOIUrl":"https://doi.org/10.1109/ISES.2018.00036","url":null,"abstract":"Towards designing an on-chip harvesting system design for IoT, an inductor free methodology is proposed. The solar system behavior is analyzed and proper control algorithm for maximum power point tracking (MPPT) is adopted. The control section monitors the computational circuit and recharging of the battery. Capacitor value modulation (CVM) is used for impedance matching. The conversion efficiency of the DC-DC converter is from 87% to 97%. The resulting output is in the range of 3-3.55V.","PeriodicalId":447663,"journal":{"name":"2018 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122926406","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Visible light communications integrated with Internet-of-Things has numerous applications in indoor wireless communications and it requires high data rates and flicker mitigation. Flicker mitigation is an important consideration since light emitting diodes are simultaneously used for illumination and communications. Several run-length limited (RLL) codes have been proposed in the literature for flicker mitigation with trade-offs between code rate, bit error performance, encoding and decoding complexities. However, there are no generalized algorithms for high rate codes generation with low complexity encoding and decoding. Hence, in this paper, we propose generalized algorithm for generating high rate RLL codes with low complexity encoding and decoding. The proposed codes can be used for flicker mitigation conditioned on maximum flickering time period (MFTP). The performance of the proposed codes is compared with existing codes in terms of various metrics like code rate, minimum Hamming distance, peak to average power ratio, run-length, and bit error rate. We show that the proposed codes mitigate flicker conditioned on MFTP and provide high data rates with low complexity encoding and decoding compared to the codes in the literature.
{"title":"Flicker Mitigating High Rate RLL Codes for VLC with Low Complexity Encoding and Decoding","authors":"Uday Thummaluri, Abhinav Kumar, L. Natarajan","doi":"10.1109/ISES.2018.00053","DOIUrl":"https://doi.org/10.1109/ISES.2018.00053","url":null,"abstract":"Visible light communications integrated with Internet-of-Things has numerous applications in indoor wireless communications and it requires high data rates and flicker mitigation. Flicker mitigation is an important consideration since light emitting diodes are simultaneously used for illumination and communications. Several run-length limited (RLL) codes have been proposed in the literature for flicker mitigation with trade-offs between code rate, bit error performance, encoding and decoding complexities. However, there are no generalized algorithms for high rate codes generation with low complexity encoding and decoding. Hence, in this paper, we propose generalized algorithm for generating high rate RLL codes with low complexity encoding and decoding. The proposed codes can be used for flicker mitigation conditioned on maximum flickering time period (MFTP). The performance of the proposed codes is compared with existing codes in terms of various metrics like code rate, minimum Hamming distance, peak to average power ratio, run-length, and bit error rate. We show that the proposed codes mitigate flicker conditioned on MFTP and provide high data rates with low complexity encoding and decoding compared to the codes in the literature.","PeriodicalId":447663,"journal":{"name":"2018 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124443505","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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