Amrutnarayan Panigrahi, J. P. Mohanty, A. Swain, K. Mahapatra
The focus on Human-Computer Interaction (HCI) research is increasing day by day, due to the increasing requirement of intelligent input devices. Hand Gesture Recognition is a small sub-field but presents a significant number of applications and consumer products. Most researches target on the feasibility of recognition systems but give less weight to the device resources, so the cost and time. The time-consuming complicated algorithms' use is limited to special purpose devices such as expensive gaming consoles. The use of such systems in low cost embedded hardware in realtime circumstances is required, with the comfortability to use it. In this paper, we design an efficient real-time keyboard-like HCI using Static HGR. We have proposed and implemented new methods to reduce the time consumption while maintaining the high accuracy of 90% with scale and rotation invariance. Also, to maintain the comfort of use, we have eliminated complicated gestures and used only 11 gestures as input gesture set.
{"title":"Real-Time Efficient Detection in Vision Based Static Hand Gesture Recognition","authors":"Amrutnarayan Panigrahi, J. P. Mohanty, A. Swain, K. Mahapatra","doi":"10.1109/ISES.2018.00064","DOIUrl":"https://doi.org/10.1109/ISES.2018.00064","url":null,"abstract":"The focus on Human-Computer Interaction (HCI) research is increasing day by day, due to the increasing requirement of intelligent input devices. Hand Gesture Recognition is a small sub-field but presents a significant number of applications and consumer products. Most researches target on the feasibility of recognition systems but give less weight to the device resources, so the cost and time. The time-consuming complicated algorithms' use is limited to special purpose devices such as expensive gaming consoles. The use of such systems in low cost embedded hardware in realtime circumstances is required, with the comfortability to use it. In this paper, we design an efficient real-time keyboard-like HCI using Static HGR. We have proposed and implemented new methods to reduce the time consumption while maintaining the high accuracy of 90% with scale and rotation invariance. Also, to maintain the comfort of use, we have eliminated complicated gestures and used only 11 gestures as input gesture set.","PeriodicalId":447663,"journal":{"name":"2018 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125744241","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper employs a model based on Artificial Neural Networks (ANN) to design a CMOS Inverter and Chain of Inverters and determine how accurately the ANN based designs are able to model the complex, non-linear problem of circuit design. ANN is designed to predict the performance parameters of a CMOS Inverter and chain of inverters for a given process technology. A function fitting ANN with Bayesian Backpropagation Regularization as the training algorithm was designed with three hidden layers of sizes 20, 10, 8 respectively. Test performances of 99% were obtained in the various studies performed. These results show that ANNs have a high accuracy and are able to adapt as the complexity of the circuit increases.
{"title":"Design of CMOS Inverter and Chain of Inverters Using Neural Networks","authors":"Likhit Valavala, Kalpit Munot, K. R. Teja","doi":"10.1109/ises.2018.00065","DOIUrl":"https://doi.org/10.1109/ises.2018.00065","url":null,"abstract":"This paper employs a model based on Artificial Neural Networks (ANN) to design a CMOS Inverter and Chain of Inverters and determine how accurately the ANN based designs are able to model the complex, non-linear problem of circuit design. ANN is designed to predict the performance parameters of a CMOS Inverter and chain of inverters for a given process technology. A function fitting ANN with Bayesian Backpropagation Regularization as the training algorithm was designed with three hidden layers of sizes 20, 10, 8 respectively. Test performances of 99% were obtained in the various studies performed. These results show that ANNs have a high accuracy and are able to adapt as the complexity of the circuit increases.","PeriodicalId":447663,"journal":{"name":"2018 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129610939","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Rolf Arne Kjellby, Erol Gorancic, Anders Liland, Linga Reddy Cenkeramaddi, Geir Jevne
This paper presents the design and development of a wireless smart brewery controller. The controller is designed to be implemented in breweries with resistive heating elements of up to 3000 watts. By utilizing Bluetooth Smart, the brewery can be remotely controlled from an Android application, with the possibility of adding recipes with ingredients, notifications, and parameter adjustments while brewing. The system has been integrated in a 27-liter kettle to demonstrate usability. A complete prototype is made and tested, in making different flavors of beers.
{"title":"Smart Brewery Controller","authors":"Rolf Arne Kjellby, Erol Gorancic, Anders Liland, Linga Reddy Cenkeramaddi, Geir Jevne","doi":"10.1109/ises.2018.00052","DOIUrl":"https://doi.org/10.1109/ises.2018.00052","url":null,"abstract":"This paper presents the design and development of a wireless smart brewery controller. The controller is designed to be implemented in breweries with resistive heating elements of up to 3000 watts. By utilizing Bluetooth Smart, the brewery can be remotely controlled from an Android application, with the possibility of adding recipes with ingredients, notifications, and parameter adjustments while brewing. The system has been integrated in a 27-liter kettle to demonstrate usability. A complete prototype is made and tested, in making different flavors of beers.","PeriodicalId":447663,"journal":{"name":"2018 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122359272","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Ashwini A. Kulkarni, Khushboo Rani, Sukarn Agarwal, S. P. Mahajan, H. Kapoor
Recent advances in CMOS technology adds more transistors to the chip that are utilised for improving processing capability by adding multiple processing components. These multiple cores raise the data demands leading to larger on-chip caches. Together, these add to the energy consumption as well as heat dissipation. Increase in chip temperature requires efficient cooling mechanisms as high temperatures can damage the onchip circuitry. Thus, the performance enhancement comes at the cost of higher power budget as well as temperature. Large onchip caches occupy significant area of the chip and are major contributors to leakage energy. It is known that as technology scales leakage becomes a prominent component which also affects the chip temperature. This paper aims to control the chip temperature by controlling the leakage energy dissipated by the last level caches (LLCs). Towards this we propose a hybrid LLC that uses a combination of SRAM cache banks and non-volatile memory (NVM) technology based STT-RAM banks. STT-RAM technology has the advantage of high density and low leakage.We demonstrate that low-leakage STT-RAM banks help in reducing the temperature of the tile in which they are located and it also assists in reducing the average chip temperature. Experimental evaluation on an isoarea and iso-capacity architecture that uses a hybrid LLC shows reduction the average chip temperature as well as gives gains in static energy and EDP compared to baseline architecture.
{"title":"Towards Analysing the Effect of Hybrid Caches on the Temperature of Tiled Chip Multi-Processors","authors":"Ashwini A. Kulkarni, Khushboo Rani, Sukarn Agarwal, S. P. Mahajan, H. Kapoor","doi":"10.1109/ISES.2018.00021","DOIUrl":"https://doi.org/10.1109/ISES.2018.00021","url":null,"abstract":"Recent advances in CMOS technology adds more transistors to the chip that are utilised for improving processing capability by adding multiple processing components. These multiple cores raise the data demands leading to larger on-chip caches. Together, these add to the energy consumption as well as heat dissipation. Increase in chip temperature requires efficient cooling mechanisms as high temperatures can damage the onchip circuitry. Thus, the performance enhancement comes at the cost of higher power budget as well as temperature. Large onchip caches occupy significant area of the chip and are major contributors to leakage energy. It is known that as technology scales leakage becomes a prominent component which also affects the chip temperature. This paper aims to control the chip temperature by controlling the leakage energy dissipated by the last level caches (LLCs). Towards this we propose a hybrid LLC that uses a combination of SRAM cache banks and non-volatile memory (NVM) technology based STT-RAM banks. STT-RAM technology has the advantage of high density and low leakage.We demonstrate that low-leakage STT-RAM banks help in reducing the temperature of the tile in which they are located and it also assists in reducing the average chip temperature. Experimental evaluation on an isoarea and iso-capacity architecture that uses a hybrid LLC shows reduction the average chip temperature as well as gives gains in static energy and EDP compared to baseline architecture.","PeriodicalId":447663,"journal":{"name":"2018 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130613246","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Rolf Arne Kjellby, Linga Reddy Cenkeramaddi, Thor Eirik Johnsrud, Geir Jevne, Svein Erik Løtveit, B. Beferull-Lozano, Soumya Joshi
This paper presents the design and prototype implementation of long-range self-powered wireless IoT devices using nRF52840 based on energy harvesting. The test-bed is setup in both star and multi-hop configurations with optimized custom protocols. In both network configurations, nodes consume less power than what is harvested in an indoor light environment using a small 0.36W rated monocrystalline solar panel. The average power by which the battery was charged during the test was 941.94µW in an indoor environment. Nodes are able to operate for 12 months using a fully charged 120mAh rated rechargeable coin cell battery with 55s transmission interval. Based on measurements, a line of sight range of 1.8km is obtained using coded transmissions. Sensors of temperature, relative humidity and visible light are integrated into the nodes.
{"title":"Design and Prototype Implementation of Long-Range Self-Powered Wireless IoT Devices","authors":"Rolf Arne Kjellby, Linga Reddy Cenkeramaddi, Thor Eirik Johnsrud, Geir Jevne, Svein Erik Løtveit, B. Beferull-Lozano, Soumya Joshi","doi":"10.1109/ISES.2018.00054","DOIUrl":"https://doi.org/10.1109/ISES.2018.00054","url":null,"abstract":"This paper presents the design and prototype implementation of long-range self-powered wireless IoT devices using nRF52840 based on energy harvesting. The test-bed is setup in both star and multi-hop configurations with optimized custom protocols. In both network configurations, nodes consume less power than what is harvested in an indoor light environment using a small 0.36W rated monocrystalline solar panel. The average power by which the battery was charged during the test was 941.94µW in an indoor environment. Nodes are able to operate for 12 months using a fully charged 120mAh rated rechargeable coin cell battery with 55s transmission interval. Based on measurements, a line of sight range of 1.8km is obtained using coded transmissions. Sensors of temperature, relative humidity and visible light are integrated into the nodes.","PeriodicalId":447663,"journal":{"name":"2018 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127874147","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Security evaluation of third-party cryptographic Soft/Hard IP (Intellectual Property) core is often ignored due to several reasons including, lack of awareness about its adversity, lack of knowledge about validation methodology or considering security as a byproduct. Particularly, the security validation of bought-out Hardware IP core is important before being deployed in particle means. In this paper, we present Look-Up-Table (LUT) based unrolled implementation of low latency cipher, PRINCE as an hard IP core and show how the susceptible implementation (nested and flexible placement of IP cores) can be experimentally exploited to reveal secret key in FPGA using power analysis attack. Such vulnerability in constrained devices, Internet-of-Things(IoT), causes serious threats in cyber physical system.
{"title":"Crypto Primitives IPCore Implementation Susceptibility in Cyber Physical System","authors":"Dillibabu Shanmugam, S. Annadurai","doi":"10.1109/ises.2018.00062","DOIUrl":"https://doi.org/10.1109/ises.2018.00062","url":null,"abstract":"Security evaluation of third-party cryptographic Soft/Hard IP (Intellectual Property) core is often ignored due to several reasons including, lack of awareness about its adversity, lack of knowledge about validation methodology or considering security as a byproduct. Particularly, the security validation of bought-out Hardware IP core is important before being deployed in particle means. In this paper, we present Look-Up-Table (LUT) based unrolled implementation of low latency cipher, PRINCE as an hard IP core and show how the susceptible implementation (nested and flexible placement of IP cores) can be experimentally exploited to reveal secret key in FPGA using power analysis attack. Such vulnerability in constrained devices, Internet-of-Things(IoT), causes serious threats in cyber physical system.","PeriodicalId":447663,"journal":{"name":"2018 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128018125","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
IPv6 Routing Protocol for Low Power and Lossy Networks (RPL) proposed by Internet Engineering Task Force (IETF) has been adopted to suit Internet of Things (IoT) requirements. However, both the storing and non-storing modes of operation for RPL brings about certain limitations. In case of storing mode of RPL, if an intermediate node along the routing path overflows, new nodes become unreachable whereas, for the non-storing mode of RPL, the entire routing topology is only saved at the root node resulting in increased congestion near the root. Therefore, in this paper, we propose a low overhead Adaptive RPL (ARPL) algorithm which allows flexibility between storing and non-storing modes of operation. Here, the benefits of both the operating modes of RPL are utilized to avoid additional control message exchange, thereby making network resource-aware. We also observe that ARPL performs better than one state-of-the-art competitor in terms of storage and memory overflow by allowing the said flexibility of switching modes. Finally, we simulate ARPL using Cooja in Contiki operating system to evaluate the performance of ARPL. The simulation results show that ARPL achieves higher packet delivery ratio (PDR) in downward communication (e.g. query mode) while keeping convergence time same. It also shows that even in the mixed mode more than 90% nodes are operating in storing mode which improves Point to Point (P2P) communication with reduced traffic near the root thus allowing nodes to save energy.
采用IETF (Internet Engineering Task Force)提出的IPv6 route Protocol for Low Power and Lossy Networks (RPL)，以适应物联网的需求。然而，RPL的存储和非存储操作方式都带来了一定的局限性。对于RPL的存储模式，如果路由路径上的一个中间节点溢出，将导致新节点不可达，而对于RPL的非存储模式，整个路由拓扑只保存在根节点，导致根附近的拥塞增加。因此，在本文中，我们提出了一种低开销的自适应RPL (ARPL)算法，该算法允许存储和非存储操作模式之间的灵活性。这里，利用RPL两种操作模式的优点来避免额外的控制消息交换，从而实现网络资源感知。我们还观察到，通过允许上述切换模式的灵活性，ARPL在存储和内存溢出方面比一个最先进的竞争对手表现得更好。最后，我们在Contiki操作系统上使用Cooja对ARPL进行了仿真，以评估ARPL的性能。仿真结果表明，在保持收敛时间不变的情况下，ARPL在向下通信(如查询模式)中实现了更高的分组投递率(PDR)。它还表明，即使在混合模式下，也有90%以上的节点以存储模式运行，这改善了点对点(P2P)通信，减少了根附近的流量，从而使节点节省了能量。
{"title":"ARPL: Supporting Adaptive Mixing of RPL Modes to Overcome Memory Overflow","authors":"Kunal Vyas, Jayasree Sengupta, S. Bit","doi":"10.1109/ISES.2018.00035","DOIUrl":"https://doi.org/10.1109/ISES.2018.00035","url":null,"abstract":"IPv6 Routing Protocol for Low Power and Lossy Networks (RPL) proposed by Internet Engineering Task Force (IETF) has been adopted to suit Internet of Things (IoT) requirements. However, both the storing and non-storing modes of operation for RPL brings about certain limitations. In case of storing mode of RPL, if an intermediate node along the routing path overflows, new nodes become unreachable whereas, for the non-storing mode of RPL, the entire routing topology is only saved at the root node resulting in increased congestion near the root. Therefore, in this paper, we propose a low overhead Adaptive RPL (ARPL) algorithm which allows flexibility between storing and non-storing modes of operation. Here, the benefits of both the operating modes of RPL are utilized to avoid additional control message exchange, thereby making network resource-aware. We also observe that ARPL performs better than one state-of-the-art competitor in terms of storage and memory overflow by allowing the said flexibility of switching modes. Finally, we simulate ARPL using Cooja in Contiki operating system to evaluate the performance of ARPL. The simulation results show that ARPL achieves higher packet delivery ratio (PDR) in downward communication (e.g. query mode) while keeping convergence time same. It also shows that even in the mixed mode more than 90% nodes are operating in storing mode which improves Point to Point (P2P) communication with reduced traffic near the root thus allowing nodes to save energy.","PeriodicalId":447663,"journal":{"name":"2018 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131884347","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Vehicular ad-hoc Network(VANET) helps various stakeholders like passengers, traffic management team, manufacturers, owners, drivers etc to access important information using a highly dynamic mobile network. Restricting unauthenticated users from free information sharing is a crucial challenge. In this paper we propose a dynamic lightweight biometric-based authentication protocol for vehicle-to-vehicle (V2V) communication networks where user after successful registration can directly login from any local mobile terminal and access his /her services/information directly from the authentication servers. We have done the security analysis of our scheme and prove that our scheme provides user anonymity, location privacy, mutual authentication to prevent spoofing attacks and resistance against forgery, modification and replay attacks. We also compare the efficiency of our scheme with other related schemes and show that our authentication scheme is more secure and performs faster than other schemes available in the literature.
{"title":"Secure Biometric-Based Authentication Protocol for Vehicular Ad-Hoc Network","authors":"M. Ismail., Santanu Chatterjee, J. Sing","doi":"10.1109/ises.2018.00057","DOIUrl":"https://doi.org/10.1109/ises.2018.00057","url":null,"abstract":"Vehicular ad-hoc Network(VANET) helps various stakeholders like passengers, traffic management team, manufacturers, owners, drivers etc to access important information using a highly dynamic mobile network. Restricting unauthenticated users from free information sharing is a crucial challenge. In this paper we propose a dynamic lightweight biometric-based authentication protocol for vehicle-to-vehicle (V2V) communication networks where user after successful registration can directly login from any local mobile terminal and access his /her services/information directly from the authentication servers. We have done the security analysis of our scheme and prove that our scheme provides user anonymity, location privacy, mutual authentication to prevent spoofing attacks and resistance against forgery, modification and replay attacks. We also compare the efficiency of our scheme with other related schemes and show that our authentication scheme is more secure and performs faster than other schemes available in the literature.","PeriodicalId":447663,"journal":{"name":"2018 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115951992","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Alternative materials such as Alumina (Al2O3) and Polyimide (PI) have lower thermal conductivity than Si/Si3N4, hence with these materials, low power consumption can be attained even with a thicker membrane. This paper first attempts to determine the convection coefficient by constructing a CFD analysis of microhotplate and then employs the obtained results to investigate the performance of microhotplates with alternative materials, like PI or Al2O3 either as a single material membrane or composite membrane. For attaining same operating temperature (694K) with single material membrane, PI membrane resulted in a lower power consumption compared to Al2O3 membrane. Further, it is found that composite membrane of PI and Al2O3 can bring advantages of both the materials and among the various simulated composite membranes, PI/Al2O3 ( 1/1µm) membrane offers the best response time and thermal uniformity with a power consumption of 19.41mW.
{"title":"Performance Evaluation of Square Microhotplate with Alternative Membrane Materials","authors":"G. Saxena","doi":"10.1109/ISES.2018.00020","DOIUrl":"https://doi.org/10.1109/ISES.2018.00020","url":null,"abstract":"Alternative materials such as Alumina (Al2O3) and Polyimide (PI) have lower thermal conductivity than Si/Si3N4, hence with these materials, low power consumption can be attained even with a thicker membrane. This paper first attempts to determine the convection coefficient by constructing a CFD analysis of microhotplate and then employs the obtained results to investigate the performance of microhotplates with alternative materials, like PI or Al2O3 either as a single material membrane or composite membrane. For attaining same operating temperature (694K) with single material membrane, PI membrane resulted in a lower power consumption compared to Al2O3 membrane. Further, it is found that composite membrane of PI and Al2O3 can bring advantages of both the materials and among the various simulated composite membranes, PI/Al2O3 ( 1/1µm) membrane offers the best response time and thermal uniformity with a power consumption of 19.41mW.","PeriodicalId":447663,"journal":{"name":"2018 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126923922","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Reliability of electronic devices in sub-nanometer technology scale has become a major concern. However, demand for battery operated low power, high performance devices necessitates technology scaling. To meet these contradictory design goals optimization and reliability must be performed simultaneously. This paper proposes by integrating compiler driven transformation and simulated annealing based optimization process for generating optimized low cost transient fault tolerant DSP core. The case study on FIR filter shows improved performance (in terms of reduced area and delay) of proposed approach in comparison to state-of-art transient fault tolerant approach.
{"title":"Integrating Compiler Driven Transformation and Simulated Annealing Based Floorplan for Optimized Transient Fault Tolerant DSP Cores","authors":"A. Sengupta, Deepak Kachave","doi":"10.1109/ises.2018.00014","DOIUrl":"https://doi.org/10.1109/ises.2018.00014","url":null,"abstract":"Reliability of electronic devices in sub-nanometer technology scale has become a major concern. However, demand for battery operated low power, high performance devices necessitates technology scaling. To meet these contradictory design goals optimization and reliability must be performed simultaneously. This paper proposes by integrating compiler driven transformation and simulated annealing based optimization process for generating optimized low cost transient fault tolerant DSP core. The case study on FIR filter shows improved performance (in terms of reduced area and delay) of proposed approach in comparison to state-of-art transient fault tolerant approach.","PeriodicalId":447663,"journal":{"name":"2018 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126593932","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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