With the aggressive scaling of the VLSI technology, Networks-on-Chip (NoCs) are becoming more susceptible to faults. Therefore, designing reliable and efficient NoCs is of significant importance. The rerouting approach which is employed in most of the fault-tolerant methods causes the network performance to degrade considerably due to taking longer paths and creating hotspots around the faults. Moreover, they cannot adapt to the dynamic traffic distribution in the network. Considering the increasing demands for real-time systems, the necessity for designing reconfigurable and robust NoCs is even more pronounced. In this paper, a dynamically reconfigurable technique is proposed to address fault-tolerance and minimal routing in mesh NoCs. To accomplish this goal, the router architecture is modified to enable the frequently communicating nodes to bypass the faulty router and communicate through shorter paths. Thus, not only the rerouting is minimized, the connectivity of the network is maintained in the vicinity of faults. The experimental results validate the performance and reliability of the proposed technique with a small hardware overhead.
{"title":"Traffic-aware reconfigurable architecture for fault-tolerant 2D mesh NoCs","authors":"Poona Bahrebar, D. Stroobandt","doi":"10.1145/3267419.3267423","DOIUrl":"https://doi.org/10.1145/3267419.3267423","url":null,"abstract":"With the aggressive scaling of the VLSI technology, Networks-on-Chip (NoCs) are becoming more susceptible to faults. Therefore, designing reliable and efficient NoCs is of significant importance. The rerouting approach which is employed in most of the fault-tolerant methods causes the network performance to degrade considerably due to taking longer paths and creating hotspots around the faults. Moreover, they cannot adapt to the dynamic traffic distribution in the network. Considering the increasing demands for real-time systems, the necessity for designing reconfigurable and robust NoCs is even more pronounced. In this paper, a dynamically reconfigurable technique is proposed to address fault-tolerance and minimal routing in mesh NoCs. To accomplish this goal, the router architecture is modified to enable the frequently communicating nodes to bypass the faulty router and communicate through shorter paths. Thus, not only the rerouting is minimized, the connectivity of the network is maintained in the vicinity of faults. The experimental results validate the performance and reliability of the proposed technique with a small hardware overhead.","PeriodicalId":447904,"journal":{"name":"SIGBED Rev.","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-08-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121871304","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Safety-critical Ethernet-based networks are receiving significant attention in avionics, automotive and industrial domains. Time-Triggered Ethernet (TTEthernet AS6802) provides safety-critical transmission guarantees via a high priority, time-triggered (TT) traffic class and a lower priority, rate-constrained (RC) traffic class. TT traffic is transmitted between synchronized nodes of a TTEthernet network in offline scheduled TT transmission windows. In this work, we analyze the impact of different placement strategies for these TT transmission windows on end-to-end delay and jitter of RC messages on the same path segment. We show that, depending on the placement of TT transmission windows in a schedule, the end-to-end delay and jitter of RC messages can vary significantly. We further introduce link-based offsets, a new placement strategy for TT transmission windows which allows to reduce the impact of TT transmission windows on RC traffic. In this strategy offsets are applied to all TT transmission windows in a physical link schedule to reduce the amount of time that an RC message on the same physical link is delayed by TT traffic. The link-based offsets strategy can be implemented in the TTEthernet scheduler and does not require hardware modifications. We show that the link-based offset strategy can reduce the end-to-end delay and jitter of RC traffic, and evaluate our claims using an OMNET++ simulation.
{"title":"Impact of time-triggered transmission window placement on rate-constrained traffic in TTEthernet networks","authors":"Florian Heilmann, G. Fohler","doi":"10.1145/3267419.3267420","DOIUrl":"https://doi.org/10.1145/3267419.3267420","url":null,"abstract":"Safety-critical Ethernet-based networks are receiving significant attention in avionics, automotive and industrial domains. Time-Triggered Ethernet (TTEthernet AS6802) provides safety-critical transmission guarantees via a high priority, time-triggered (TT) traffic class and a lower priority, rate-constrained (RC) traffic class. TT traffic is transmitted between synchronized nodes of a TTEthernet network in offline scheduled TT transmission windows. In this work, we analyze the impact of different placement strategies for these TT transmission windows on end-to-end delay and jitter of RC messages on the same path segment. We show that, depending on the placement of TT transmission windows in a schedule, the end-to-end delay and jitter of RC messages can vary significantly. We further introduce link-based offsets, a new placement strategy for TT transmission windows which allows to reduce the impact of TT transmission windows on RC traffic. In this strategy offsets are applied to all TT transmission windows in a physical link schedule to reduce the amount of time that an RC message on the same physical link is delayed by TT traffic. The link-based offsets strategy can be implemented in the TTEthernet scheduler and does not require hardware modifications. We show that the link-based offset strategy can reduce the end-to-end delay and jitter of RC traffic, and evaluate our claims using an OMNET++ simulation.","PeriodicalId":447904,"journal":{"name":"SIGBED Rev.","volume":"330 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-08-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115970040","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The recently published IEEE 802.1Qbv standard specifies enhancements for providing real-time communication guarantees for time-triggered flows while also handling best-effort traffic in a converged Ethernet network. The enhancements include a programmable time-based gating mechanism for stipulating which of the queues of an egress port are available for transmission at any given point of time. By appropriately programming (opening and closing) these gates, the traversal of packets through the network can be controlled to precisely follow a precomputed schedule that satisfies the timing constraints of the time-triggered flows. Computing such transmission schedules requires routing of the flows in the first step, followed by the computation of gate schedules for the flows along their respective routes. So far off-the-shelf algorithms like shortest path routing, which optimize the number of hops over which flows are routed, have been used for computing routes for the time-triggered traffic. In this paper, we explore how the routing of time-triggered flows affects their schedulability. Moreover, we identify additional parameters that must be considered while routing time-triggered traffic and propose ILP-based algorithms for the purpose. Our evaluations show that the proposed routing algorithms could improve the slack in the computed schedules by upto 60 % and 30 % compared to shortest path routing and equal cost multi-pathing (ECMP), respectively, and, thus, increase the capacity of the network to accommodate more time-triggered traffic.
{"title":"Routing algorithms for IEEE802.1Qbv networks","authors":"N. Nayak, Frank Dürr, K. Rothermel","doi":"10.1145/3267419.3267421","DOIUrl":"https://doi.org/10.1145/3267419.3267421","url":null,"abstract":"The recently published IEEE 802.1Qbv standard specifies enhancements for providing real-time communication guarantees for time-triggered flows while also handling best-effort traffic in a converged Ethernet network. The enhancements include a programmable time-based gating mechanism for stipulating which of the queues of an egress port are available for transmission at any given point of time. By appropriately programming (opening and closing) these gates, the traversal of packets through the network can be controlled to precisely follow a precomputed schedule that satisfies the timing constraints of the time-triggered flows. Computing such transmission schedules requires routing of the flows in the first step, followed by the computation of gate schedules for the flows along their respective routes. So far off-the-shelf algorithms like shortest path routing, which optimize the number of hops over which flows are routed, have been used for computing routes for the time-triggered traffic. In this paper, we explore how the routing of time-triggered flows affects their schedulability. Moreover, we identify additional parameters that must be considered while routing time-triggered traffic and propose ILP-based algorithms for the purpose. Our evaluations show that the proposed routing algorithms could improve the slack in the computed schedules by upto 60 % and 30 % compared to shortest path routing and equal cost multi-pathing (ECMP), respectively, and, thus, increase the capacity of the network to accommodate more time-triggered traffic.","PeriodicalId":447904,"journal":{"name":"SIGBED Rev.","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-08-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128081225","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
To support mixed-criticality applications, the AFDX may integrate multiple traffic classes: Safety-Critical Traffic (SCT) with hard realtime constraints, Rate-Constrained (RC) traffic requiring bounded latencies and Best Effort (BE) traffic with no delivery constraints. These traffic classes are managed based on a Non-Preemptive Strict Priority (NP-SP) Scheduler, where the highest priority traffic (SCT) is shaped with a Burst Limiting Shaper (BLS). The latter has been defined by the Time Sensitive Networking (TSN) task group to limit the impact of high priority flows on lower priority ones. This paper proposes two bandwidth reservation methods for BLS shapers in AFDX networks. The proposed methods are evaluated on a realistic AFDX configuration. Results show their efficiency to noticeably enhance the RC delay bounds and the SCT schedulability, in comparison to an intuitive method.
{"title":"Performance enhancement of extended AFDX via bandwidth reservation for TSN/BLS shapers","authors":"A. Finzi, A. Mifdaoui, F. Frances, E. Lochin","doi":"10.1145/3314206.3314209","DOIUrl":"https://doi.org/10.1145/3314206.3314209","url":null,"abstract":"To support mixed-criticality applications, the AFDX may integrate multiple traffic classes: Safety-Critical Traffic (SCT) with hard realtime constraints, Rate-Constrained (RC) traffic requiring bounded latencies and Best Effort (BE) traffic with no delivery constraints. These traffic classes are managed based on a Non-Preemptive Strict Priority (NP-SP) Scheduler, where the highest priority traffic (SCT) is shaped with a Burst Limiting Shaper (BLS). The latter has been defined by the Time Sensitive Networking (TSN) task group to limit the impact of high priority flows on lower priority ones. This paper proposes two bandwidth reservation methods for BLS shapers in AFDX networks. The proposed methods are evaluated on a realistic AFDX configuration. Results show their efficiency to noticeably enhance the RC delay bounds and the SCT schedulability, in comparison to an intuitive method.","PeriodicalId":447904,"journal":{"name":"SIGBED Rev.","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127069532","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
D. Chattopadhyay, Abinash Samantaray, Anupam Datta
Smart home implementation in IoT involves practical challenges of management and scalability of connecting various non IP end-devices i.e. sensors and actuators behind the connnected home gateway. While there are separate standards for interaction between IoT service to home gateway and gateway to variety of end-devices there remains disconnect regarding how this two ends meet in an adaptable and scalable way. In this paper we present an light-weight, loosly coupled architecture for IoT smart home gateway whereby end-devices can be added dynamically on the gateway without disrupting long haul communication between IoT cloud service and gateway. The gateway agent exchanges data through sensor-block or actuator-block with end-devices via device microagents and the protocol specific read-write task is offloaded to individual device microagent. This hybrid approach to integrate MQTT pub/sub flexibility with LWM2M RESTful adaptability results in a design of plug-n-play modular agent architecture for home gateway management in IoT applications.
{"title":"Device microagent for IoT home gateway: a lightweight plug-n-play architecture","authors":"D. Chattopadhyay, Abinash Samantaray, Anupam Datta","doi":"10.1145/3231535.3231537","DOIUrl":"https://doi.org/10.1145/3231535.3231537","url":null,"abstract":"Smart home implementation in IoT involves practical challenges of management and scalability of connecting various non IP end-devices i.e. sensors and actuators behind the connnected home gateway. While there are separate standards for interaction between IoT service to home gateway and gateway to variety of end-devices there remains disconnect regarding how this two ends meet in an adaptable and scalable way. In this paper we present an light-weight, loosly coupled architecture for IoT smart home gateway whereby end-devices can be added dynamically on the gateway without disrupting long haul communication between IoT cloud service and gateway. The gateway agent exchanges data through sensor-block or actuator-block with end-devices via device microagents and the protocol specific read-write task is offloaded to individual device microagent. This hybrid approach to integrate MQTT pub/sub flexibility with LWM2M RESTful adaptability results in a design of plug-n-play modular agent architecture for home gateway management in IoT applications.","PeriodicalId":447904,"journal":{"name":"SIGBED Rev.","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128080404","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Smartphones or in general handhelds commonly used for indoor localization purposes are not a viable option in places where people do not carry them all the time - for example, home and office. Alternatively, wearable devices can partially solve this problem but have many limitations with respect to power supply, processing capability, and availability of sensors. These issues prevent the adoption of many common handheld localization solutions. In this work, we present PErvasive Localization Engine (PELE), a distributed localization system that uses wearable and handheld jointly to address the above drawbacks. Using only magnetometer, accelerometer, and Bluetooth radio, localization is performed by means of a particle filter. In addition, a dynamic handoff mechanism is presented, which uses the wearable only when it is necessary, thus reducing energy consumption on the wearable without affecting the desired localization accuracy. Evaluating the system with ten participants, we achieve a localization accuracy of 90.31 % in an indoor environment spanning about 320 m2.
{"title":"Where is PELE?: pervasive localization using wearable and handheld devices","authors":"L. H. John, Chayan Sarkar, R. V. Prasad","doi":"10.1145/3231535.3231536","DOIUrl":"https://doi.org/10.1145/3231535.3231536","url":null,"abstract":"Smartphones or in general handhelds commonly used for indoor localization purposes are not a viable option in places where people do not carry them all the time - for example, home and office. Alternatively, wearable devices can partially solve this problem but have many limitations with respect to power supply, processing capability, and availability of sensors. These issues prevent the adoption of many common handheld localization solutions. In this work, we present PErvasive Localization Engine (PELE), a distributed localization system that uses wearable and handheld jointly to address the above drawbacks. Using only magnetometer, accelerometer, and Bluetooth radio, localization is performed by means of a particle filter. In addition, a dynamic handoff mechanism is presented, which uses the wearable only when it is necessary, thus reducing energy consumption on the wearable without affecting the desired localization accuracy. Evaluating the system with ten participants, we achieve a localization accuracy of 90.31 % in an indoor environment spanning about 320 m2.","PeriodicalId":447904,"journal":{"name":"SIGBED Rev.","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134442899","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
T. V. Prabhakar, V. Shashidhar, G. Meghana, R. V. Prasad, Garani Vittal Pranavendra
Internet of Things is bringing multiple domains and multiple avenues to connect anything and everything. It mainly uses RF connectivity. However, recently visible light communication (VLC) is also being explored. VLC has the properties that are unique with respect to the privacy and security that it provides. Though the transmission is of broadcast in nature the receiver needs to be in the vicinity of the transmitter, thus providing secure communications. Further, when low power receivers need to be constructed, it is important to harness energy from transmission itself. In this article we propose a novel design for a receiver to be used in VLC for embedded systems. The setup works, using a small solar panel (2mm x 2mm) as a medium to simultaneously harvest incident light energy and receive data bit streams. The LED source was modulated using On-Off Keying. The receiver works for close range communications. The results in this paper show experimental evaluation of the system. We could detect the signals from the source using harvested energy from the same transmission.
物联网带来了多个领域和多种途径来连接任何东西。它主要使用射频连接。然而，最近可见光通信(VLC)也在探索中。VLC在其提供的隐私和安全性方面具有独特的属性。虽然传输本质上是广播，但接收器需要在发射器附近，从而提供安全的通信。此外，当需要构建低功率接收器时，重要的是利用传输本身的能量。在本文中，我们提出了一种用于嵌入式系统的VLC接收机的新设计。该装置使用一个小型太阳能电池板(2mm x 2mm)作为介质，同时收集入射光能和接收数据比特流。LED光源采用开关键控调制。接收器用于近距离通信。最后给出了该系统的实验结果。我们可以利用从同一传输中收集的能量来探测来自源的信号。
{"title":"Zero energy visible light communication receiver for embedded applications","authors":"T. V. Prabhakar, V. Shashidhar, G. Meghana, R. V. Prasad, Garani Vittal Pranavendra","doi":"10.1145/3231535.3231540","DOIUrl":"https://doi.org/10.1145/3231535.3231540","url":null,"abstract":"Internet of Things is bringing multiple domains and multiple avenues to connect anything and everything. It mainly uses RF connectivity. However, recently visible light communication (VLC) is also being explored. VLC has the properties that are unique with respect to the privacy and security that it provides. Though the transmission is of broadcast in nature the receiver needs to be in the vicinity of the transmitter, thus providing secure communications. Further, when low power receivers need to be constructed, it is important to harness energy from transmission itself. In this article we propose a novel design for a receiver to be used in VLC for embedded systems. The setup works, using a small solar panel (2mm x 2mm) as a medium to simultaneously harvest incident light energy and receive data bit streams. The LED source was modulated using On-Off Keying. The receiver works for close range communications. The results in this paper show experimental evaluation of the system. We could detect the signals from the source using harvested energy from the same transmission.","PeriodicalId":447904,"journal":{"name":"SIGBED Rev.","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126345216","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In the era of the Internet of Things (IoT), millions of devices and embedded platforms based on low-cost and limited resources microcontroller units (MCUs) will be used in continuous operation. Even if over-the-air firmware update is today a common feature, many applications might require not to reboot or to support hardware resource sharing. In such a context stop, update and reboot the platform is unpractical and dynamic loading of new user code is required. This in turn requires mechanisms to protect the MCU hardware resources and the continuously executing system tasks from uncontrolled perturbation caused by new user code being dynamically loaded. In this paper, we present a framework which provides a lightweight virtualization of the IO and platform peripherals and permits the dynamic loading of new user code. The aim of this work is to support critical isolation features typical of virtualization-ready CPUs on low-cost low-power microcontrollers with no MMU (Memory Management Unit), IOMMU or dedicated instruction extensions. Our approach only leverages the Memory Protection Unit (MPU), which is generally available in all ARM Cortex-M3 and Cortex-M4 microcontrollers. Experimental evaluations demonstrate not only the feasibility, but also the really low impact of the proposed framework in terms of memory requirements and runtime overhead.
{"title":"Lightweight IO virtualization on MPU enabled microcontrollers","authors":"F. Paci, D. Brunelli, L. Benini","doi":"10.1145/3199610.3199617","DOIUrl":"https://doi.org/10.1145/3199610.3199617","url":null,"abstract":"In the era of the Internet of Things (IoT), millions of devices and embedded platforms based on low-cost and limited resources microcontroller units (MCUs) will be used in continuous operation. Even if over-the-air firmware update is today a common feature, many applications might require not to reboot or to support hardware resource sharing. In such a context stop, update and reboot the platform is unpractical and dynamic loading of new user code is required. This in turn requires mechanisms to protect the MCU hardware resources and the continuously executing system tasks from uncontrolled perturbation caused by new user code being dynamically loaded. In this paper, we present a framework which provides a lightweight virtualization of the IO and platform peripherals and permits the dynamic loading of new user code. The aim of this work is to support critical isolation features typical of virtualization-ready CPUs on low-cost low-power microcontrollers with no MMU (Memory Management Unit), IOMMU or dedicated instruction extensions. Our approach only leverages the Memory Protection Unit (MPU), which is generally available in all ARM Cortex-M3 and Cortex-M4 microcontrollers. Experimental evaluations demonstrate not only the feasibility, but also the really low impact of the proposed framework in terms of memory requirements and runtime overhead.","PeriodicalId":447904,"journal":{"name":"SIGBED Rev.","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126237795","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The Open Group Future Airborne Capability Environment (FACE™) Consortium has developed a reference architecture and standard for real-time embedded avionics systems. The FACE Technical Standard defines required capabilities for real-time operating systems (RTOS), portable components, and a shared data model to facilitate information exchange between components. FACE RTOS requirements are based on ARINC 653 and POSIX 1003.1b with tailoring to address the safety and security needs of avionics systems. Deos is a safety-certified RTOS that supports ARINC 653 but not POSIX. In contrast, RTEMS is an open source RTOS that supports POSIX but not ARINC 653. Integrating a paravirtualized RTEMS with Deos combines the strengths of both and provides a path to conformance with the FACE Safety Base operating system profile. This paper presents the FACE operating system profiles and discusses the technical challenges of the paravirtualization and integration effort.
{"title":"Aligning Deos and RTEMS with the FACE safety base operating system profile","authors":"Gedare Bloom, J. Sherrill, G. Gilliland","doi":"10.1145/3199610.3199612","DOIUrl":"https://doi.org/10.1145/3199610.3199612","url":null,"abstract":"The Open Group Future Airborne Capability Environment (FACE™) Consortium has developed a reference architecture and standard for real-time embedded avionics systems. The FACE Technical Standard defines required capabilities for real-time operating systems (RTOS), portable components, and a shared data model to facilitate information exchange between components. FACE RTOS requirements are based on ARINC 653 and POSIX 1003.1b with tailoring to address the safety and security needs of avionics systems. Deos is a safety-certified RTOS that supports ARINC 653 but not POSIX. In contrast, RTEMS is an open source RTOS that supports POSIX but not ARINC 653. Integrating a paravirtualized RTEMS with Deos combines the strengths of both and provides a path to conformance with the FACE Safety Base operating system profile. This paper presents the FACE operating system profiles and discusses the technical challenges of the paravirtualization and integration effort.","PeriodicalId":447904,"journal":{"name":"SIGBED Rev.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131998225","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
C. Bolchini, Stefano Cherubin, Gianluca Durelli, Simone Libutti, A. Miele, M. Santambrogio
Nowadays Heterogeneous System Architectures (HSAs) are becoming very attractive in the embedded and mobile markets thanks to the possibility to select the best computational resource among the available compute units to optimize the performance per Watt figure of merit. In this scenario, OpenCL is becoming the standard paradigm for heterogeneous computing supporting the programming of all types of units with a single abstraction level. However, the decision of the resource to use together with its architectural tuning is still left to the programmer; this issue is even more exacerbated when considering the fact that the choice depends also on the actual conditions in which the system is operating. This work aims at proposing a runtime controller, integrated in Linux Operating System (OS), for optimizing the power efficiency of a running OpenCL application deciding the system configuration. Our experimental results over a set of applications from the Polybench suite on the Odroid XU3 board show that our controller is able to obtain a power efficiency of more than 90% of the one achievable via offline profiling.
{"title":"A runtime controller for openCL applications on heterogeneous system architectures","authors":"C. Bolchini, Stefano Cherubin, Gianluca Durelli, Simone Libutti, A. Miele, M. Santambrogio","doi":"10.1145/3199610.3199614","DOIUrl":"https://doi.org/10.1145/3199610.3199614","url":null,"abstract":"Nowadays Heterogeneous System Architectures (HSAs) are becoming very attractive in the embedded and mobile markets thanks to the possibility to select the best computational resource among the available compute units to optimize the performance per Watt figure of merit. In this scenario, OpenCL is becoming the standard paradigm for heterogeneous computing supporting the programming of all types of units with a single abstraction level. However, the decision of the resource to use together with its architectural tuning is still left to the programmer; this issue is even more exacerbated when considering the fact that the choice depends also on the actual conditions in which the system is operating. This work aims at proposing a runtime controller, integrated in Linux Operating System (OS), for optimizing the power efficiency of a running OpenCL application deciding the system configuration. Our experimental results over a set of applications from the Polybench suite on the Odroid XU3 board show that our controller is able to obtain a power efficiency of more than 90% of the one achievable via offline profiling.","PeriodicalId":447904,"journal":{"name":"SIGBED Rev.","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124065182","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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