Pub Date : 2020-07-10DOI: 10.1147/JRD.2020.3008101
A. T. Sofia;M. Klein;B. D. Stilwell;S. Weishaupt;Q. Y. Chen;R. W. St John
IBM z15 replaces the former I/O attached accelerator for DEFLATE, zEnterprise Data Compression (zEDC) Express, with an on-chip accelerator that can be synchronously accessed via an instruction. The integration of this new accelerator in the z/OS software stack has been designed to maintain a consistent user experience for software packages that used the previous technology, while still allowing the enhanced aspects of the new technology to deliver the additional value. Two different access paths for DEFLATE have been created in z/OS to accomplish both goals. For user space programs that utilize the zlib API, z/OS directly executes the instruction synchronously, which avoids overhead and reduces latency. Authorized users continue to utilize existing infrastructure and have the Service Assist Processors (SAP) perform compression in an asynchronous fashion on their behalf. The SAP receives information about the requested task via a thin and efficient communication path to z/OS, invokes the instruction in a well-defined fashion, and returns the result to z/OS.
This article describes the integration of DEFLATE acceleration in z15 into the z/OS software stack in both synchronous and asynchronous mode and presents the resulting performance for selected workloads.
IBM z15用一个可以通过指令同步访问的片上加速器取代了DEFLATE以前的I/O连接加速器zEnterprise Data Compression（zEDC）Express。在z/OS软件堆栈中集成这种新加速器的目的是为使用以前技术的软件包保持一致的用户体验，同时仍然允许新技术的增强方面提供额外的价值。为了实现这两个目标，在z/OS中为DEFLATE创建了两个不同的访问路径。对于使用zlib API的用户空间程序，z/OS直接同步执行指令，避免了开销并减少了延迟。授权用户继续利用现有的基础设施，并让服务辅助处理器（SAP）以异步方式代表他们执行压缩。SAP通过到z/OS的精简高效的通信路径接收有关请求任务的信息，以定义良好的方式调用指令，并将结果返回到z/OS。本文描述了在同步和异步模式下将z15中的DEFLATE加速集成到z/OS软件堆栈中，并介绍了所选工作负载的最终性能。
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Pub Date : 2020-07-10DOI: 10.1147/JRD.2020.3008111
A. Bieswanger;A. Maier;C. Mayer;H. Shah;J. Candee
The IBM z15 is built to support users to deliver mission-critical workloads and services in a hybrid cloud environment. In this article, we describe the new capabilities that are intended to fit the platform into private and public cloud frameworks. This work is rooted in the broader IBM cloud strategy and point-of-view and based on ongoing efforts to identify and address critical pain-points for a key set of enterprise clients through applying Enterprise Design Thinking practices. By outlining the hardware, firmware, and software support added for z15, we show how we have been able to integrate the IBM Z platform into the IBM Cloud infrastructure. We also discuss how cloud-focused technologies and tooling enable users to access, deploy, and lifecycle manage z/OS resources and services for a seamless cloud experience.
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Pub Date : 2020-07-10DOI: 10.1147/JRD.2020.3008102
D. H. Surman;S. Lederer;D. B. Petersen;M. Gubitz;P. J. Relson
System Recovery Boost on the IBM z15 server expedites planned operating system shutdown, either planned or unplanned operating system initial program load (IPL), middleware and workload restart and recovery, and the client workload execution that follows, to accelerate service restoration around downtime. It does this by providing limited-duration “boost periods” that deliver significant usable additional processor capacity and parallelism. On subcapacity machine models, it provides a boost in processor speed by running the general-purpose processors at full-capacity speed, for the boosting LPARs only, and only during the boost periods. It makes all available processing capacity defined to the boosting images available to process any kind of work, “blurring” general-purpose processor and specialty processor capacity together during the boost period. System Recovery Boost also expedites and parallelizes processor reconfiguration actions that may be part of the client's overall restart and recovery process, as orchestrated by Geographically Dispersed Parallel Sysplex (GDPS) automation. Optionally, System Recovery Boost provides the ability to add additional processor capacity from the client's unused “dark cores” via activation of a new type of temporary capacity record. All of this can be accomplished without increasing the client's IBM software billing costs or the processor consumption associated with the client's workload during these boost periods.
IBM z15服务器上的System Recovery Boost加速了计划中的操作系统关闭、计划中的或计划外的操作系统初始程序负载(IPL)、中间件和工作负载重启和恢复，以及随后的客户机工作负载执行，从而加速了停机前后的服务恢复。它通过提供持续时间有限的“提升周期”来实现这一点，提升周期提供了大量可用的额外处理器容量和并行性。在次容量机器模型上，它通过以全容量速度运行通用处理器来提高处理器速度，这只适用于增强lpar，并且只在增强期间。它使所有定义为增强图像的可用处理能力可用于处理任何类型的工作，在增强期间“模糊”了通用处理器和专用处理器的能力。System Recovery Boost还加速和并行处理器重新配置操作，这些操作可能是客户端整体重启和恢复过程的一部分，由地理分散并行系统(GDPS)自动化编排。System Recovery Boost还可以通过激活一种新的临时容量记录，从客户端未使用的“暗核”中添加额外的处理器容量。所有这些都可以在不增加客户机的IBM软件计费成本或在这些提升期间与客户机工作负载相关的处理器消耗的情况下完成。
{"title":"System Recovery Boost on IBM z15","authors":"D. H. Surman;S. Lederer;D. B. Petersen;M. Gubitz;P. J. Relson","doi":"10.1147/JRD.2020.3008102","DOIUrl":"https://doi.org/10.1147/JRD.2020.3008102","url":null,"abstract":"System Recovery Boost on the IBM z15 server expedites planned operating system shutdown, either planned or unplanned operating system initial program load (IPL), middleware and workload restart and recovery, and the client workload execution that follows, to accelerate service restoration around downtime. It does this by providing limited-duration “boost periods” that deliver significant usable additional processor capacity and parallelism. On subcapacity machine models, it provides a boost in processor speed by running the general-purpose processors at full-capacity speed, for the boosting LPARs only, and only during the boost periods. It makes all available processing capacity defined to the boosting images available to process any kind of work, “blurring” general-purpose processor and specialty processor capacity together during the boost period. System Recovery Boost also expedites and parallelizes processor reconfiguration actions that may be part of the client's overall restart and recovery process, as orchestrated by Geographically Dispersed Parallel Sysplex (GDPS) automation. Optionally, System Recovery Boost provides the ability to add additional processor capacity from the client's unused “dark cores” via activation of a new type of temporary capacity record. All of this can be accomplished without increasing the client's IBM software billing costs or the processor consumption associated with the client's workload during these boost periods.","PeriodicalId":55034,"journal":{"name":"IBM Journal of Research and Development","volume":null,"pages":null},"PeriodicalIF":1.3,"publicationDate":"2020-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1147/JRD.2020.3008102","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49979349","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The IBM Z processor continues to improve over previous System Z processors, but for the first time it does so without a technology improvement as the baseline enabler. The IBM z15 was designed in the same 14-nm High-Performance GLOBALFOUNDRIES technology as the IBM z14 and yet still added 20% more cores, doubled the L3 cache, and increased the L2 cache by a third while also adding a third peripheral component interconnect express (PCIe) port to the chip and an elliptic curve cryptography engine into each core. This article discusses the design, tool, and methodology enhancements required to increase the design content so significantly while maintaining the chip size and power limits from the previous z14 design. This article also discusses other design and methodology improvements that were made possible via the deeper understanding of the technology and how to more fully leverage it in a second generation.
{"title":"IBM z15: Physical design improvements to significantly increase content in the same technology","authors":"C. J. Berry;D. Wolpert;B. Bell;A. Jatkowski;J. Surprise;G. Strevig;J. Isakson;O. Geva;B. Deskin;M. Cichanowski;G. Biran;D. Hamid;C. Cavitt;G. Fredeman;D. Chidambarrao;B. Bruen;M. Wood;S. Carey;D. Turner;L. Sigal","doi":"10.1147/JRD.2020.3008099","DOIUrl":"https://doi.org/10.1147/JRD.2020.3008099","url":null,"abstract":"The IBM Z processor continues to improve over previous System Z processors, but for the first time it does so without a technology improvement as the baseline enabler. The IBM z15 was designed in the same 14-nm High-Performance GLOBALFOUNDRIES technology as the IBM z14 and yet still added 20% more cores, doubled the L3 cache, and increased the L2 cache by a third while also adding a third peripheral component interconnect express (PCIe) port to the chip and an elliptic curve cryptography engine into each core. This article discusses the design, tool, and methodology enhancements required to increase the design content so significantly while maintaining the chip size and power limits from the previous z14 design. This article also discusses other design and methodology improvements that were made possible via the deeper understanding of the technology and how to more fully leverage it in a second generation.","PeriodicalId":55034,"journal":{"name":"IBM Journal of Research and Development","volume":null,"pages":null},"PeriodicalIF":1.3,"publicationDate":"2020-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1147/JRD.2020.3008099","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49952810","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-07-10DOI: 10.1147/JRD.2020.3008106
M. Klein;A. Misra;B. Abali;P. Sethia;S. Weishaupt;B. Giamei;M. Farrell;T. J. Slegel
The IBM z15 processor chip contains a new hardware component to perform DEFLATE compliant compression and decompression. The Integrated Accelerator for zEnterprise Data Compression is based on a high-frequency DEFLATE pipeline and includes a hardware generator for dynamic Huffman tables. Accessible as an architected instruction, this engine has been designed for straight forward exploitation by software and is easily available to any application in the problem state. A brand-new hardware/firmware integration model has been developed to provide this complex functionality without imposing restrictions on data patterns or data sizes and without impacting system responsiveness. This article describes the concept, implementation, and verification of DEFLATE compliant compression acceleration in z15 across both hardware and firmware. It illustrates various challenges that result from incorporating complex data-dependent and data-intense functionality like DEFLATE as an architected instruction and discusses how solutions in hardware/firmware codesign have been applied to overcome these challenges.
{"title":"Design and verification of DEFLATE acceleration as an architected instruction in z15","authors":"M. Klein;A. Misra;B. Abali;P. Sethia;S. Weishaupt;B. Giamei;M. Farrell;T. J. Slegel","doi":"10.1147/JRD.2020.3008106","DOIUrl":"https://doi.org/10.1147/JRD.2020.3008106","url":null,"abstract":"The IBM z15 processor chip contains a new hardware component to perform DEFLATE compliant compression and decompression. The Integrated Accelerator for zEnterprise Data Compression is based on a high-frequency DEFLATE pipeline and includes a hardware generator for dynamic Huffman tables. Accessible as an architected instruction, this engine has been designed for straight forward exploitation by software and is easily available to any application in the problem state. A brand-new hardware/firmware integration model has been developed to provide this complex functionality without imposing restrictions on data patterns or data sizes and without impacting system responsiveness. This article describes the concept, implementation, and verification of DEFLATE compliant compression acceleration in z15 across both hardware and firmware. It illustrates various challenges that result from incorporating complex data-dependent and data-intense functionality like DEFLATE as an architected instruction and discusses how solutions in hardware/firmware codesign have been applied to overcome these challenges.","PeriodicalId":55034,"journal":{"name":"IBM Journal of Research and Development","volume":null,"pages":null},"PeriodicalIF":1.3,"publicationDate":"2020-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1147/JRD.2020.3008106","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49952814","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-07-10DOI: 10.1147/JRD.2020.3008145
J. A. Busby;E. N. Cohen;E. A. Dames;J. Doherty;S. Dragone;D. Evans;M. J. Fisher;N. Hadzic;C. Hagleitner;A. J. Higby;M. D. Hocker;L. S. Jagich;M. J. Jordan;R. Kisley;K. D. Lamb;M. D. Marik;J. Mayfield;T. E. Morris;T. D. Needham;W. Santiago-Fernandez;V. Urban;T. Visegrady;K. Werner
System security is currently a main focus area for all IT infrastructure providers. New system features like pervasive encryption, the transition to cloud-based offerings, and the demand for quantum-safe platforms demand increased cryptographic performance as well as more cryptographic agility. The new IBM 4769 Cryptographic Coprocessor addresses these trends. It brings performance improvements that match the requirements of the new IBM z15. A combination of newly available features allows IBM z15 to scale to greater than 5,000 Virtual Hardware secure modules per system and makes it suitable to support virtualized client environments such as cloud-scale datacenters. To meet the dense packaging and energy requirements of those data centers, the form factor and power consumption of the card were reduced significantly. The card also offers an expanded set of algorithms to support state-of-the-art as well as future workloads. For the first time, the user interface provides access to a selected set of quantum-safe algorithms. Infrastructure extensions add hardware-embedded, attestation-friendly trusted boot services, which improve system resiliency by providing hardware enabled measurements of the secure and trusted boot process. These extensions simultaneously simplify the security certifications built on them. This article provides an overview of the IBM 4769 cryptographic coprocessor, highlighting security characteristics, internal hardware, form factor, and enhanced firmware.
{"title":"The IBM 4769 Cryptographic Coprocessor","authors":"J. A. Busby;E. N. Cohen;E. A. Dames;J. Doherty;S. Dragone;D. Evans;M. J. Fisher;N. Hadzic;C. Hagleitner;A. J. Higby;M. D. Hocker;L. S. Jagich;M. J. Jordan;R. Kisley;K. D. Lamb;M. D. Marik;J. Mayfield;T. E. Morris;T. D. Needham;W. Santiago-Fernandez;V. Urban;T. Visegrady;K. Werner","doi":"10.1147/JRD.2020.3008145","DOIUrl":"https://doi.org/10.1147/JRD.2020.3008145","url":null,"abstract":"System security is currently a main focus area for all IT infrastructure providers. New system features like pervasive encryption, the transition to cloud-based offerings, and the demand for quantum-safe platforms demand increased cryptographic performance as well as more cryptographic agility. The new IBM 4769 Cryptographic Coprocessor addresses these trends. It brings performance improvements that match the requirements of the new IBM z15. A combination of newly available features allows IBM z15 to scale to greater than 5,000 Virtual Hardware secure modules per system and makes it suitable to support virtualized client environments such as cloud-scale datacenters. To meet the dense packaging and energy requirements of those data centers, the form factor and power consumption of the card were reduced significantly. The card also offers an expanded set of algorithms to support state-of-the-art as well as future workloads. For the first time, the user interface provides access to a selected set of quantum-safe algorithms. Infrastructure extensions add hardware-embedded, attestation-friendly trusted boot services, which improve system resiliency by providing hardware enabled measurements of the secure and trusted boot process. These extensions simultaneously simplify the security certifications built on them. This article provides an overview of the IBM 4769 cryptographic coprocessor, highlighting security characteristics, internal hardware, form factor, and enhanced firmware.","PeriodicalId":55034,"journal":{"name":"IBM Journal of Research and Development","volume":null,"pages":null},"PeriodicalIF":1.3,"publicationDate":"2020-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1147/JRD.2020.3008145","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49952821","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-07-10DOI: 10.1147/JRD.2020.3008104
M. Somasundaram;J. P. Kubala;S. E. Lederer;J. Chan
Every new machine generation of IBM Z brings with it an increase in number of physical processors and memory capacity. Some generations can also bring change in the physical configuration of the server. The z15 for example, can have from one to five drawers instead of a maximum of four on the z14. As another example, z15 has fixed two chips per node versus the two or three chips per node on z14. The logical partitions on the other hand can come in various configurations, including “Dedicated” logical partition, shared “Hiperdispatch = YES” logical partition, and shared “Hiperdispatch = NO” partition. Each of the partition types can request as many logical processors and memory as the machine generation will allow, which is usually less than the physical resources available on the machine. The optimal placement of logical partitions on the physical server, given its configuration, is an NP-hard problem. Memory access latency and cache usage play vital roles in the performance of logical partitions, and it is imperative that placement is optimal. Moreover, on z15, the integrated facility for linux processors and internal coupling facility processors can be moved from one chip to another, during reoptimization of partition placement, in addition to general-purpose and IBM Z integrated information processors that are already allowed to be moved, compounding the placement problem. This article describes the changes made to the Processor Resource/Systems Manager (PR/SM) heuristic placement algorithm for z15 and how it surmounts the problems inherent for optimal placement of logical partitions.
IBM Z的每一代新机器都会带来物理处理器数量和内存容量的增加。某些代还可以更改服务器的物理配置。例如，z15可以有一到五个抽屉，而不是z14上最多四个抽屉。作为另一个例子，与z14上的每个节点两个或三个芯片相比，z15每个节点固定两个芯片。另一方面，逻辑分区可以有各种配置，包括“专用”逻辑分区、共享“Hiperdispatch=YES”逻辑分区和共享“Hierdispatch=NO”分区。每种分区类型都可以请求机器生成所允许的逻辑处理器和内存，这通常少于机器上可用的物理资源。给定物理服务器的配置，逻辑分区在物理服务器上的最佳位置是一个NP难题。内存访问延迟和缓存使用率在逻辑分区的性能中起着至关重要的作用，因此必须优化布局。此外，在z15上，除了已经允许移动的通用和IBMZ集成信息处理器之外，在分区布局的重新优化过程中，linux处理器和内部耦合设备处理器的集成设施可以从一个芯片移动到另一个芯片，这加剧了布局问题。本文描述了对z15的处理器资源/系统管理器（PR/SM）启发式布局算法所做的更改，以及它如何克服逻辑分区优化布局所固有的问题。
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Pub Date : 2020-07-10DOI: 10.1147/JRD.2020.3008100
W. P. Kostenko;J. G. Torok;D. W. Demetriou
The IBM z15 is designed to meet the requirements of a range of data centers, while reducing costs through increased density, configuration flexibility, and cooling efficiency. The z15 is a continuation and broadening of the physical transformation of the mainframe that began with the IBM z14 ZR1/LR1, which introduced the new “true 19-in” frame. A maximum configuration z15 delivers greater than 30% additional compute capacity per watt than z14, and maintains approximately the same maximum system footprint, while enabling significant floor space reduction for most configurations. The z15 introduces the choice of integrated 2N power using either intelligent power distribution units or bulk power, also supporting most data centers including hot/cold-aisle containment, raised-floor and nonraised-floor, and top and bottom-exit I/O and power. The z15 supports the ASHRAE A3 (fourth edition) environment, providing efficiency advantages by reducing humidification requirements. The z15 maintains the value of a system that is preconfigured/pretested before shipping. Innovations in packaging, I/O cabling, controls, and testing are put in the context of the latest data center trends. The capabilities of new tools to estimate power, weight, airflow, heat extracted to water for water-cooled systems as well as 3-D and computational fluid dynamics models to aid in the planning for the system are described.
IBM z15旨在满足一系列数据中心的要求，同时通过提高密度、配置灵活性和冷却效率来降低成本。z15是从IBM z14 ZR1/LR1开始的大型机物理转型的延续和扩展，它引入了新的“true 19 in”框架。与z14相比，最大配置z15每瓦可提供超过30%的额外计算容量，并保持大致相同的最大系统占地面积，同时能够显著减少大多数配置的占地面积。z15引入了集成2N电源的选择，使用智能配电单元或大容量电源，还支持大多数数据中心，包括热/冷通道安全壳、活动地板和非活动地板，以及顶部和底部出口I/O和电源。z15支持ASHRAE A3（第四版）环境，通过降低加湿要求提供效率优势。z15保持了装运前预配置/预测试的系统的价值。封装、I/O布线、控制和测试方面的创新都是在最新数据中心趋势的背景下进行的。描述了新工具估计水冷系统的功率、重量、气流、提取到水中的热量的能力，以及帮助系统规划的三维和计算流体动力学模型。
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Pub Date : 2020-07-10DOI: 10.1147/JRD.2020.3008143
T. Webel;P. M. Lobo;T. Strach;P. B. Parashurama;S. Purushotham;R. Bertran;A. Buyuktosunoglu
The IBM z15 processor power management enhances several on-chip power management techniques over z14 processor with a specific focus on reducing response time for voltage droop management. The IBM z15 processor puts a specific emphasis on proactive voltage droop management strategy to reduce conservative static guard band that is added to the supply voltage in order to protect against worst-case voltage droops. The z15 processor relies on selected events from the earlier stages of a deep pipeline processor as indicators to predict sharp changes in the power consumption over a short period of time. The early information of the selected events allows to throttle the execution flow through the processor pipeline and prevents the sharp power change before it takes place and thus reduces the voltage droop. In z15, as one of the proactive schemes, we combine both the digital power-proxies, which are direct indicators of the processor activity and the Critical Path Monitors (CPMs) to give an earlier and proactive indication of voltage droop events. This proactive indication provides enough time for the throttle actuation circuits to prevent the voltage droop. CPMs act as real-time timing margin indicators, and power-proxies act to serve as the activity monitors.
{"title":"Proactive power management in IBM z15","authors":"T. Webel;P. M. Lobo;T. Strach;P. B. Parashurama;S. Purushotham;R. Bertran;A. Buyuktosunoglu","doi":"10.1147/JRD.2020.3008143","DOIUrl":"https://doi.org/10.1147/JRD.2020.3008143","url":null,"abstract":"The IBM z15 processor power management enhances several on-chip power management techniques over z14 processor with a specific focus on reducing response time for voltage droop management. The IBM z15 processor puts a specific emphasis on proactive voltage droop management strategy to reduce conservative static guard band that is added to the supply voltage in order to protect against worst-case voltage droops. The z15 processor relies on selected events from the earlier stages of a deep pipeline processor as indicators to predict sharp changes in the power consumption over a short period of time. The early information of the selected events allows to throttle the execution flow through the processor pipeline and prevents the sharp power change before it takes place and thus reduces the voltage droop. In z15, as one of the proactive schemes, we combine both the digital power-proxies, which are direct indicators of the processor activity and the Critical Path Monitors (CPMs) to give an earlier and proactive indication of voltage droop events. This proactive indication provides enough time for the throttle actuation circuits to prevent the voltage droop. CPMs act as real-time timing margin indicators, and power-proxies act to serve as the activity monitors.","PeriodicalId":55034,"journal":{"name":"IBM Journal of Research and Development","volume":null,"pages":null},"PeriodicalIF":1.3,"publicationDate":"2020-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1147/JRD.2020.3008143","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49952816","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-07-10DOI: 10.1147/JRD.2020.3008119
A. Saporito;M. Recktenwald;C. Jacobi;G. Koch;D. P. D. Berger;R. J. Sonnelitter;C. R. Walters;J.-S. Lee;C. Lichtenau;U. Mayer;E. Herkel;S. Payer;S. M. Mueller;V. K. Papazova;E. M. Ambroladze;T. C. Bronson
The latest-generation IBM Z processor provides enhanced performance and compute capacity compared to its IBM z14 predecessor. This article describes some of the major improvements in both process and design including out-of-order load-and-store sequencing, single-instruction multiple-data and floating point enhancements, a new modulo arithmetic engine for accelerating elliptic curve cryptography, a hardware sort accelerator, and a workflow that modernized the development of these features. Outside of the central processing unit (CPU), the cache sizes have increased on all levels, and each processor chip now contains 12 CPUs. System topology changes have been introduced allowing up to five drawers to exist in a fully populated system. The processor cache subsystem includes numerous improvements in the area of fetch, store, and cache management policies aimed at speeding up both traditional data serving workloads and highly virtualized environments alike.
{"title":"Design of the IBM z15 microprocessor","authors":"A. Saporito;M. Recktenwald;C. Jacobi;G. Koch;D. P. D. Berger;R. J. Sonnelitter;C. R. Walters;J.-S. Lee;C. Lichtenau;U. Mayer;E. Herkel;S. Payer;S. M. Mueller;V. K. Papazova;E. M. Ambroladze;T. C. Bronson","doi":"10.1147/JRD.2020.3008119","DOIUrl":"https://doi.org/10.1147/JRD.2020.3008119","url":null,"abstract":"The latest-generation IBM Z processor provides enhanced performance and compute capacity compared to its IBM z14 predecessor. This article describes some of the major improvements in both process and design including out-of-order load-and-store sequencing, single-instruction multiple-data and floating point enhancements, a new modulo arithmetic engine for accelerating elliptic curve cryptography, a hardware sort accelerator, and a workflow that modernized the development of these features. Outside of the central processing unit (CPU), the cache sizes have increased on all levels, and each processor chip now contains 12 CPUs. System topology changes have been introduced allowing up to five drawers to exist in a fully populated system. The processor cache subsystem includes numerous improvements in the area of fetch, store, and cache management policies aimed at speeding up both traditional data serving workloads and highly virtualized environments alike.","PeriodicalId":55034,"journal":{"name":"IBM Journal of Research and Development","volume":null,"pages":null},"PeriodicalIF":1.3,"publicationDate":"2020-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1147/JRD.2020.3008119","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49952809","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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