Pub Date : 2016-10-01DOI: 10.1109/DASIP.2016.7853821
Judicael Menant, G. Gautier, J. Nezan, M. Pressigout, L. Morin
Stereo matching techniques aim at reconstructing depth information from a pair of images. The use of stereo matching algorithms in embedded systems is very challenging due to the complexity of state-of-the-art algorithms.
{"title":"A comparison of cost construction methods onto a C6678 platform for stereo matching","authors":"Judicael Menant, G. Gautier, J. Nezan, M. Pressigout, L. Morin","doi":"10.1109/DASIP.2016.7853821","DOIUrl":"https://doi.org/10.1109/DASIP.2016.7853821","url":null,"abstract":"Stereo matching techniques aim at reconstructing depth information from a pair of images. The use of stereo matching algorithms in embedded systems is very challenging due to the complexity of state-of-the-art algorithms.","PeriodicalId":6494,"journal":{"name":"2016 Conference on Design and Architectures for Signal and Image Processing (DASIP)","volume":"76 1","pages":"208-214"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75077753","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/DASIP.2016.7853806
Mohamad-Al-Fadl Rihani, Jean-Christophe Prévotet, F. Nouvel, M. Mroué, Y. Mohanna
Recent fixed and mobile wireless communication systems have attracted researchers to propose new techniques and methodologies that greatly improve performance. For example, adaptive techniques have improved the wireless channel efficiency while decreasing the overall power consumption. They consist in reconfiguring parts of the global system automatically according to different parameters. In parallel, circuit technology has also considerably evolved. One example is Field Programmable Gate Arrays (FPGAs) that are now suitable for implementing the physical layer of most complex wireless communication systems. This has been made possible thanks to their high level of performance, flexibility, and bit-level programming. In these devices, the Dynamic Partial Reconfiguration (DPR) constitutes a well known technique for reconfiguring only a specific area within the circuit. This technique offers efficient resource utilization, reduced power consumption and permits the optimization of the configuration time. In our work, we benefit from this technology to implement a wireless communication system in hardware. Hardware reconfiguration is performed automatically according to adaptive decision processes running on top of a micro-kernel that manages partial reconfiguration. The system is implemented on a ZedBoard which features a Xilinx Zynq 7000 System on Chip (SoC).
{"title":"ARM-FPGA based platform for automated adaptive wireless communication systems using partial reconfiguration technique","authors":"Mohamad-Al-Fadl Rihani, Jean-Christophe Prévotet, F. Nouvel, M. Mroué, Y. Mohanna","doi":"10.1109/DASIP.2016.7853806","DOIUrl":"https://doi.org/10.1109/DASIP.2016.7853806","url":null,"abstract":"Recent fixed and mobile wireless communication systems have attracted researchers to propose new techniques and methodologies that greatly improve performance. For example, adaptive techniques have improved the wireless channel efficiency while decreasing the overall power consumption. They consist in reconfiguring parts of the global system automatically according to different parameters. In parallel, circuit technology has also considerably evolved. One example is Field Programmable Gate Arrays (FPGAs) that are now suitable for implementing the physical layer of most complex wireless communication systems. This has been made possible thanks to their high level of performance, flexibility, and bit-level programming. In these devices, the Dynamic Partial Reconfiguration (DPR) constitutes a well known technique for reconfiguring only a specific area within the circuit. This technique offers efficient resource utilization, reduced power consumption and permits the optimization of the configuration time. In our work, we benefit from this technology to implement a wireless communication system in hardware. Hardware reconfiguration is performed automatically according to adaptive decision processes running on top of a micro-kernel that manages partial reconfiguration. The system is implemented on a ZedBoard which features a Xilinx Zynq 7000 System on Chip (SoC).","PeriodicalId":6494,"journal":{"name":"2016 Conference on Design and Architectures for Signal and Image Processing (DASIP)","volume":"6 1","pages":"113-120"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72734039","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/DASIP.2016.7853810
S. Smets, T. Goedemé, M. Verhelst
State-of-the-art solutions to optical flow fail to jointly offer high density flow estimation, low power consumption and real time operation, rendering them unsuitable for embedded applications. Joint hardware-software scalability at run-time is crucial to achieve these conflicting requirements in one device. This paper therefore presents a scalable Lucas-Kanade optical flow algorithm, together with a flexible power-optimized processor architecture. The C-programmable processor exploits algorithmic scalability through innovations in its memory structure, memory interface, and datapath optimized for efficient convolutions. Jointly, the scalable flow algorithm and optimized computer vision hardware platform enable applications to on-the-fly trade-off throughput and power consumption in function of flow density and accuracy. The processor chip is synthesized in 40nm CMOS technology and verified on FPGA. The architecture is capable of scaling the frame rate at run-time and processes 16fps of dense optical flow at 640×480 resolution with 15.06° average angular error, while only consuming 24mW.
{"title":"Custom processor design for efficient, yet flexible Lucas-Kanade optical flow","authors":"S. Smets, T. Goedemé, M. Verhelst","doi":"10.1109/DASIP.2016.7853810","DOIUrl":"https://doi.org/10.1109/DASIP.2016.7853810","url":null,"abstract":"State-of-the-art solutions to optical flow fail to jointly offer high density flow estimation, low power consumption and real time operation, rendering them unsuitable for embedded applications. Joint hardware-software scalability at run-time is crucial to achieve these conflicting requirements in one device. This paper therefore presents a scalable Lucas-Kanade optical flow algorithm, together with a flexible power-optimized processor architecture. The C-programmable processor exploits algorithmic scalability through innovations in its memory structure, memory interface, and datapath optimized for efficient convolutions. Jointly, the scalable flow algorithm and optimized computer vision hardware platform enable applications to on-the-fly trade-off throughput and power consumption in function of flow density and accuracy. The processor chip is synthesized in 40nm CMOS technology and verified on FPGA. The architecture is capable of scaling the frame rate at run-time and processes 16fps of dense optical flow at 640×480 resolution with 15.06° average angular error, while only consuming 24mW.","PeriodicalId":6494,"journal":{"name":"2016 Conference on Design and Architectures for Signal and Image Processing (DASIP)","volume":"54 1","pages":"138-145"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74993099","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/DASIP.2016.7853817
M. Komorkiewicz, Krzysztof Turek, P. Skruch, T. Kryjak, M. Gorgon
In this paper an FPGA-based video HiL (Hardwarein-the-Loop) solution is presented. It was designed to evaluate an of-the-shelf ADAS (Advanced Driver Assistance System) smart camera consisting of a video sensor (so-called forward looking camera (FLC)) and video processing unit. It allows to directly capture and store on a PC the video stream from the sensor. Then, the pre-recorded sequences can be directly injected into the video processing unit. Therefore, it is possible to evaluate the vision system in the laboratory under conditions almost identical to those present during real test drives. Moreover, all experiments are fully repeatable. The proposed system supports video streams with resolution 1280×960 @ 30 fps in the RCCC (Red/Clear)1 colour system. It is used in research and development projects in Delphi Technical Center Krakow.
{"title":"FPGA-based Hardware-in-the-Loop environment using video injection concept for camera-based systems in automotive applications","authors":"M. Komorkiewicz, Krzysztof Turek, P. Skruch, T. Kryjak, M. Gorgon","doi":"10.1109/DASIP.2016.7853817","DOIUrl":"https://doi.org/10.1109/DASIP.2016.7853817","url":null,"abstract":"In this paper an FPGA-based video HiL (Hardwarein-the-Loop) solution is presented. It was designed to evaluate an of-the-shelf ADAS (Advanced Driver Assistance System) smart camera consisting of a video sensor (so-called forward looking camera (FLC)) and video processing unit. It allows to directly capture and store on a PC the video stream from the sensor. Then, the pre-recorded sequences can be directly injected into the video processing unit. Therefore, it is possible to evaluate the vision system in the laboratory under conditions almost identical to those present during real test drives. Moreover, all experiments are fully repeatable. The proposed system supports video streams with resolution 1280×960 @ 30 fps in the RCCC (Red/Clear)1 colour system. It is used in research and development projects in Delphi Technical Center Krakow.","PeriodicalId":6494,"journal":{"name":"2016 Conference on Design and Architectures for Signal and Image Processing (DASIP)","volume":"38 1","pages":"183-190"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77253031","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/DASIP.2016.7853835
Carlo Sau, Tiziana Fanni, P. Meloni, L. Raffo, M. Pelcat, F. Palumbo
Coarse-grained reconfigurable systems are capable of providing flexibility and optimal performance, suitable for nowadays embedded computing systems. The RPCT project has tackled the issue of their complex design, debug and mapping. Demonstration of its potentials and features are presented on an MPEG HEVC motion compensation use case.
{"title":"Demo: Reconfigurable Platform Composer Tool","authors":"Carlo Sau, Tiziana Fanni, P. Meloni, L. Raffo, M. Pelcat, F. Palumbo","doi":"10.1109/DASIP.2016.7853835","DOIUrl":"https://doi.org/10.1109/DASIP.2016.7853835","url":null,"abstract":"Coarse-grained reconfigurable systems are capable of providing flexibility and optimal performance, suitable for nowadays embedded computing systems. The RPCT project has tackled the issue of their complex design, debug and mapping. Demonstration of its potentials and features are presented on an MPEG HEVC motion compensation use case.","PeriodicalId":6494,"journal":{"name":"2016 Conference on Design and Architectures for Signal and Image Processing (DASIP)","volume":"27 3 1","pages":"245-246"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89579794","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/DASIP.2016.7853819
P. Delmas, R. Ababou
Computer vision and Image analysis have taken advantage of five decades of intense development. The complexity of the algorithms in this field can now benefit from dramatically increasing computational power to offer viable applications going from embedded systems to cloud computing. This special session proposes three papers dealing with the implementation of computer vision and image analysis applications on embedded systems.
{"title":"Special session 2 Computer vision and Image analysis","authors":"P. Delmas, R. Ababou","doi":"10.1109/DASIP.2016.7853819","DOIUrl":"https://doi.org/10.1109/DASIP.2016.7853819","url":null,"abstract":"Computer vision and Image analysis have taken advantage of five decades of intense development. The complexity of the algorithms in this field can now benefit from dramatically increasing computational power to offer viable applications going from embedded systems to cloud computing. This special session proposes three papers dealing with the implementation of computer vision and image analysis applications on embedded systems.","PeriodicalId":6494,"journal":{"name":"2016 Conference on Design and Architectures for Signal and Image Processing (DASIP)","volume":"1 1","pages":"199"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89120709","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/DASIP.2016.7853795
Koldo Basterretxea, Unai Martinez-Corral, Raul Finker, I. D. Campo
Hyperspectral imagery is being widely used for accurate object detection and terrain feature classification. Modern imaging spectrometers produce huge amounts of data that are compressed onboard and downloaded to ground stations to be processed. Increasing spectral resolution and data acquisition rates demand more efficient compression techniques to meet downlink bandwidth restrictions. A different approach to reducing data-transfer bottlenecks consists of processing hyperspectral imagery information onboard. Real-time onboard processing would, at the same time, broaden the scope of missions that spacecrafts and aircrafts carrying hyperspectral cameras could fulfill by providing them with immediate decision-making capacity in critical circumstances. This paper investigates the use of Extreme Learning Machines (ELMs) for the classification of high dimensional data, and how specialized hardware and application-specific processor design can help to produce high performance, lightweight, and reduced power consumption systems for onboard hyperspectral imagery processing.
{"title":"ELM-based hyperspectral imagery processor for onboard real-time classification","authors":"Koldo Basterretxea, Unai Martinez-Corral, Raul Finker, I. D. Campo","doi":"10.1109/DASIP.2016.7853795","DOIUrl":"https://doi.org/10.1109/DASIP.2016.7853795","url":null,"abstract":"Hyperspectral imagery is being widely used for accurate object detection and terrain feature classification. Modern imaging spectrometers produce huge amounts of data that are compressed onboard and downloaded to ground stations to be processed. Increasing spectral resolution and data acquisition rates demand more efficient compression techniques to meet downlink bandwidth restrictions. A different approach to reducing data-transfer bottlenecks consists of processing hyperspectral imagery information onboard. Real-time onboard processing would, at the same time, broaden the scope of missions that spacecrafts and aircrafts carrying hyperspectral cameras could fulfill by providing them with immediate decision-making capacity in critical circumstances. This paper investigates the use of Extreme Learning Machines (ELMs) for the classification of high dimensional data, and how specialized hardware and application-specific processor design can help to produce high performance, lightweight, and reduced power consumption systems for onboard hyperspectral imagery processing.","PeriodicalId":6494,"journal":{"name":"2016 Conference on Design and Architectures for Signal and Image Processing (DASIP)","volume":"393 1","pages":"43-50"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76454707","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/DASIP.2016.7853820
K. H. Salem, Yann Kieffer, S. Mancini
Embedded vision systems design faces a memory-wall kind of challenge: images are big, and therefore memories containing them have high latency; and still, high performance is desired. For the case of non-linear processings, Mancini and Rousseau (Proc. DATE 2012) have designed a software generator of adhoc memory hierarchies, called Memory Management Optimization (MMOpt). While the performance of the generated circuits is very good, design-time decisions have to be made regarding their operation in order to handle finely the compromise between the usual metrics of design area, energy consumption, and performance. This study tackles the optimization challenge set by the design of the operational behavior of the memory hierarchy generated by MMOpt. After a precise formulation as a 3-objective optimization problem is given, two algorithms are proposed, and their performance is analyzed on real-world processings against the previously proposed algorithms. The results show a reduction of the amount of transferred data by 17% on average, and of the computing times by 11.7%, for the same design area.
嵌入式视觉系统设计面临着内存墙的挑战:图像很大，因此包含它们的内存具有高延迟;但是，仍然需要高性能。对于非线性处理的情况，Mancini和Rousseau (Proc. DATE 2012)设计了一个临时内存层次的软件生成器，称为内存管理优化(MMOpt)。虽然生成的电路的性能非常好，但设计时必须做出有关其操作的决策，以便在通常的设计面积、能耗和性能指标之间进行精细的折衷。本研究解决了由MMOpt生成的内存层次结构的操作行为设计所带来的优化挑战。在给出三目标优化问题的精确表述后，提出了两种算法，并在实际处理中对比分析了它们的性能。结果表明，对于相同的设计区域，传输的数据量平均减少了17%，计算时间减少了11.7%。
{"title":"Memory management in embedded vision systems: Optimization problems and solution methods","authors":"K. H. Salem, Yann Kieffer, S. Mancini","doi":"10.1109/DASIP.2016.7853820","DOIUrl":"https://doi.org/10.1109/DASIP.2016.7853820","url":null,"abstract":"Embedded vision systems design faces a memory-wall kind of challenge: images are big, and therefore memories containing them have high latency; and still, high performance is desired. For the case of non-linear processings, Mancini and Rousseau (Proc. DATE 2012) have designed a software generator of adhoc memory hierarchies, called Memory Management Optimization (MMOpt). While the performance of the generated circuits is very good, design-time decisions have to be made regarding their operation in order to handle finely the compromise between the usual metrics of design area, energy consumption, and performance. This study tackles the optimization challenge set by the design of the operational behavior of the memory hierarchy generated by MMOpt. After a precise formulation as a 3-objective optimization problem is given, two algorithms are proposed, and their performance is analyzed on real-world processings against the previously proposed algorithms. The results show a reduction of the amount of transferred data by 17% on average, and of the computing times by 11.7%, for the same design area.","PeriodicalId":6494,"journal":{"name":"2016 Conference on Design and Architectures for Signal and Image Processing (DASIP)","volume":"72 1","pages":"200-207"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77377126","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/DASIP.2016.7853797
Hamza Bendaoudi, F. Cheriet, J. Langlois
This paper presents a memory efficient architecture that implements the Multi-Scale Line Detector (MSLD) algorithm for real-time retinal blood vessel detection in fundus images on a Zynq FPGA. This implementation benefits from the FPGA parallelism to drastically reduce the memory requirements of the MSLD from two images to a few values. The architecture is optimized in terms of resource utilization by reusing the computations and optimizing the bit-width. The throughput is increased by designing fully pipelined functional units. The architecture is capable of achieving a comparable accuracy to its software implementation but 70× faster for low resolution images. For high resolution images, it achieves an acceleration by a factor of 323×.
本文提出了一种基于Zynq FPGA的多尺度线检测器(Multi-Scale Line Detector, MSLD)算法的高效内存架构，用于眼底图像中视网膜血管的实时检测。这种实现得益于FPGA的并行性，可以将MSLD的内存需求从两个映像大幅减少到几个值。通过对计算的重用和位宽的优化，从资源利用率方面对体系结构进行了优化。通过设计完全流水线的功能单元，提高了吞吐量。该架构能够达到与其软件实现相当的精度，但对于低分辨率图像要快70倍。对于高分辨率图像，它可以实现323倍的加速度。
{"title":"Memory efficient Multi-Scale Line Detector architecture for retinal blood vessel segmentation","authors":"Hamza Bendaoudi, F. Cheriet, J. Langlois","doi":"10.1109/DASIP.2016.7853797","DOIUrl":"https://doi.org/10.1109/DASIP.2016.7853797","url":null,"abstract":"This paper presents a memory efficient architecture that implements the Multi-Scale Line Detector (MSLD) algorithm for real-time retinal blood vessel detection in fundus images on a Zynq FPGA. This implementation benefits from the FPGA parallelism to drastically reduce the memory requirements of the MSLD from two images to a few values. The architecture is optimized in terms of resource utilization by reusing the computations and optimizing the bit-width. The throughput is increased by designing fully pipelined functional units. The architecture is capable of achieving a comparable accuracy to its software implementation but 70× faster for low resolution images. For high resolution images, it achieves an acceleration by a factor of 323×.","PeriodicalId":6494,"journal":{"name":"2016 Conference on Design and Architectures for Signal and Image Processing (DASIP)","volume":"11 1","pages":"59-64"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80852868","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/DASIP.2016.7853805
Thibaud Tonnellier, Camille Leroux, B. Gal, C. Jégo, B. Gadat, N. V. Wambeke
Turbo codes are well known error-correcting codes used in many communication standards. However, they suffer from error floors. Recently, a method - denoted as the flip and check algorithm - that lowers the error floor of turbo codes was proposed. This method relies on the identification of the least reliable bits during the turbo decoding process. Gains of about one order of magnitude were reached in terms of error rate performance. In this article, the first hardware implementation of the method is presented. The feasibility and hardware complexity are addressed by studying the impact of the algorithmic parameters of the technique. Synthesis results for FPGA implementations are reported and compared to turbo decoders implementations.
{"title":"Hardware architecture for lowering the error floor of LTE turbo codes","authors":"Thibaud Tonnellier, Camille Leroux, B. Gal, C. Jégo, B. Gadat, N. V. Wambeke","doi":"10.1109/DASIP.2016.7853805","DOIUrl":"https://doi.org/10.1109/DASIP.2016.7853805","url":null,"abstract":"Turbo codes are well known error-correcting codes used in many communication standards. However, they suffer from error floors. Recently, a method - denoted as the flip and check algorithm - that lowers the error floor of turbo codes was proposed. This method relies on the identification of the least reliable bits during the turbo decoding process. Gains of about one order of magnitude were reached in terms of error rate performance. In this article, the first hardware implementation of the method is presented. The feasibility and hardware complexity are addressed by studying the impact of the algorithmic parameters of the technique. Synthesis results for FPGA implementations are reported and compared to turbo decoders implementations.","PeriodicalId":6494,"journal":{"name":"2016 Conference on Design and Architectures for Signal and Image Processing (DASIP)","volume":"2 1","pages":"107-112"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90749522","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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