Pub Date : 2016-05-22DOI: 10.1109/ISCAS.2016.7527191
V. Tavsanoglu
This paper considers the task of constructing an (M×A+1)-node rectangular planar resistive grid as: first forming two (M×A+1)-node planar sub-grids; one made up of M of (N+1)-node horizontal, and the other of N of (M+1)-node vertical linear resistive grids, then joining their corresponding nodes. By doing so it is sho wn that the nodal conductance matrices GH and GV of the two sub-grids can be expressed as the Kronecker products GH = Im ⊗ Gn, Gv = Gm ⊗ In, and G of the resultant planar grid as the Kronecker sum G = Gn ⊕ Gm, where Gm and Im are, respectively, the nodal conductance matrix of a linear resistive grid and the identity matrix, both of size M. Moreover, since the analytical expression s for the eigenvalues and eigenvectors of Gm — which is a symmetric tridiagonal matrix — are well known, this approach enables the derivation of the analytical expressions of the eigenvalues and eigenvectors of Gh, Gv and G in terms of those of Gm and Gn, thereby drastically simplifying their computation and rendering the use of any matrix-inversion-based method unnecessary in the solution of nodal equations of very large grids.
{"title":"Construction of the nodal conductance matrix of a planar resistive grid and derivation of the analytical expressions of its eigenvalues and eigenvectors using the Kronecker product and sum","authors":"V. Tavsanoglu","doi":"10.1109/ISCAS.2016.7527191","DOIUrl":"https://doi.org/10.1109/ISCAS.2016.7527191","url":null,"abstract":"This paper considers the task of constructing an (M×A+1)-node rectangular planar resistive grid as: first forming two (M×A+1)-node planar sub-grids; one made up of M of (N+1)-node horizontal, and the other of N of (M+1)-node vertical linear resistive grids, then joining their corresponding nodes. By doing so it is sho wn that the nodal conductance matrices GH and GV of the two sub-grids can be expressed as the Kronecker products GH = Im ⊗ Gn, Gv = Gm ⊗ In, and G of the resultant planar grid as the Kronecker sum G = Gn ⊕ Gm, where Gm and Im are, respectively, the nodal conductance matrix of a linear resistive grid and the identity matrix, both of size M. Moreover, since the analytical expression s for the eigenvalues and eigenvectors of Gm — which is a symmetric tridiagonal matrix — are well known, this approach enables the derivation of the analytical expressions of the eigenvalues and eigenvectors of Gh, Gv and G in terms of those of Gm and Gn, thereby drastically simplifying their computation and rendering the use of any matrix-inversion-based method unnecessary in the solution of nodal equations of very large grids.","PeriodicalId":6546,"journal":{"name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"6 1","pages":"145-148"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83507489","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-22DOI: 10.1109/ISCAS.2016.7539163
H. Sun, Kazuki Sobue, K. Hamashita, U. Moon
This paper presents an in-loop-bandwidth spread-spectrum clock generation by proposing a linear charge-based discrete-time loop filter. The proposed architecture achieves a power efficient (2.29mA/GHz) spread-spectrum modulation scheme based upon a conventional CP-PLL. This work supports a modulation range of +/−2.7 % of a 700 MHz output frequency with the modulation rate in the range of 10 ∼ 100 kHz. The measured period rms and peak-to-peak jitters are 2.71 ps, rms and 20.6 ps, pp, respectively. The proposed spread-spectrum clock generator is fabricated in a 180 nm CMOS process and occupies an area of 0.525 mm2.
{"title":"A power efficient PLL with in-loop-bandwidth spread-spectrum modulation scheme using a charge-based discrete-time loop filter","authors":"H. Sun, Kazuki Sobue, K. Hamashita, U. Moon","doi":"10.1109/ISCAS.2016.7539163","DOIUrl":"https://doi.org/10.1109/ISCAS.2016.7539163","url":null,"abstract":"This paper presents an in-loop-bandwidth spread-spectrum clock generation by proposing a linear charge-based discrete-time loop filter. The proposed architecture achieves a power efficient (2.29mA/GHz) spread-spectrum modulation scheme based upon a conventional CP-PLL. This work supports a modulation range of +/−2.7 % of a 700 MHz output frequency with the modulation rate in the range of 10 ∼ 100 kHz. The measured period rms and peak-to-peak jitters are 2.71 ps, rms and 20.6 ps, pp, respectively. The proposed spread-spectrum clock generator is fabricated in a 180 nm CMOS process and occupies an area of 0.525 mm2.","PeriodicalId":6546,"journal":{"name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"13 1","pages":"2755-2758"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83544279","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-22DOI: 10.1109/ISCAS.2016.7527165
R. Taco, I. Levi, M. Lanuzza, A. Fish
Recently, we proposed a low-granularity back-bias control technique [1] optimized for the ultra-thin body and box (UTBB) fully-depleted silicon-on-insulator (FD-SOI) technology. The technique was preliminary evaluated through the design of a low-voltage 8-bit ripple carry adder (RCA), showing very competitive energy and delay values. In this paper, the characteristics of the low-granularity back-biasing control are explored considering as benchmarks basic logic gates as well as adders with different bit lengths. All the designed circuits were compared to their equivalent dynamic threshold voltage MOSFE T (DTMOS) and conventional CMOS designs. The higher efficiency of low granularity body bias control is emphasized by the single well layout strategy, offered by the 28 nm UTBB FD-SOI technology, thus leading our approach to achieve competitive silicon area occupancy along with significant performance and energy improvements. More precisely, postlayout simulations have demonstrated that circuits designed according the suggested strategy, can achieve a delay reduction of 33% compared to conventional CMOS designs, whereas the energy consumption can be reduced down to 46% compared to DTMOS solutions, for a supply voltage of 0.4V. These results were obtained while maintaining robustness against process and temperature variations.
最近，我们提出了一种针对超薄体盒(UTBB)全耗尽绝缘体上硅(FD-SOI)技术优化的低粒度反偏控制技术[1]。通过设计一个低压8位纹波进位加法器(RCA)对该技术进行了初步评估，显示出非常有竞争力的能量和延迟值。本文以基本逻辑门和不同位长加法器为基准，探讨了低粒度反偏控制的特性。将所有设计的电路与等效动态阈值电压MOSFE T (DTMOS)和传统CMOS设计进行了比较。28纳米UTBB FD-SOI技术提供的单井布局策略强调了低粒度体偏置控制的更高效率，从而使我们的方法实现了具有竞争力的硅面积占用，同时显著提高了性能和能源。更准确地说，布局后仿真表明，与传统CMOS设计相比，根据所建议的策略设计的电路可以实现延迟降低33%，而在0.4V的电源电压下，与DTMOS解决方案相比，能耗可以降低46%。这些结果是在保持对工艺和温度变化的稳健性的情况下获得的。
{"title":"Extended exploration of low granularity back biasing control in 28nm UTBB FD-SOI technology","authors":"R. Taco, I. Levi, M. Lanuzza, A. Fish","doi":"10.1109/ISCAS.2016.7527165","DOIUrl":"https://doi.org/10.1109/ISCAS.2016.7527165","url":null,"abstract":"Recently, we proposed a low-granularity back-bias control technique [1] optimized for the ultra-thin body and box (UTBB) fully-depleted silicon-on-insulator (FD-SOI) technology. The technique was preliminary evaluated through the design of a low-voltage 8-bit ripple carry adder (RCA), showing very competitive energy and delay values. In this paper, the characteristics of the low-granularity back-biasing control are explored considering as benchmarks basic logic gates as well as adders with different bit lengths. All the designed circuits were compared to their equivalent dynamic threshold voltage MOSFE T (DTMOS) and conventional CMOS designs. The higher efficiency of low granularity body bias control is emphasized by the single well layout strategy, offered by the 28 nm UTBB FD-SOI technology, thus leading our approach to achieve competitive silicon area occupancy along with significant performance and energy improvements. More precisely, postlayout simulations have demonstrated that circuits designed according the suggested strategy, can achieve a delay reduction of 33% compared to conventional CMOS designs, whereas the energy consumption can be reduced down to 46% compared to DTMOS solutions, for a supply voltage of 0.4V. These results were obtained while maintaining robustness against process and temperature variations.","PeriodicalId":6546,"journal":{"name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"1 1","pages":"41-44"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88623452","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-22DOI: 10.1109/ISCAS.2016.7527170
S. Sutula, M. Dei, L. Terés, F. Serra-Graells
This paper presents a 96.6-dB-peak-SNDR and 50-kHz-bandwidth switched-capacitor delta-sigma modulator for ADC operating at 1.8 V and consuming 7.9 mW. This performance is achieved by the introduction of Class-AB single-stage switched variable-mirror amplifiers (VMAs) combined with an optimized architecture and a 5-phase switched-capacitor scheme. The resulting 1.8-mm2 delta-sigma modulator is integrated in a standard 0.18-μm 1P6M CMOS technology and reaches a Schreier figure of merit of 164.6 dB from experimental SNDR measurements without the need for any clock bootstrapping, analog calibration or digital compensation technique.
{"title":"A calibration-free 96.6-dB-SNDR non-bootstrapped 1.8-V 7.9-mW delta-sigma modulator with class-AB single-stage switched VMAs","authors":"S. Sutula, M. Dei, L. Terés, F. Serra-Graells","doi":"10.1109/ISCAS.2016.7527170","DOIUrl":"https://doi.org/10.1109/ISCAS.2016.7527170","url":null,"abstract":"This paper presents a 96.6-dB-peak-SNDR and 50-kHz-bandwidth switched-capacitor delta-sigma modulator for ADC operating at 1.8 V and consuming 7.9 mW. This performance is achieved by the introduction of Class-AB single-stage switched variable-mirror amplifiers (VMAs) combined with an optimized architecture and a 5-phase switched-capacitor scheme. The resulting 1.8-mm2 delta-sigma modulator is integrated in a standard 0.18-μm 1P6M CMOS technology and reaches a Schreier figure of merit of 164.6 dB from experimental SNDR measurements without the need for any clock bootstrapping, analog calibration or digital compensation technique.","PeriodicalId":6546,"journal":{"name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"23 1","pages":"61-64"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80640876","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-22DOI: 10.1109/ISCAS.2016.7539118
A. Safaei, Q. M. J. Wu
This paper proposes a system-on-chip (SoC) FPGA - based real-time video processing platform for background and foreground identification. Background and foreground identification is a co mmon feature in many tasks in video content analytics (VCA), including object detection, tracking, segmentation and recognition. VCA is a relatively new field in video processing; it has generally been implemented using two chips, with the image signal processing (ISP) part in a DSP or an FPGA and the VCA part executed by a processor. However, a new generation of SoC FPGAs that incorporates a processor and an FPGA into a single chip makes it possible for a single chip to perform both ISP and VCA. This study details the hardware implementation of a real-time background and foreground identification algorithm in an SoC, including the capture, processing and display stages. The proposed platform uses photometric invariant color, depth data and local binary patterns (LBPs) to distinguish backgrounds from foregrounds. The system uses minimal cell resources and tries to implement modules using a pipeline technique.
{"title":"A system-level design for foreground and background identification in 3D scenes","authors":"A. Safaei, Q. M. J. Wu","doi":"10.1109/ISCAS.2016.7539118","DOIUrl":"https://doi.org/10.1109/ISCAS.2016.7539118","url":null,"abstract":"This paper proposes a system-on-chip (SoC) FPGA - based real-time video processing platform for background and foreground identification. Background and foreground identification is a co mmon feature in many tasks in video content analytics (VCA), including object detection, tracking, segmentation and recognition. VCA is a relatively new field in video processing; it has generally been implemented using two chips, with the image signal processing (ISP) part in a DSP or an FPGA and the VCA part executed by a processor. However, a new generation of SoC FPGAs that incorporates a processor and an FPGA into a single chip makes it possible for a single chip to perform both ISP and VCA. This study details the hardware implementation of a real-time background and foreground identification algorithm in an SoC, including the capture, processing and display stages. The proposed platform uses photometric invariant color, depth data and local binary patterns (LBPs) to distinguish backgrounds from foregrounds. The system uses minimal cell resources and tries to implement modules using a pipeline technique.","PeriodicalId":6546,"journal":{"name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"52 1","pages":"2571-2574"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85249976","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-22DOI: 10.1109/ISCAS.2016.7527512
A. Robichaud, F. Nabki, D. Deslandes
This paper presents a simple integrated reference based adaptive matching network capable of undertaking real time antenna tuning for applications such as wearable wireless sensors. The signal sent to the antenna is compared to a reference signal using a single flip-flop acting as a phase detector. In case of an impedance mismatch, a counter controlling a capacitor bank is activated reducing the sensed mismatch. The system is capable of three modes: calibration, matching and operation. The calibration mode ensures that the reference signal is in phase with the signal sent to the antenna when the impedance of the antenna is 50 Ω. In matching mode, the capacitor bank is adjusted to maintain antenna matching. In operation mode, the circuit is shut off allowing for low power consumption (85 nW while matching every 1 ms). The circuit is able to provide a VSWR < 2 over a wide range of antenna impedance levels. It is designed in CMOS 0.13 μm technology.
{"title":"An efficient reference-based adaptive antenna impedance matching CMOS circuit","authors":"A. Robichaud, F. Nabki, D. Deslandes","doi":"10.1109/ISCAS.2016.7527512","DOIUrl":"https://doi.org/10.1109/ISCAS.2016.7527512","url":null,"abstract":"This paper presents a simple integrated reference based adaptive matching network capable of undertaking real time antenna tuning for applications such as wearable wireless sensors. The signal sent to the antenna is compared to a reference signal using a single flip-flop acting as a phase detector. In case of an impedance mismatch, a counter controlling a capacitor bank is activated reducing the sensed mismatch. The system is capable of three modes: calibration, matching and operation. The calibration mode ensures that the reference signal is in phase with the signal sent to the antenna when the impedance of the antenna is 50 Ω. In matching mode, the capacitor bank is adjusted to maintain antenna matching. In operation mode, the circuit is shut off allowing for low power consumption (85 nW while matching every 1 ms). The circuit is able to provide a VSWR < 2 over a wide range of antenna impedance levels. It is designed in CMOS 0.13 μm technology.","PeriodicalId":6546,"journal":{"name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"63 1","pages":"1402-1405"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85271258","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-22DOI: 10.1109/ISCAS.2016.7527277
H. Molaei, Ata Khorami, K. Hajsadeghi
The most challenging issue of conventional Time Amplifiers (TAs) is their limited Dynamic Range (DR). This paper presents a mathematical analysis to clarify principle of operation of conventional 2× TA's. The mathematical derivations release strength reduction of the current sources of the TA is the simplest way to increase DR. Besides, a new technique is presented to expand the Dynamic Range (DR) of conventional 2× TAs. Proposed technique employs current subtraction in place of changing strength of current sources using conventional gain compensation methods, which results in more stable gain over a wider DR. The TA is simulated using Spectre-rf in TSMC 0.18um COMS technology. DR of the 2× TA is expanded to 300ps only with 9% gain error while it consumes only 28uW from a 1.2V supply voltage.
{"title":"A wide dynamic range low power 2× time amplifier using current subtraction scheme","authors":"H. Molaei, Ata Khorami, K. Hajsadeghi","doi":"10.1109/ISCAS.2016.7527277","DOIUrl":"https://doi.org/10.1109/ISCAS.2016.7527277","url":null,"abstract":"The most challenging issue of conventional Time Amplifiers (TAs) is their limited Dynamic Range (DR). This paper presents a mathematical analysis to clarify principle of operation of conventional 2× TA's. The mathematical derivations release strength reduction of the current sources of the TA is the simplest way to increase DR. Besides, a new technique is presented to expand the Dynamic Range (DR) of conventional 2× TAs. Proposed technique employs current subtraction in place of changing strength of current sources using conventional gain compensation methods, which results in more stable gain over a wider DR. The TA is simulated using Spectre-rf in TSMC 0.18um COMS technology. DR of the 2× TA is expanded to 300ps only with 9% gain error while it consumes only 28uW from a 1.2V supply voltage.","PeriodicalId":6546,"journal":{"name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"21 1","pages":"462-465"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81995090","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a low-power 14-bit column-level ADC for 640×512 size uncooled infrared imager. A novel differential-ramp single-slope (DRSS) structure is proposed in this work, which achieves 2x faster conversion speed and 3dB higher SNR performance compared with classical single-slope scheme. Moreover, a novel low-power area-saving result-consistent coarse-fine TDC scheme is proposed. The sensor with 17μm pixel pitch has been realized in 0.5 μm 2P3M CMOS process and applied in the thermal imaging system. Power consumption of per ADC is 120 μW. Measurement results demonstrate an average output RMS noise of 0.5LSB and a maximum nonlinearity of 3LSB.
{"title":"A 14-bit differential-ramp single-slope column-level ADC for 640×512 uncooled infrared imager","authors":"Dahe Liu, Wengao Lu, Zhongjian Chen, Yacong Zhang, Shuyu Lei, Guo Tan","doi":"10.1109/ISCAS.2016.7538949","DOIUrl":"https://doi.org/10.1109/ISCAS.2016.7538949","url":null,"abstract":"This paper presents a low-power 14-bit column-level ADC for 640×512 size uncooled infrared imager. A novel differential-ramp single-slope (DRSS) structure is proposed in this work, which achieves 2x faster conversion speed and 3dB higher SNR performance compared with classical single-slope scheme. Moreover, a novel low-power area-saving result-consistent coarse-fine TDC scheme is proposed. The sensor with 17μm pixel pitch has been realized in 0.5 μm 2P3M CMOS process and applied in the thermal imaging system. Power consumption of per ADC is 120 μW. Measurement results demonstrate an average output RMS noise of 0.5LSB and a maximum nonlinearity of 3LSB.","PeriodicalId":6546,"journal":{"name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"73 1","pages":"1922-1925"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83624154","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-22DOI: 10.1109/ISCAS.2016.7527245
Qian Wang, Youjie Li, Peng Li
This paper presents an FPGA architecture and implementation of the Liquid State Machine, a spiking neural network model, for real world pattern recognition problems. The proposed architecture consists of a parallel digital reservoir with fixed synapses, and a readout stage that is tuned by a biologically plausible supervised learning rule. When evaluated using the TI46 speech corpus, a widely adopted speech recognition benchmark, the presented FPGA neuromorphic processors demonstrate highly competitive recognition performance and provide a runtime speedup of 88X over the 2.3 GHz AMD OpteronTM Processor. A number of critical design issues such as interconnection of liquid neurons, storage of synaptic weights and design of arithmetic blocks are addressed in this work. More importantly, it is shown that the unique computational structure and inherent resilience of the liquid state machine can be leveraged for highly efficient FPGA implementation. For t Iiis, it is demonstrated that the proposed firing-activity based power gating and approximate arithmetic computing with runtime adjustable precision can lead to up to 30.2% reduction in power and energy dissipation without greatly impacting speech recognition performance.
{"title":"Liquid state machine based pattern recognition on FPGA with firing-activity dependent power gating and approximate computing","authors":"Qian Wang, Youjie Li, Peng Li","doi":"10.1109/ISCAS.2016.7527245","DOIUrl":"https://doi.org/10.1109/ISCAS.2016.7527245","url":null,"abstract":"This paper presents an FPGA architecture and implementation of the Liquid State Machine, a spiking neural network model, for real world pattern recognition problems. The proposed architecture consists of a parallel digital reservoir with fixed synapses, and a readout stage that is tuned by a biologically plausible supervised learning rule. When evaluated using the TI46 speech corpus, a widely adopted speech recognition benchmark, the presented FPGA neuromorphic processors demonstrate highly competitive recognition performance and provide a runtime speedup of 88X over the 2.3 GHz AMD OpteronTM Processor. A number of critical design issues such as interconnection of liquid neurons, storage of synaptic weights and design of arithmetic blocks are addressed in this work. More importantly, it is shown that the unique computational structure and inherent resilience of the liquid state machine can be leveraged for highly efficient FPGA implementation. For t Iiis, it is demonstrated that the proposed firing-activity based power gating and approximate arithmetic computing with runtime adjustable precision can lead to up to 30.2% reduction in power and energy dissipation without greatly impacting speech recognition performance.","PeriodicalId":6546,"journal":{"name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"2 1","pages":"361-364"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89244269","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-22DOI: 10.1109/ISCAS.2016.7539093
J. Agustin, M. López-Vallejo
In this work we propose a Ring Oscillator PUF focused on the variability of the duty cycle instead of measuring the output frequency deviations. To achieve this goal, we replace the common ring oscillators, whose outputs are clock signals of 50% duty cycle, for ring oscillators with an asymmetric structure. The asymmetry confers the ability to configure the duty cycle of each individual node. Through the measurement of a relative value, such as the duty cycle, the robustness of the PUF is improved. For example, the output shift due to the temperature variation is decreased from 3% to less than 0,5%. Moreover, the potential input challenges are multiplied by the number of stages of each ring oscillator. Hence, with our design, the number of ring oscillators needed to build a robust PUF is decreased thanks to the addition of multiple and uncorrelated variables but with negligible area overhead.
{"title":"A temperature-independent PUF with a configurable duty cycle of CMOS ring oscillators","authors":"J. Agustin, M. López-Vallejo","doi":"10.1109/ISCAS.2016.7539093","DOIUrl":"https://doi.org/10.1109/ISCAS.2016.7539093","url":null,"abstract":"In this work we propose a Ring Oscillator PUF focused on the variability of the duty cycle instead of measuring the output frequency deviations. To achieve this goal, we replace the common ring oscillators, whose outputs are clock signals of 50% duty cycle, for ring oscillators with an asymmetric structure. The asymmetry confers the ability to configure the duty cycle of each individual node. Through the measurement of a relative value, such as the duty cycle, the robustness of the PUF is improved. For example, the output shift due to the temperature variation is decreased from 3% to less than 0,5%. Moreover, the potential input challenges are multiplied by the number of stages of each ring oscillator. Hence, with our design, the number of ring oscillators needed to build a robust PUF is decreased thanks to the addition of multiple and uncorrelated variables but with negligible area overhead.","PeriodicalId":6546,"journal":{"name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"15 1","pages":"2471-2474"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84829931","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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