Pub Date : 2016-05-22DOI: 10.1109/ISCAS.2016.7538909
Weng-Geng Ho, Nan Liu, K. Z. L. Ne, Kwen-Siong Chong, B. Gwee, J. Chang
We propose a novel Template-based Cell-Interleave Pipeline (TCIP) approach for generating high performance and yet low overhead asynchronous-logic (async) quasi-delay-insensitive (QDI) circuits. Our TCIP approach exploits the characteristics of the four prevalent QDI cell templates, namely Weak-Conditioned Half-Buffer (WCHB), Pre-Charged HalfBuffer (PCHB), Autonomous Signal-Validity Half-Buffer (ASVHB), and Sense-Amplifier Half-Buffer (SAHB), and then strategically interleave these template cells to form a composite pipeline. There are three main features in our TCIP approach. First, all QDI cell templates are first standardized with the same interface signals, and their corresponding cells are characterized in terms of transistor count, cycle time and energy dissipation for ease of comparison/selection/replacement. Second, our TCIP approach prioritizes the speed requirement when forming the initial pipeline circuits, and then subsequently reduces circuit overheads by interleaving various template cells without compromising the speed significantly. Third, the final optimized QDI pipeline circuit inherently features high robustness against process-voltage-temperature (PVT) variations, hence suitable for dynamic-voltage-scaling (DVS) operation. By means of 65nm CMOS process, we demonstrate a 4-bit pipeline tree adder based on the proposed TCIP approach, and benchmark it against the WCHB, PCHB, ASVHB and SAHB counterparts. These five designs feature same high operational robustness, nonetheless the design based on our TCIP approach is more competitive. Particularly, the designs based on reported approaches are, on average, ~1.22× more transistor count, ~1.21× slower and ~1.22× higher energy dissipation. Furthermore, under DVS operation from 1.2V to 0.3V, our proposed TCIP adder can reduce up to 88% energy for non-speed critical applications.
{"title":"High performance low overhead template-based Cell-Interleave Pipeline (TCIP) for asynchronous-logic QDI circuits","authors":"Weng-Geng Ho, Nan Liu, K. Z. L. Ne, Kwen-Siong Chong, B. Gwee, J. Chang","doi":"10.1109/ISCAS.2016.7538909","DOIUrl":"https://doi.org/10.1109/ISCAS.2016.7538909","url":null,"abstract":"We propose a novel Template-based Cell-Interleave Pipeline (TCIP) approach for generating high performance and yet low overhead asynchronous-logic (async) quasi-delay-insensitive (QDI) circuits. Our TCIP approach exploits the characteristics of the four prevalent QDI cell templates, namely Weak-Conditioned Half-Buffer (WCHB), Pre-Charged HalfBuffer (PCHB), Autonomous Signal-Validity Half-Buffer (ASVHB), and Sense-Amplifier Half-Buffer (SAHB), and then strategically interleave these template cells to form a composite pipeline. There are three main features in our TCIP approach. First, all QDI cell templates are first standardized with the same interface signals, and their corresponding cells are characterized in terms of transistor count, cycle time and energy dissipation for ease of comparison/selection/replacement. Second, our TCIP approach prioritizes the speed requirement when forming the initial pipeline circuits, and then subsequently reduces circuit overheads by interleaving various template cells without compromising the speed significantly. Third, the final optimized QDI pipeline circuit inherently features high robustness against process-voltage-temperature (PVT) variations, hence suitable for dynamic-voltage-scaling (DVS) operation. By means of 65nm CMOS process, we demonstrate a 4-bit pipeline tree adder based on the proposed TCIP approach, and benchmark it against the WCHB, PCHB, ASVHB and SAHB counterparts. These five designs feature same high operational robustness, nonetheless the design based on our TCIP approach is more competitive. Particularly, the designs based on reported approaches are, on average, ~1.22× more transistor count, ~1.21× slower and ~1.22× higher energy dissipation. Furthermore, under DVS operation from 1.2V to 0.3V, our proposed TCIP adder can reduce up to 88% energy for non-speed critical applications.","PeriodicalId":6546,"journal":{"name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"34 1","pages":"1762-1765"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91234674","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-22DOI: 10.1109/ISCAS.2016.7527304
Yanbo Gao, Ce Zhu, Shuai Li
Hierarchical coding structure (HCS) is one of the most important components in High Efficiency Video Coding (HEVC) that improves the coding performance greatly, especially for Low-Delay (LD) coding. It groups frames into different layers and enc odes them with different quantization parameters (QP) and different reference mechanisms. Due to the extensively used inter-prediction, the coding of frames in different layers is highly dependent and an appropriate QP and reference selection scheme may significantly improve the performance by taking advantage of such temporal dependency. However in the current HEVC codec, a predefined HCS, such as the Low-Delay HCS (LD-HCS), is performed without considering the different characteristic of different video contents, thus leading to a suboptimal coding solution. In this paper, the hierarchical temporal relationship under LD-HCS is first investigated and a hierarchical temporal propagation chain is constructed to describe the temporal dependency among frames. Then a hierarchical temporal dependent rate-distortion optimization scheme is developed specifically for the LD-HCS in HEVC. Experiments results show that the proposed scheme achieves BD-rate saving of 2.9% and 2.8% in average against HEVC codec under LD-HCS of P and B frames, respectively, with a negligible increase in encoding time.
{"title":"Hierarchical temporal dependent rate-distortion optimization for low-delay coding","authors":"Yanbo Gao, Ce Zhu, Shuai Li","doi":"10.1109/ISCAS.2016.7527304","DOIUrl":"https://doi.org/10.1109/ISCAS.2016.7527304","url":null,"abstract":"Hierarchical coding structure (HCS) is one of the most important components in High Efficiency Video Coding (HEVC) that improves the coding performance greatly, especially for Low-Delay (LD) coding. It groups frames into different layers and enc odes them with different quantization parameters (QP) and different reference mechanisms. Due to the extensively used inter-prediction, the coding of frames in different layers is highly dependent and an appropriate QP and reference selection scheme may significantly improve the performance by taking advantage of such temporal dependency. However in the current HEVC codec, a predefined HCS, such as the Low-Delay HCS (LD-HCS), is performed without considering the different characteristic of different video contents, thus leading to a suboptimal coding solution. In this paper, the hierarchical temporal relationship under LD-HCS is first investigated and a hierarchical temporal propagation chain is constructed to describe the temporal dependency among frames. Then a hierarchical temporal dependent rate-distortion optimization scheme is developed specifically for the LD-HCS in HEVC. Experiments results show that the proposed scheme achieves BD-rate saving of 2.9% and 2.8% in average against HEVC codec under LD-HCS of P and B frames, respectively, with a negligible increase in encoding time.","PeriodicalId":6546,"journal":{"name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"37 1","pages":"570-573"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91292392","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-22DOI: 10.1109/ISCAS.2016.7527263
Dalvir K. Saini, A. Ayachit, M. Kazimierczuk, H. Sekiya
The following closed-loop transfer functions of the boost converter operating in continuous-conduction mode (CCM) supplying a complex impedance load are derived and analyzed: input-to-output voltage Mvcl and reference-to-output Tcl. The load of the boost dc-dc converter is composed of a series-connected resistance and inductance. The dynamic characteristics of the closed-loop boost converter with a third-order double-lead integral compensator are evaluated for different load inductances. The theoretically predicted results are validated through switching-circuit simulations using a suitable converter design example.
{"title":"Small-signal analysis of closed-loop PWM boost converter in CCM with complex impedance load","authors":"Dalvir K. Saini, A. Ayachit, M. Kazimierczuk, H. Sekiya","doi":"10.1109/ISCAS.2016.7527263","DOIUrl":"https://doi.org/10.1109/ISCAS.2016.7527263","url":null,"abstract":"The following closed-loop transfer functions of the boost converter operating in continuous-conduction mode (CCM) supplying a complex impedance load are derived and analyzed: input-to-output voltage Mvcl and reference-to-output Tcl. The load of the boost dc-dc converter is composed of a series-connected resistance and inductance. The dynamic characteristics of the closed-loop boost converter with a third-order double-lead integral compensator are evaluated for different load inductances. The theoretically predicted results are validated through switching-circuit simulations using a suitable converter design example.","PeriodicalId":6546,"journal":{"name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"27 1","pages":"433-436"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89473736","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-22DOI: 10.1109/ISCAS.2016.7527334
J. Eshraghian, H. Iu, T. Fernando, Dongsheng Yu, Zhen Li
This paper explores the dynamic behavior of dual flux coupled memristor circuits in order to further ascertain fundamental theory of memristor circuits. Different cases of flux coupling are mathematically modelled where two memristors are connected in both series and parallel, with consideration given to the polarity of each device. The dynamic behavior is characterized based on the constitutive relations, with a variation of memductance represented in terms of flux, charge, voltage and current. The agreement between theoretical and simulation analyses affirm the memristor closure theorem with coupled memristor circuits behaving as a different type of memristor with higher complexity.
{"title":"Modelling and characterization of dynamic behavior of coupled memristor circuits","authors":"J. Eshraghian, H. Iu, T. Fernando, Dongsheng Yu, Zhen Li","doi":"10.1109/ISCAS.2016.7527334","DOIUrl":"https://doi.org/10.1109/ISCAS.2016.7527334","url":null,"abstract":"This paper explores the dynamic behavior of dual flux coupled memristor circuits in order to further ascertain fundamental theory of memristor circuits. Different cases of flux coupling are mathematically modelled where two memristors are connected in both series and parallel, with consideration given to the polarity of each device. The dynamic behavior is characterized based on the constitutive relations, with a variation of memductance represented in terms of flux, charge, voltage and current. The agreement between theoretical and simulation analyses affirm the memristor closure theorem with coupled memristor circuits behaving as a different type of memristor with higher complexity.","PeriodicalId":6546,"journal":{"name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"10 1","pages":"690-693"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90121035","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-22DOI: 10.1109/ISCAS.2016.7527239
M. Magno, G. Salvatore, S. Mutter, Waleed Farrukh, G. Tröster, L. Benini
Epidermal sensors, which form an intimate and robust contact with the skin, are capable of providing clinically relevant information about cardiovascular health, electrophysiology and dermatology with high accuracy and in an unobtrusive manner. To enable clinical applications, however, continuous and long-term monitoring is necessary. In addition, wireless and energetically autonomous systems are highly desirable to eliminate the needs of tethers and cables for powering and data transmission. Such requirements call for devices that combine accurate and precise sensing with high performance electronics for signal treatment, communication and power management in formats which conformal laminate on the body. In this work, we present a novel system whose design leverages on the recent developments in low power wearable devices and flexible sensors. It consists of an ultra-low power smartwatch connected to flexible solar modules assembled on a strap and an array of epidermal temperature sensors which are mounted on the wrist. Preliminary experiments show how this platform is well-suited for long-term, accurate and continuous mapping of the temperature of the skin.
{"title":"Autonomous smartwatch with flexible sensors for accurate and continuous mapping of skin temperature","authors":"M. Magno, G. Salvatore, S. Mutter, Waleed Farrukh, G. Tröster, L. Benini","doi":"10.1109/ISCAS.2016.7527239","DOIUrl":"https://doi.org/10.1109/ISCAS.2016.7527239","url":null,"abstract":"Epidermal sensors, which form an intimate and robust contact with the skin, are capable of providing clinically relevant information about cardiovascular health, electrophysiology and dermatology with high accuracy and in an unobtrusive manner. To enable clinical applications, however, continuous and long-term monitoring is necessary. In addition, wireless and energetically autonomous systems are highly desirable to eliminate the needs of tethers and cables for powering and data transmission. Such requirements call for devices that combine accurate and precise sensing with high performance electronics for signal treatment, communication and power management in formats which conformal laminate on the body. In this work, we present a novel system whose design leverages on the recent developments in low power wearable devices and flexible sensors. It consists of an ultra-low power smartwatch connected to flexible solar modules assembled on a strap and an array of epidermal temperature sensors which are mounted on the wrist. Preliminary experiments show how this platform is well-suited for long-term, accurate and continuous mapping of the temperature of the skin.","PeriodicalId":6546,"journal":{"name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"38 1","pages":"337-340"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88486950","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-22DOI: 10.1109/ISCAS.2016.7539121
Zahi Moudallal, F. Najm
Efficient verification of the chip power distribution network is a critical task in modern chip design. It should be done early in the design process where adjustments can be most easily incorporated. As an alternative to simulation based methods, vectorless verification is a class of techniques that requires user-specified current constraints (budgets), and checks if the corresponding worst-case voltage drops at all grid nodes are below user-specified thresholds. However, obtaining/specifying the current constraints remains a burdensome task for users. Recent literature has addressed the constraints generation problem by proposing the inverse problem: for a given grid, we would like to generate circuit current constraints which, if adhered to by the underlying logic, would guarantee grid safety. In this paper, we adopt the same framework. We develop an efficient algorithm for constraints generation that targets a key grid quality metric namely the uniformity of temperature distribution across the die area.
{"title":"Generating voltage drop aware current budgets for RC power grids","authors":"Zahi Moudallal, F. Najm","doi":"10.1109/ISCAS.2016.7539121","DOIUrl":"https://doi.org/10.1109/ISCAS.2016.7539121","url":null,"abstract":"Efficient verification of the chip power distribution network is a critical task in modern chip design. It should be done early in the design process where adjustments can be most easily incorporated. As an alternative to simulation based methods, vectorless verification is a class of techniques that requires user-specified current constraints (budgets), and checks if the corresponding worst-case voltage drops at all grid nodes are below user-specified thresholds. However, obtaining/specifying the current constraints remains a burdensome task for users. Recent literature has addressed the constraints generation problem by proposing the inverse problem: for a given grid, we would like to generate circuit current constraints which, if adhered to by the underlying logic, would guarantee grid safety. In this paper, we adopt the same framework. We develop an efficient algorithm for constraints generation that targets a key grid quality metric namely the uniformity of temperature distribution across the die area.","PeriodicalId":6546,"journal":{"name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"158 Suppl 1 1","pages":"2583-2586"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73540067","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-22DOI: 10.1109/ISCAS.2016.7527394
Hao Jiang, Weijie Zhu, Fu Luo, Kangjun Bai, Chenchen Liu, Xiaorong Zhang, J. Yang, Q. Xia, Yiran Chen, Qing Wu
The brain-inspired, spike-based neuromorphic system is highly anticipated in the artificial intelligence community due to its high computational efficiency. The recently developed memristor-crossbar-array technology, which is able to efficiently emulate the plasticity of biological synapses and accommodate matrix multiplication, has demonstrated its potential for neuromorphic computing. To facilitate the computation, a high-speed integrate-and-fire circuit (IFC) and a counter were previously developed to efficiently convert the current from the memristor array into rate-coded spikes. However, the linear dynamic range of the circuit, which is limited by its responding speed, is challenged when the input intensity and the conductance of the memristor array are both high simultaneously. In this paper, a novel cyclical sensing scheme is developed that can significantly extend the linear dynamic range of the original IFC. Meanwhile, the power efficiency of the IFC can also be increased. The circuit simulation results indicated that the cyclical sensing IFC was able to efficiently and accurately facilitate the matrix multiplication when it was integrated with a 32×32 memristor crossbar array. With the optimized crossbar array structure and its peripheral circuits, the developed cyclical sensing IFC has shown great promise in accelerating matrix multiplication in spike-based computing systems.
{"title":"Cyclical sensing integrate-and-fire circuit for memristor array based neuromorphic computing","authors":"Hao Jiang, Weijie Zhu, Fu Luo, Kangjun Bai, Chenchen Liu, Xiaorong Zhang, J. Yang, Q. Xia, Yiran Chen, Qing Wu","doi":"10.1109/ISCAS.2016.7527394","DOIUrl":"https://doi.org/10.1109/ISCAS.2016.7527394","url":null,"abstract":"The brain-inspired, spike-based neuromorphic system is highly anticipated in the artificial intelligence community due to its high computational efficiency. The recently developed memristor-crossbar-array technology, which is able to efficiently emulate the plasticity of biological synapses and accommodate matrix multiplication, has demonstrated its potential for neuromorphic computing. To facilitate the computation, a high-speed integrate-and-fire circuit (IFC) and a counter were previously developed to efficiently convert the current from the memristor array into rate-coded spikes. However, the linear dynamic range of the circuit, which is limited by its responding speed, is challenged when the input intensity and the conductance of the memristor array are both high simultaneously. In this paper, a novel cyclical sensing scheme is developed that can significantly extend the linear dynamic range of the original IFC. Meanwhile, the power efficiency of the IFC can also be increased. The circuit simulation results indicated that the cyclical sensing IFC was able to efficiently and accurately facilitate the matrix multiplication when it was integrated with a 32×32 memristor crossbar array. With the optimized crossbar array structure and its peripheral circuits, the developed cyclical sensing IFC has shown great promise in accelerating matrix multiplication in spike-based computing systems.","PeriodicalId":6546,"journal":{"name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"1 1","pages":"930-933"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76838041","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-22DOI: 10.1109/ISCAS.2016.7527501
H. Heidari, W. Navaraj, G. Toldi, R. Dahiya
This paper presents the directions for computer aided design, modelling and simulation of bendable MOSFET transistors towards futuristic bendable ICs. In order to compensate the bending stress a generalised geometry variation is discussed. Based on drain-current and threshold-voltage parameters varying under the bending stress, a Verilog-A compact model is proposed and describes I-V characteristics of a MOSFET in a standard 0.18-μm CMOS technology. This model has been compiled into Cadence environment to predict value and orientation of the bending stress. The proposed model validates against macro-model simulation results, and agrees for both the electron and hole conduction. It has been found that there is significant performance advantage in process-induced uniaxial stressed n-MOSFET, exhibiting a smaller drain-current variation and thresh old voltage shift by monitoring the bending stress and changing the supply voltage.
{"title":"Device modelling of bendable MOS transistors","authors":"H. Heidari, W. Navaraj, G. Toldi, R. Dahiya","doi":"10.1109/ISCAS.2016.7527501","DOIUrl":"https://doi.org/10.1109/ISCAS.2016.7527501","url":null,"abstract":"This paper presents the directions for computer aided design, modelling and simulation of bendable MOSFET transistors towards futuristic bendable ICs. In order to compensate the bending stress a generalised geometry variation is discussed. Based on drain-current and threshold-voltage parameters varying under the bending stress, a Verilog-A compact model is proposed and describes I-V characteristics of a MOSFET in a standard 0.18-μm CMOS technology. This model has been compiled into Cadence environment to predict value and orientation of the bending stress. The proposed model validates against macro-model simulation results, and agrees for both the electron and hole conduction. It has been found that there is significant performance advantage in process-induced uniaxial stressed n-MOSFET, exhibiting a smaller drain-current variation and thresh old voltage shift by monitoring the bending stress and changing the supply voltage.","PeriodicalId":6546,"journal":{"name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"57 1","pages":"1358-1361"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76962666","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-22DOI: 10.1109/ISCAS.2016.7527529
D. Muratore, E. Bonizzoni, F. Maloberti
This paper presents a novel pipeline configuration for wireless applications. Redundancy and multi sampling of the input techniques are used for overcoming the main limitations of pipeline ADCs. A special pre-amplifier with built-in thresholds generation is also discussed. The circuit, designed and simulated in a 65-nm CMOS technology, achieves 2.66 GS/s and 8-bit resolution. The supply voltage is 1V and the simulated power consumption is 22.06 mW, which leads to a FoM of 32.4 fJ/conversion-step.
{"title":"A pipeline ADC for very high conversion rates","authors":"D. Muratore, E. Bonizzoni, F. Maloberti","doi":"10.1109/ISCAS.2016.7527529","DOIUrl":"https://doi.org/10.1109/ISCAS.2016.7527529","url":null,"abstract":"This paper presents a novel pipeline configuration for wireless applications. Redundancy and multi sampling of the input techniques are used for overcoming the main limitations of pipeline ADCs. A special pre-amplifier with built-in thresholds generation is also discussed. The circuit, designed and simulated in a 65-nm CMOS technology, achieves 2.66 GS/s and 8-bit resolution. The supply voltage is 1V and the simulated power consumption is 22.06 mW, which leads to a FoM of 32.4 fJ/conversion-step.","PeriodicalId":6546,"journal":{"name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"100 1","pages":"1446-1449"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76989405","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-22DOI: 10.1109/ISCAS.2016.7527479
G. Giustolisi, G. Palumbo, P. Finocchiaro, A. Pappalardo
The Silicon Photomultiplier (SiPM) is a promising kind of device able to detect single photons thus permitting the measurement of weak optical signals. The design of high-performance front-end electronics for the read-out, require an accurate model of the SiPM. In this paper we propose a new SiPM model implemented through the behavioral language Verilog-a and suitable for transistor-level circuit simulation. The model is based on a traditional electrical model and a statistical modeling to implement the SiPM noise characteristic in terms of dark-count and after-pulsing phenomena. We also provide a procedure for extracting the model parameters from measurements and validate both the extraction procedure and the Verilog-a model by comparing simulations to measurement results.
{"title":"Verilog-a modeling of Silicon Photo-Multipliers","authors":"G. Giustolisi, G. Palumbo, P. Finocchiaro, A. Pappalardo","doi":"10.1109/ISCAS.2016.7527479","DOIUrl":"https://doi.org/10.1109/ISCAS.2016.7527479","url":null,"abstract":"The Silicon Photomultiplier (SiPM) is a promising kind of device able to detect single photons thus permitting the measurement of weak optical signals. The design of high-performance front-end electronics for the read-out, require an accurate model of the SiPM. In this paper we propose a new SiPM model implemented through the behavioral language Verilog-a and suitable for transistor-level circuit simulation. The model is based on a traditional electrical model and a statistical modeling to implement the SiPM noise characteristic in terms of dark-count and after-pulsing phenomena. We also provide a procedure for extracting the model parameters from measurements and validate both the extraction procedure and the Verilog-a model by comparing simulations to measurement results.","PeriodicalId":6546,"journal":{"name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"6 1","pages":"1270-1273"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78575303","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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