Pub Date : 2017-09-01DOI: 10.1109/DASIP.2017.8122131
Bibek Kabi, Anand S. Sahadevan, Tapan Pradhan
We consider the problem of enabling robust range estimation of eigenvalue decomposition (EVD) algorithm for a reliable fixed-point design. The simplicity of fixed-point circuitry has always been so tempting to implement EVD algorithms in fixed-point arithmetic. Working towards an effective fixed-point design, integer bit-width allocation is a significant step which has a crucial impact on accuracy and hardware efficiency. This paper investigates the shortcomings of the existing range estimation methods while deriving bounds for the variables of the EVD algorithm. In light of the circumstances, we introduce a range estimation approach based on vector and matrix norm properties together with a scaling procedure that maintains all the assets of an analytical method. The method could derive robust and tight bounds for the variables of EVD algorithm. The bounds derived using the proposed approach remain same for any input matrix and are also independent of the number of iterations or size of the problem. Some benchmark hyperspectral data sets have been used to evaluate the efficiency of the proposed technique. It was found that by the proposed range estimation approach, all the variables generated during the computation of Jacobi EVD is bounded within ±1.
{"title":"An overflow free fixed-point eigenvalue decomposition algorithm: Case study of dimensionality reduction in hyperspectral images","authors":"Bibek Kabi, Anand S. Sahadevan, Tapan Pradhan","doi":"10.1109/DASIP.2017.8122131","DOIUrl":"https://doi.org/10.1109/DASIP.2017.8122131","url":null,"abstract":"We consider the problem of enabling robust range estimation of eigenvalue decomposition (EVD) algorithm for a reliable fixed-point design. The simplicity of fixed-point circuitry has always been so tempting to implement EVD algorithms in fixed-point arithmetic. Working towards an effective fixed-point design, integer bit-width allocation is a significant step which has a crucial impact on accuracy and hardware efficiency. This paper investigates the shortcomings of the existing range estimation methods while deriving bounds for the variables of the EVD algorithm. In light of the circumstances, we introduce a range estimation approach based on vector and matrix norm properties together with a scaling procedure that maintains all the assets of an analytical method. The method could derive robust and tight bounds for the variables of EVD algorithm. The bounds derived using the proposed approach remain same for any input matrix and are also independent of the number of iterations or size of the problem. Some benchmark hyperspectral data sets have been used to evaluate the efficiency of the proposed technique. It was found that by the proposed range estimation approach, all the variables generated during the computation of Jacobi EVD is bounded within ±1.","PeriodicalId":6637,"journal":{"name":"2017 Conference on Design and Architectures for Signal and Image Processing (DASIP)","volume":"15 1","pages":"1-9"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79128930","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-09-01DOI: 10.1109/DASIP.2017.8122114
O. Ibraheem, Arif Irwansyah, J. Hagemeyer, Mario Porrmann, U. Rückert
In recent years, there has been an increasing growth of using vision-based systems for tracking the players in team sports to evaluate and enhance their performance. Vision-based player tracking has high computational demands since it requires processing of a huge amount of video data based on the utilization of multiple cameras with high resolution and high frame rates. In this paper, we present a reconfigurable system to track the players in indoor sports automatically without user interaction. The proposed system can process live video data streams from multiple cameras as well as offline data from recorded video files. FPGA technology is used to accelerate this player tracking system by implementing the video acquisition, video preprocessing, player segmentation, and team identification & player detection modules in hardware, realizing a real-time system. The teams are identified and the players' positions are detected based on the colors of their jerseys. The detection results are sent from the FPGA to the host-PC where the players are tracked. Our results show that the achieved average player detection rate is up to 95.5%. The proposed system can process live video data using two GigE Vision cameras with a resolution of 1392×1040 pixels and 30 fps for each camera. A speed-up of 20 is achieved compared to an OpenCV-based software implementation on a host-PC equipped with a 2.93 GHz Intel i7 CPU.
{"title":"Reconfigurable vision processing system for player tracking in indoor sports","authors":"O. Ibraheem, Arif Irwansyah, J. Hagemeyer, Mario Porrmann, U. Rückert","doi":"10.1109/DASIP.2017.8122114","DOIUrl":"https://doi.org/10.1109/DASIP.2017.8122114","url":null,"abstract":"In recent years, there has been an increasing growth of using vision-based systems for tracking the players in team sports to evaluate and enhance their performance. Vision-based player tracking has high computational demands since it requires processing of a huge amount of video data based on the utilization of multiple cameras with high resolution and high frame rates. In this paper, we present a reconfigurable system to track the players in indoor sports automatically without user interaction. The proposed system can process live video data streams from multiple cameras as well as offline data from recorded video files. FPGA technology is used to accelerate this player tracking system by implementing the video acquisition, video preprocessing, player segmentation, and team identification & player detection modules in hardware, realizing a real-time system. The teams are identified and the players' positions are detected based on the colors of their jerseys. The detection results are sent from the FPGA to the host-PC where the players are tracked. Our results show that the achieved average player detection rate is up to 95.5%. The proposed system can process live video data using two GigE Vision cameras with a resolution of 1392×1040 pixels and 30 fps for each camera. A speed-up of 20 is achieved compared to an OpenCV-based software implementation on a host-PC equipped with a 2.93 GHz Intel i7 CPU.","PeriodicalId":6637,"journal":{"name":"2017 Conference on Design and Architectures for Signal and Image Processing (DASIP)","volume":"28 1","pages":"1-6"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83509331","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-09-01DOI: 10.1109/DASIP.2017.8122115
T. Nguyen, A. Mouraud, M. Thévenin, G. Corre, O. Pasquier, S. Pillement
When designing a Multi-Processor System-on-Chip (MPSoC), a very large range of design alternatives arises from a huge space of possible design options and component choices. Literature proposes numerous Design-Space-Exploration (DSE) approaches thats mainly focus on cost optimization. In this paper, we present a DSE approach which focuses on the reliability of the whole design. This approach is based on a meta-model of Multi-Processor System-on-Chips (MPSoCs) integrated the reliability evaluation. We develop a tool that allows designers to describe and optimize their platform based on the proposed meta-model. The obtained results of an MPSoC is presented including the improved overall reliability of the system thanks to the automatic selection of the fault tolerance strategies for each component.
{"title":"Model-driven reliability evaluation for MPSoC design","authors":"T. Nguyen, A. Mouraud, M. Thévenin, G. Corre, O. Pasquier, S. Pillement","doi":"10.1109/DASIP.2017.8122115","DOIUrl":"https://doi.org/10.1109/DASIP.2017.8122115","url":null,"abstract":"When designing a Multi-Processor System-on-Chip (MPSoC), a very large range of design alternatives arises from a huge space of possible design options and component choices. Literature proposes numerous Design-Space-Exploration (DSE) approaches thats mainly focus on cost optimization. In this paper, we present a DSE approach which focuses on the reliability of the whole design. This approach is based on a meta-model of Multi-Processor System-on-Chips (MPSoCs) integrated the reliability evaluation. We develop a tool that allows designers to describe and optimize their platform based on the proposed meta-model. The obtained results of an MPSoC is presented including the improved overall reliability of the system thanks to the automatic selection of the fault tolerance strategies for each component.","PeriodicalId":6637,"journal":{"name":"2017 Conference on Design and Architectures for Signal and Image Processing (DASIP)","volume":"1 1","pages":"1-6"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90654585","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-09-01DOI: 10.1109/DASIP.2017.8122121
Javier Arcenegui, Rosario Arjona, I. Baturone
A demonstrator has been developed to illustrate the performance of a lightweight fingerprint recognition algorithm based on the feature QFingerMap16, which is extracted from a window of the directional image centered at the convex core of the fingerprint. The algorithm has been implemented into a low-power ARM Cortex-M3 microcontroller included in a Texas Instruments LaunchPad CC2650 evaluation kit. It has been also implemented in a Raspberry Pi 2 so as to show the results obtained at the successive steps of the recognition process with the aid of a Graphical User Interface (GUI). The algorithm offers a good tradeoff between power consumption and recognition accuracy, being suitable for authentication on wearables.
本文开发了一种基于QFingerMap16特征的轻量级指纹识别算法，该特征是从指纹凸核为中心的方向图像窗口中提取的。该算法已在德州仪器(Texas Instruments) LaunchPad CC2650评估套件中的低功耗ARM Cortex-M3微控制器中实现。它还在Raspberry Pi 2中实现，以便在图形用户界面(GUI)的帮助下显示识别过程的连续步骤所获得的结果。该算法在功耗和识别精度之间进行了很好的权衡，适用于可穿戴设备的身份验证。
{"title":"Demonstrator of a fingerprint recognition algorithm into a low-power microcontroller","authors":"Javier Arcenegui, Rosario Arjona, I. Baturone","doi":"10.1109/DASIP.2017.8122121","DOIUrl":"https://doi.org/10.1109/DASIP.2017.8122121","url":null,"abstract":"A demonstrator has been developed to illustrate the performance of a lightweight fingerprint recognition algorithm based on the feature QFingerMap16, which is extracted from a window of the directional image centered at the convex core of the fingerprint. The algorithm has been implemented into a low-power ARM Cortex-M3 microcontroller included in a Texas Instruments LaunchPad CC2650 evaluation kit. It has been also implemented in a Raspberry Pi 2 so as to show the results obtained at the successive steps of the recognition process with the aid of a Graphical User Interface (GUI). The algorithm offers a good tradeoff between power consumption and recognition accuracy, being suitable for authentication on wearables.","PeriodicalId":6637,"journal":{"name":"2017 Conference on Design and Architectures for Signal and Image Processing (DASIP)","volume":"67 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74490186","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-09-01DOI: 10.1109/DASIP.2017.8122127
Sebastian Vogel, A. Guntoro, G. Ascheid
In recent years, Deep Neural Networks (DNNs) have been of special interest in the area of image processing and scene perception. Albeit being effective and accurate, DNNs demand challenging computational resources. Fortunately, dedicated low bitwidth accelerators enable efficient, real-time inference of DNNs. We present an approximate evaluation method and a specialized multiplierless accelerator for the recently proposed bitwise DNNs. Our approximate evaluation method is based on the speculative recomputation of selective parts of a bitwise neural network. The selection is based on the intermediate results of a previous input evaluation. In context with limited energy budgets, our method and accelerator enable a fast, power efficient, first decision. If necessary, a reliable and accurate output is available after reevaluating the input data multiple times in an approximate manner. Our experiments on the GTSRB and CIFAR-10 dataset show that this approach results in no loss of classification performance in comparison with floating-point evaluation. Our work contributes to efficient inference of neural networks on power-constrained embedded devices.
{"title":"Efficient hardware acceleration for approximate inference of bitwise deep neural networks","authors":"Sebastian Vogel, A. Guntoro, G. Ascheid","doi":"10.1109/DASIP.2017.8122127","DOIUrl":"https://doi.org/10.1109/DASIP.2017.8122127","url":null,"abstract":"In recent years, Deep Neural Networks (DNNs) have been of special interest in the area of image processing and scene perception. Albeit being effective and accurate, DNNs demand challenging computational resources. Fortunately, dedicated low bitwidth accelerators enable efficient, real-time inference of DNNs. We present an approximate evaluation method and a specialized multiplierless accelerator for the recently proposed bitwise DNNs. Our approximate evaluation method is based on the speculative recomputation of selective parts of a bitwise neural network. The selection is based on the intermediate results of a previous input evaluation. In context with limited energy budgets, our method and accelerator enable a fast, power efficient, first decision. If necessary, a reliable and accurate output is available after reevaluating the input data multiple times in an approximate manner. Our experiments on the GTSRB and CIFAR-10 dataset show that this approach results in no loss of classification performance in comparison with floating-point evaluation. Our work contributes to efficient inference of neural networks on power-constrained embedded devices.","PeriodicalId":6637,"journal":{"name":"2017 Conference on Design and Architectures for Signal and Image Processing (DASIP)","volume":"104 1","pages":"1-6"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83412995","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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