Pub Date : 2010-07-01DOI: 10.1109/ASAP.2010.5540793
A. Jerraya
The last decade was dominated by HW-SW convergence where designers learned to combine hardware and software design to cope with the increased demand of lower cost and increased performances. This starting decade will be dominated by the convergence between design technology (HW and SW) and fabrication technologies. In fact more and more designs require a deep knowledge of technology characteristics to reach the required performances. On the other side, design technologies are more and more used to overcome fabrication process imperfection and to improve yield. This talk will first explain the achievements in HW-SW convergence and SoC design. Then, it will address the fabrication technology trends and challenges to deal with this convergence.
{"title":"Convergence of design and fabrication technologies, a key enabler for HW-SW integration","authors":"A. Jerraya","doi":"10.1109/ASAP.2010.5540793","DOIUrl":"https://doi.org/10.1109/ASAP.2010.5540793","url":null,"abstract":"The last decade was dominated by HW-SW convergence where designers learned to combine hardware and software design to cope with the increased demand of lower cost and increased performances. This starting decade will be dominated by the convergence between design technology (HW and SW) and fabrication technologies. In fact more and more designs require a deep knowledge of technology characteristics to reach the required performances. On the other side, design technologies are more and more used to overcome fabrication process imperfection and to improve yield. This talk will first explain the achievements in HW-SW convergence and SoC design. Then, it will address the fabrication technology trends and challenges to deal with this convergence.","PeriodicalId":6642,"journal":{"name":"2015 IEEE 26th International Conference on Application-specific Systems, Architectures and Processors (ASAP)","volume":"22 1","pages":"3"},"PeriodicalIF":0.0,"publicationDate":"2010-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82948061","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Modern communication, control, avionic, and radar systems require the use of computationally intensive algebraic operations for real-time high throughput filtering, estimation, tracking, direction-of-arrival, and localization purposes. In this overview paper, we first review some basic systolic array (SA) concept, then SA algorithms for digital filtering, recursive least-squares, QR decomposition, Kalman filtering, eigenvalue and singular value decompositions will be discussed.
{"title":"An Overview of Systolic Array Concepts and Applications for Linear Algebra and Signal Processing","authors":"K. Yao, F. Lorenzelli","doi":"10.1109/ASAP.2006.13","DOIUrl":"https://doi.org/10.1109/ASAP.2006.13","url":null,"abstract":"Modern communication, control, avionic, and radar systems require the use of computationally intensive algebraic operations for real-time high throughput filtering, estimation, tracking, direction-of-arrival, and localization purposes. In this overview paper, we first review some basic systolic array (SA) concept, then SA algorithms for digital filtering, recursive least-squares, QR decomposition, Kalman filtering, eigenvalue and singular value decompositions will be discussed.","PeriodicalId":6642,"journal":{"name":"2015 IEEE 26th International Conference on Application-specific Systems, Architectures and Processors (ASAP)","volume":"127 4 1","pages":"213"},"PeriodicalIF":0.0,"publicationDate":"2006-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83444551","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
For over a decade, the COMAD International Conference on Management of Data, modeled along the lines of ACM SIGMOD, has been the premier database conference hosted in India. It has been held on an approximately annual basis. This year, COMAD will be held in New Delhi during December 14-16, in the beautiful campus of the Indian Institute of Technology, renowned for its world class education and research. New Delhi, the capital city of India is a fusion of the ancient and the modern. Delhi unwinds a picture rich with culture, architecture and human diversity, deep in history, monuments, museums, galleries, gardens and exotic shows. It generates a mesmerizing charm reflecting well-composed and spacious streets under the shade of beautifully lined avenues of trees and tall and imposing government buildings.
{"title":"Message from the Conference Chairs","authors":"S. Gupta, V. Laks, Anthony K H Lakshmanan, Tung","doi":"10.1109/ASAP.2006.45","DOIUrl":"https://doi.org/10.1109/ASAP.2006.45","url":null,"abstract":"For over a decade, the COMAD International Conference on Management of Data, modeled along the lines of ACM SIGMOD, has been the premier database conference hosted in India. It has been held on an approximately annual basis. This year, COMAD will be held in New Delhi during December 14-16, in the beautiful campus of the Indian Institute of Technology, renowned for its world class education and research. New Delhi, the capital city of India is a fusion of the ancient and the modern. Delhi unwinds a picture rich with culture, architecture and human diversity, deep in history, monuments, museums, galleries, gardens and exotic shows. It generates a mesmerizing charm reflecting well-composed and spacious streets under the shade of beautifully lined avenues of trees and tall and imposing government buildings.","PeriodicalId":6642,"journal":{"name":"2015 IEEE 26th International Conference on Application-specific Systems, Architectures and Processors (ASAP)","volume":"33 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2006-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91396166","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The RN-codings, where "RN" stands for "round to nearest", are particular cases of signed digit representations, for which rounding to nearest is always identical to truncation. In radix 2, booth recoding is an RN-coding. In this paper, we suggest several multiplication algorithms able to handle RN-codings, and we analyze their properties.
{"title":"Multiplication Algorithms for Radix-2 RN-Codings and Two's Complement Multiplication Algorithms for Radix-2 RN-Codings and Two's Complement","authors":"Jean-Luc Beuchat, J. Muller","doi":"10.1109/ASAP.2005.45","DOIUrl":"https://doi.org/10.1109/ASAP.2005.45","url":null,"abstract":"The RN-codings, where \"RN\" stands for \"round to nearest\", are particular cases of signed digit representations, for which rounding to nearest is always identical to truncation. In radix 2, booth recoding is an RN-coding. In this paper, we suggest several multiplication algorithms able to handle RN-codings, and we analyze their properties.","PeriodicalId":6642,"journal":{"name":"2015 IEEE 26th International Conference on Application-specific Systems, Architectures and Processors (ASAP)","volume":"43 4 1","pages":"303-308"},"PeriodicalIF":0.0,"publicationDate":"2005-07-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83778520","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Application specific is always a tradeoff among competing design goals (or design parameters). In addition to the well established area (cost) - time (performance) - power metrics specific applications imply a relatively limited market so design cost becomes an especially important consideration. As technology offers increasing transistor density with lower cost power constraints limit frequency as the primary avenue to performance. The alternative is to use area (transistors) to recover performance putting an additional strain on the design budget. The search for flexibility in design without paying a significant area - time - power cost remains the primary problem for application specific and system on a chip (SoC) design.
{"title":"Area - Time - Power and Design effort: the basic tradeoffs in Application Specific Systems","authors":"M. Flynn","doi":"10.1109/ASAP.2005.17","DOIUrl":"https://doi.org/10.1109/ASAP.2005.17","url":null,"abstract":"Application specific is always a tradeoff among competing design goals (or design parameters). In addition to the well established area (cost) - time (performance) - power metrics specific applications imply a relatively limited market so design cost becomes an especially important consideration. As technology offers increasing transistor density with lower cost power constraints limit frequency as the primary avenue to performance. The alternative is to use area (transistors) to recover performance putting an additional strain on the design budget. The search for flexibility in design without paying a significant area - time - power cost remains the primary problem for application specific and system on a chip (SoC) design.","PeriodicalId":6642,"journal":{"name":"2015 IEEE 26th International Conference on Application-specific Systems, Architectures and Processors (ASAP)","volume":"21 1","pages":"3"},"PeriodicalIF":0.0,"publicationDate":"2005-07-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82958823","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a network-based asynchronous architecture that improves the physical-level security of cryptographic devices to known side-channel attacks. This is achieved by decorrelating power consumption measurements by exploiting parallel execution and randomised data-forwarding over a network of functional units. Instructions execute in parallel and forward register values between them, thereby avoiding the register bank. A secret-sharing scheme is used in data-forwarding to remove the effect of sending critical register values through the network, which does not significantly degrade performance and has a positive effect of increasing the noise due to network activity. The simulation results show that both the security threshold and the performance are improved, and the network-based architecture is more robust to differential power analysis when compared to the asynchronous pipelined architecture.
{"title":"Design and Evaluation of a Network-Based Asynchronous Architecture for Cryptographic Devices","authors":"Ljiljana Dilparic, D. Arvind","doi":"10.1109/ASAP.2004.10017","DOIUrl":"https://doi.org/10.1109/ASAP.2004.10017","url":null,"abstract":"This paper presents a network-based asynchronous architecture that improves the physical-level security of cryptographic devices to known side-channel attacks. This is achieved by decorrelating power consumption measurements by exploiting parallel execution and randomised data-forwarding over a network of functional units. Instructions execute in parallel and forward register values between them, thereby avoiding the register bank. A secret-sharing scheme is used in data-forwarding to remove the effect of sending critical register values through the network, which does not significantly degrade performance and has a positive effect of increasing the noise due to network activity. The simulation results show that both the security threshold and the performance are improved, and the network-based architecture is more robust to differential power analysis when compared to the asynchronous pipelined architecture.","PeriodicalId":6642,"journal":{"name":"2015 IEEE 26th International Conference on Application-specific Systems, Architectures and Processors (ASAP)","volume":"27 1","pages":"191-201"},"PeriodicalIF":0.0,"publicationDate":"2004-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77786535","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Digit-Serial Algorithm for the Discrete Logarithm Modulo 2k","authors":"A. Fit-Florea, D. Matula","doi":"10.1109/ASAP.2004.10033","DOIUrl":"https://doi.org/10.1109/ASAP.2004.10033","url":null,"abstract":"","PeriodicalId":6642,"journal":{"name":"2015 IEEE 26th International Conference on Application-specific Systems, Architectures and Processors (ASAP)","volume":"120 1","pages":"236-246"},"PeriodicalIF":0.0,"publicationDate":"2004-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77967007","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-26DOI: 10.1109/ASAP.2003.1212824
R. Lee
Summary form only given. Approaches to cyber security have focused on reactive measures, perimeter security and software implementations. In contrast, we propose a proactive approach to cyber security, where every component, hardware, software or networking, has secure or trustworthy operation as a primary design goal. Architecture for cyber security must be defined at many levels. At the foundational level, if we want core hardware and software to be more responsible for cyber security, what architectural features must be included? How do we translate business and personal security needs, in addition to military and national security needs, into scalable technology features? In this talk, we focus on processors as the engines of the Information Age upon which all software runs. What does it mean for a processor to be security-aware? We illustrate with a few examples. In the area of e-commerce and e-business, we discuss how the processor can make cyber transactions more trustworthy. Can cryptography algorithms, and security protocols, be radically accelerated to provide needed confidentiality, data integrity, digital signatures and user authentication, in an automatic and painless way? In the area of service availability, we discuss whether the processor can provide defenses against misuse of computers by malicious third parties. Are there ways processor architecture can be enhanced to detect, prevent or mitigate potentially disastrous Distributed Denial of Service attacks? What are the processor and software vendors��� responsibilities in providing best-effort security features? What are the technical, policy and social challenges in digital rights management (DRM) with regard to built-in anti-piracy mechanisms? Many of these issues have legal, economic, social and ethical aspects, in addition to technological possibilities and limitations. We propose that it is time to consider how technology in general, and processor architecture in particular, can be designed to facilitate greater security and trust in cyberspace transactions and services.
{"title":"Challenges in the Design of Security-Aware Processors","authors":"R. Lee","doi":"10.1109/ASAP.2003.1212824","DOIUrl":"https://doi.org/10.1109/ASAP.2003.1212824","url":null,"abstract":"Summary form only given. Approaches to cyber security have focused on reactive measures, perimeter security and software implementations. In contrast, we propose a proactive approach to cyber security, where every component, hardware, software or networking, has secure or trustworthy operation as a primary design goal. Architecture for cyber security must be defined at many levels. At the foundational level, if we want core hardware and software to be more responsible for cyber security, what architectural features must be included? How do we translate business and personal security needs, in addition to military and national security needs, into scalable technology features? In this talk, we focus on processors as the engines of the Information Age upon which all software runs. What does it mean for a processor to be security-aware? We illustrate with a few examples. In the area of e-commerce and e-business, we discuss how the processor can make cyber transactions more trustworthy. Can cryptography algorithms, and security protocols, be radically accelerated to provide needed confidentiality, data integrity, digital signatures and user authentication, in an automatic and painless way? In the area of service availability, we discuss whether the processor can provide defenses against misuse of computers by malicious third parties. Are there ways processor architecture can be enhanced to detect, prevent or mitigate potentially disastrous Distributed Denial of Service attacks? What are the processor and software vendors��� responsibilities in providing best-effort security features? What are the technical, policy and social challenges in digital rights management (DRM) with regard to built-in anti-piracy mechanisms? Many of these issues have legal, economic, social and ethical aspects, in addition to technological possibilities and limitations. We propose that it is time to consider how technology in general, and processor architecture in particular, can be designed to facilitate greater security and trust in cyberspace transactions and services.","PeriodicalId":6642,"journal":{"name":"2015 IEEE 26th International Conference on Application-specific Systems, Architectures and Processors (ASAP)","volume":"37 1","pages":"2-"},"PeriodicalIF":0.0,"publicationDate":"2003-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80336415","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-24DOI: 10.1109/ASAP.2003.1212831
A. Turjan, B. Kienhuis
At the Leiden embedded research center, we are developing a compiler called Compaan that automatically translates signal processing applications written in Matlab into Kahn process networks (KPNs). In general, these signal processing applications are data-flow intensive, requiring large storage capacities, usually represented by matrices. An important issue in Compaan is the derivation of a memory management mechanism that allows for efficient interprocess communication. This mechanism has previously been published and is called the extended linearization model (ELM). The controller needed in the ELM is derived using the Ehrhart theory, leading to a computational intensive procedure. We present a new approach to derive the ELM controller, based on the notion of lexicographically maximal preimage. Using polytope manipulations and parametric integer linear programming techniques, we get less computational intensive and easier to be derived controller implementation for the ELM.
{"title":"Storage Management in Process Networks using the Lexicographically Maximal Preimage","authors":"A. Turjan, B. Kienhuis","doi":"10.1109/ASAP.2003.1212831","DOIUrl":"https://doi.org/10.1109/ASAP.2003.1212831","url":null,"abstract":"At the Leiden embedded research center, we are developing a compiler called Compaan that automatically translates signal processing applications written in Matlab into Kahn process networks (KPNs). In general, these signal processing applications are data-flow intensive, requiring large storage capacities, usually represented by matrices. An important issue in Compaan is the derivation of a memory management mechanism that allows for efficient interprocess communication. This mechanism has previously been published and is called the extended linearization model (ELM). The controller needed in the ELM is derived using the Ehrhart theory, leading to a computational intensive procedure. We present a new approach to derive the ELM controller, based on the notion of lexicographically maximal preimage. Using polytope manipulations and parametric integer linear programming techniques, we get less computational intensive and easier to be derived controller implementation for the ELM.","PeriodicalId":6642,"journal":{"name":"2015 IEEE 26th International Conference on Application-specific Systems, Architectures and Processors (ASAP)","volume":"23 1","pages":"75-85"},"PeriodicalIF":0.0,"publicationDate":"2003-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76170091","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-24DOI: 10.1109/ASAP.2003.1212862
Georgios Kornaros, T. Orphanoudakis, I. Papaefstathiou
In order to address the challenge of providing quality of service guarantees in today's network processing systems, the use of efficient scheduling algorithms is required. The efficiency of a scheduler is determined by several factors including its fairness, capability to operate at high speeds, as well as the resources required for its implementation. We present an architecture to support fair scheduling (gigabit FS) considering variable length packets (i. e. for packet forwarding/switching networks) over gigabit links. This high speed scheduler is designed to manage 32 K flows based on an algorithm that yields efficient implementation in hardware by avoiding the complexity of computing the system virtual time function that many packet fair queueing (PFQ) algorithms have proposed. Further, we demonstrate the critical factors in designing an effective scheduling engine at gigabit rates and we present several enhancements together with their associated cost.
{"title":"GFS: An Efficient Implementation of Fair Scheduling for Mult-Gigabit Packet Networks","authors":"Georgios Kornaros, T. Orphanoudakis, I. Papaefstathiou","doi":"10.1109/ASAP.2003.1212862","DOIUrl":"https://doi.org/10.1109/ASAP.2003.1212862","url":null,"abstract":"In order to address the challenge of providing quality of service guarantees in today's network processing systems, the use of efficient scheduling algorithms is required. The efficiency of a scheduler is determined by several factors including its fairness, capability to operate at high speeds, as well as the resources required for its implementation. We present an architecture to support fair scheduling (gigabit FS) considering variable length packets (i. e. for packet forwarding/switching networks) over gigabit links. This high speed scheduler is designed to manage 32 K flows based on an algorithm that yields efficient implementation in hardware by avoiding the complexity of computing the system virtual time function that many packet fair queueing (PFQ) algorithms have proposed. Further, we demonstrate the critical factors in designing an effective scheduling engine at gigabit rates and we present several enhancements together with their associated cost.","PeriodicalId":6642,"journal":{"name":"2015 IEEE 26th International Conference on Application-specific Systems, Architectures and Processors (ASAP)","volume":"16 1","pages":"389-399"},"PeriodicalIF":0.0,"publicationDate":"2003-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88268221","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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