Pub Date : 1992-01-07DOI: 10.1109/HICSS.1992.183173
S. Raina, Dhd Warren
The authors present a multiprocessor emulator designed to evaluate a scalable shared virtual memory architecture called the Data Diffusion Machine (DDM). The DDM is characterised by the lack of any fixed home location for data, with the virtual address being completely decoupled from the physical location of a datum. The authors describe the design of the emulator for the DDM and its transputer-based implementation. The emulator provides a flexible platform for evaluating the architecture and enables one to study the overall behaviour of the machine while running real, lace shared-memory applications. They present a profile of traffic observed at the controllers in the DDM hierarchy while running a variety of real shared-memory applications.<>
{"title":"Traffic patterns in a scalable multiprocessor through transputer emulation","authors":"S. Raina, Dhd Warren","doi":"10.1109/HICSS.1992.183173","DOIUrl":"https://doi.org/10.1109/HICSS.1992.183173","url":null,"abstract":"The authors present a multiprocessor emulator designed to evaluate a scalable shared virtual memory architecture called the Data Diffusion Machine (DDM). The DDM is characterised by the lack of any fixed home location for data, with the virtual address being completely decoupled from the physical location of a datum. The authors describe the design of the emulator for the DDM and its transputer-based implementation. The emulator provides a flexible platform for evaluating the architecture and enables one to study the overall behaviour of the machine while running real, lace shared-memory applications. They present a profile of traffic observed at the controllers in the DDM hierarchy while running a variety of real shared-memory applications.<<ETX>>","PeriodicalId":103288,"journal":{"name":"Proceedings of the Twenty-Fifth Hawaii International Conference on System Sciences","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123920896","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-01-07DOI: 10.1109/HICSS.1992.183288
D. Rover
Observing the activities of a complex parallel computer system is no small feat, and relating these observations to program behavior is even harder. This paper presents a general measurement approach that is applicable to a large class of scalable programs and machines, specifically data parallel programs executing on distributed memory computer systems. The combined instrumentation and visualization paradigm, called VISTA (which stands for Visualization and Instrumentation of Scalable mulTicomputer Applications), is based on the author's experiences of programming and monitoring applications running on an nCUBE 2 computer and a MasPar MP-1 computer. The key is that performance data are treated similarly to any distributed data in the context of the data parallel programming model. Because of the data-parallel mapping of the program onto the machine, one can view the performance as it relates to each processor, processor cluster or processor ensemble and as it relates to the data structures of the program. The author illustrates the utility of VISTA by way of an example.<>
{"title":"A performance visualization paradigm for data parallel computing","authors":"D. Rover","doi":"10.1109/HICSS.1992.183288","DOIUrl":"https://doi.org/10.1109/HICSS.1992.183288","url":null,"abstract":"Observing the activities of a complex parallel computer system is no small feat, and relating these observations to program behavior is even harder. This paper presents a general measurement approach that is applicable to a large class of scalable programs and machines, specifically data parallel programs executing on distributed memory computer systems. The combined instrumentation and visualization paradigm, called VISTA (which stands for Visualization and Instrumentation of Scalable mulTicomputer Applications), is based on the author's experiences of programming and monitoring applications running on an nCUBE 2 computer and a MasPar MP-1 computer. The key is that performance data are treated similarly to any distributed data in the context of the data parallel programming model. Because of the data-parallel mapping of the program onto the machine, one can view the performance as it relates to each processor, processor cluster or processor ensemble and as it relates to the data structures of the program. The author illustrates the utility of VISTA by way of an example.<<ETX>>","PeriodicalId":103288,"journal":{"name":"Proceedings of the Twenty-Fifth Hawaii International Conference on System Sciences","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122295945","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-01-07DOI: 10.1109/HICSS.1992.183275
P. Grogono, B. Cheung
Object-oriented methods allow programmers to construct software with a simple and uniform structure. Object-oriented programs should be simple to maintain and extend. Source code browsers are not sufficient for understanding object-oriented programs. The authors have combined a strongly-typed object-oriented language with an integrated, interactive development environment. For several reasons, they designed the compiler as an integral component of the environment. Coupling the compiler and the browser simplifies symbol table management in the compiler. Conversely, the same coupling ensures that information is semantically checked before the browser displays it. Also, programmers do not have to understand the class hierarchy because the compiler creates class views.<>
{"title":"A semantic browser for object oriented program development","authors":"P. Grogono, B. Cheung","doi":"10.1109/HICSS.1992.183275","DOIUrl":"https://doi.org/10.1109/HICSS.1992.183275","url":null,"abstract":"Object-oriented methods allow programmers to construct software with a simple and uniform structure. Object-oriented programs should be simple to maintain and extend. Source code browsers are not sufficient for understanding object-oriented programs. The authors have combined a strongly-typed object-oriented language with an integrated, interactive development environment. For several reasons, they designed the compiler as an integral component of the environment. Coupling the compiler and the browser simplifies symbol table management in the compiler. Conversely, the same coupling ensures that information is semantically checked before the browser displays it. Also, programmers do not have to understand the class hierarchy because the compiler creates class views.<<ETX>>","PeriodicalId":103288,"journal":{"name":"Proceedings of the Twenty-Fifth Hawaii International Conference on System Sciences","volume":"112 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127988073","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-01-07DOI: 10.1109/HICSS.1992.183279
N. Boudriga, A. Mili, R. Zalila
A specification is complete if it carries all the information required by the user, and minimal if it carries nothing but the information required by the user. The authors have designed a lifecycle of the requirements specification phase, whose purpose is to help achieve completeness and minimality by the proper use of redundancy. In their view of the lifecycle, the verification and validation group elicits information from the user and matches it against the generated specification to check completeness and minimality. In this paper, the authors give details of this lifecycle, and present an automated system that carries out the proofs of completeness and minimality using Prolog's inference capability.<>
{"title":"An automated tool for specification validation: design and preliminary implementation","authors":"N. Boudriga, A. Mili, R. Zalila","doi":"10.1109/HICSS.1992.183279","DOIUrl":"https://doi.org/10.1109/HICSS.1992.183279","url":null,"abstract":"A specification is complete if it carries all the information required by the user, and minimal if it carries nothing but the information required by the user. The authors have designed a lifecycle of the requirements specification phase, whose purpose is to help achieve completeness and minimality by the proper use of redundancy. In their view of the lifecycle, the verification and validation group elicits information from the user and matches it against the generated specification to check completeness and minimality. In this paper, the authors give details of this lifecycle, and present an automated system that carries out the proofs of completeness and minimality using Prolog's inference capability.<<ETX>>","PeriodicalId":103288,"journal":{"name":"Proceedings of the Twenty-Fifth Hawaii International Conference on System Sciences","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128043548","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-01-07DOI: 10.1109/HICSS.1992.183172
S. Chaumette
For efficiency, multiprocessor local memory machines work mostly on the message passing principle, and therefore are programmed using the framework of communicating sequential processes. This programming should be easy to do, and this ease obviously requires an adequate software environment. One such environment, ADAM, is the main topic of the paper. Especially important and time consuming in the development cycle of a distributed application is the debugging phase. Therefore among the tools provided by the ADAM environment, those dedicated to debugging have been emphasized. The most interesting are: a centralized simulator-debugger at the level of the language; a tool based upon traces that enables to see the communication that took place during an execution. The most original part of this work consists of debugging mechanisms dedicated to communication.<>
{"title":"A software environment for programming distributed memory machines","authors":"S. Chaumette","doi":"10.1109/HICSS.1992.183172","DOIUrl":"https://doi.org/10.1109/HICSS.1992.183172","url":null,"abstract":"For efficiency, multiprocessor local memory machines work mostly on the message passing principle, and therefore are programmed using the framework of communicating sequential processes. This programming should be easy to do, and this ease obviously requires an adequate software environment. One such environment, ADAM, is the main topic of the paper. Especially important and time consuming in the development cycle of a distributed application is the debugging phase. Therefore among the tools provided by the ADAM environment, those dedicated to debugging have been emphasized. The most interesting are: a centralized simulator-debugger at the level of the language; a tool based upon traces that enables to see the communication that took place during an execution. The most original part of this work consists of debugging mechanisms dedicated to communication.<<ETX>>","PeriodicalId":103288,"journal":{"name":"Proceedings of the Twenty-Fifth Hawaii International Conference on System Sciences","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128346580","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-01-07DOI: 10.1109/HICSS.1992.183216
T. Dix, C. Ho-Stuart
Computationally, constraint checking for circular restriction site maps is considerably more difficult than for linear maps. The authors consider complete single and double digestions of plasmids, circular DNA molecules. To allow for experimental error in fragment measurements, a range is specified for each fragment length. The authors find exactly those solutions that satisfy the discrete constraints of the date. For sites s/sub i/ and s/sub j/ they consider linear inequalities in either of the forms L/sub ij/>
{"title":"Constraint checking for circular restriction site mapping (DNA)","authors":"T. Dix, C. Ho-Stuart","doi":"10.1109/HICSS.1992.183216","DOIUrl":"https://doi.org/10.1109/HICSS.1992.183216","url":null,"abstract":"Computationally, constraint checking for circular restriction site maps is considerably more difficult than for linear maps. The authors consider complete single and double digestions of plasmids, circular DNA molecules. To allow for experimental error in fragment measurements, a range is specified for each fragment length. The authors find exactly those solutions that satisfy the discrete constraints of the date. For sites s/sub i/ and s/sub j/ they consider linear inequalities in either of the forms L/sub ij/<or=s/sub j/-s/sub i/<or=H/sub ij/ or L/sub ij/<or=c-(s/sub j/-s/sub i/)<or=H/sub ij/ where s/sub i/<s/sub j/, the measured fragment is in the range (L/sub ij/,H/sub ij/) and c is the length of the map. For consistent inequalities, minimum ranges for fragments are found. Otherwise inconsistent inequalities are detected.<<ETX>>","PeriodicalId":103288,"journal":{"name":"Proceedings of the Twenty-Fifth Hawaii International Conference on System Sciences","volume":"i 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129672808","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-01-07DOI: 10.1109/HICSS.1992.183289
G. Sabot
Describes the techniques that are used in the CM Fortran 1.0 compiler to map the fine-grained array parallelism of Fortran 90 onto the CM-2 architecture. The compiler views the parallel hardware at a much lower level of detail than did previous CM-2 compilers, which had targeted a function library named Paris. In the slicewise machine model used by CM Fortran 1.0, the FPUs, their registers, and the memory hierarchy are directly exposed to the compiler. Thus, the CM-2 target machine is not 64K simple bit-serial processors. Rather, the target is a machine containing 2K PEs (processing elements), where each PE is both superpipelined and superscalar. The compiler uses data distribution to spread the problem out among the 2K processors. A new compiler phase is used to separate the code that runs on the two types of processors in the CM: the parallel PEs, which execute a new RISC-like instruction set called PEAC, and the scalar front-end processor, which executes SPARC or VAX assembler code. The pipelines in PEs are filled by using conventional vector processing techniques along with a new, RISC-like vector instruction set. An innovative scheduler overlaps the execution of a number of RISC operations. This new compiler has greatly increased the performance of Fortran codes on the CM-2 on many important computation kernels, such as climate modeling, seismic processing, and hydrodynamics simulations.<>
{"title":"Optimized CM Fortran compiler for the Connection Machine computer","authors":"G. Sabot","doi":"10.1109/HICSS.1992.183289","DOIUrl":"https://doi.org/10.1109/HICSS.1992.183289","url":null,"abstract":"Describes the techniques that are used in the CM Fortran 1.0 compiler to map the fine-grained array parallelism of Fortran 90 onto the CM-2 architecture. The compiler views the parallel hardware at a much lower level of detail than did previous CM-2 compilers, which had targeted a function library named Paris. In the slicewise machine model used by CM Fortran 1.0, the FPUs, their registers, and the memory hierarchy are directly exposed to the compiler. Thus, the CM-2 target machine is not 64K simple bit-serial processors. Rather, the target is a machine containing 2K PEs (processing elements), where each PE is both superpipelined and superscalar. The compiler uses data distribution to spread the problem out among the 2K processors. A new compiler phase is used to separate the code that runs on the two types of processors in the CM: the parallel PEs, which execute a new RISC-like instruction set called PEAC, and the scalar front-end processor, which executes SPARC or VAX assembler code. The pipelines in PEs are filled by using conventional vector processing techniques along with a new, RISC-like vector instruction set. An innovative scheduler overlaps the execution of a number of RISC operations. This new compiler has greatly increased the performance of Fortran codes on the CM-2 on many important computation kernels, such as climate modeling, seismic processing, and hydrodynamics simulations.<<ETX>>","PeriodicalId":103288,"journal":{"name":"Proceedings of the Twenty-Fifth Hawaii International Conference on System Sciences","volume":"ii 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129682350","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-01-07DOI: 10.1109/HICSS.1992.183301
R. Robson
A prevalent problem in code reuse is the difficult if in locating the code to be reused. Rapid prototyping depends heavily on being able to locate software components to assemble into new applications. The paper presents DYHARD, a specification language that allows a programmer to specify how hypertext links are to be maintained between reusable software components in a library. The language is object-oriented and exploits the class structure to help the user model his data. The hypertext links are used to form multiple logical threads interconnecting the software components to let the programmer to locate and reuse code more easily.<>
{"title":"Using hypertext to locate reusable objects","authors":"R. Robson","doi":"10.1109/HICSS.1992.183301","DOIUrl":"https://doi.org/10.1109/HICSS.1992.183301","url":null,"abstract":"A prevalent problem in code reuse is the difficult if in locating the code to be reused. Rapid prototyping depends heavily on being able to locate software components to assemble into new applications. The paper presents DYHARD, a specification language that allows a programmer to specify how hypertext links are to be maintained between reusable software components in a library. The language is object-oriented and exploits the class structure to help the user model his data. The hypertext links are used to form multiple logical threads interconnecting the software components to let the programmer to locate and reuse code more easily.<<ETX>>","PeriodicalId":103288,"journal":{"name":"Proceedings of the Twenty-Fifth Hawaii International Conference on System Sciences","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130620299","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-01-07DOI: 10.1109/HICSS.1992.183285
John L. Gustafson
In measuring the performance of parallel computers, the usual method is to choose a problem and test the execution time as the processor count is varied. This model underlies definitions of 'speedup,' 'efficiency,' and arguments against parallel processing such as Ware's (1972) formulation of Amdahl's law (1967). Fixed time models use problem size as the figure of merit. Analysis and experiments based on fixed time instead of fixed size have yielded surprising consequences: the fixed time method does not reward slower processors with higher speedup; it predicts a new limit to speedup, which is more optimistic than Amdahl's; it shows an efficiency which is independent of processor speed and ensemble size; it sometimes gives non-spurious superlinear speedup; it provides a practical means (the SLALOM benchmark) of comparing computers of widely varying speeds without distortion.<>
{"title":"The consequences of fixed time performance measurement","authors":"John L. Gustafson","doi":"10.1109/HICSS.1992.183285","DOIUrl":"https://doi.org/10.1109/HICSS.1992.183285","url":null,"abstract":"In measuring the performance of parallel computers, the usual method is to choose a problem and test the execution time as the processor count is varied. This model underlies definitions of 'speedup,' 'efficiency,' and arguments against parallel processing such as Ware's (1972) formulation of Amdahl's law (1967). Fixed time models use problem size as the figure of merit. Analysis and experiments based on fixed time instead of fixed size have yielded surprising consequences: the fixed time method does not reward slower processors with higher speedup; it predicts a new limit to speedup, which is more optimistic than Amdahl's; it shows an efficiency which is independent of processor speed and ensemble size; it sometimes gives non-spurious superlinear speedup; it provides a practical means (the SLALOM benchmark) of comparing computers of widely varying speeds without distortion.<<ETX>>","PeriodicalId":103288,"journal":{"name":"Proceedings of the Twenty-Fifth Hawaii International Conference on System Sciences","volume":"134 21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127775401","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-01-07DOI: 10.1109/HICSS.1992.183333
K. Kato, A. Ohori
One important concept established through research of persistent programming languages is orthogonal persistence. The techniques so far proposed for this concept are, however, limited to single language systems. This paper proposes a systematic method to achieve orthogonal persistence in a multilanguage system by combining a technique for higher-order remote procedure calls and a mechanism of orthogonal persistence in a single language system. The proposed method can be used to develop a multilanguage persistent type system, where any data of any types including higher-order functions can persist and can later be used from a different language. The necessary data conversion between languages is transparent to the user. In addition to an effective algorithm to implement a multilanguage persistent system, the authors system has rigorous type discipline and formal properties that enable them to show that multilanguage sharing preserves the intended semantics of persistent data.<>
{"title":"An approach to multilanguage persistent type system","authors":"K. Kato, A. Ohori","doi":"10.1109/HICSS.1992.183333","DOIUrl":"https://doi.org/10.1109/HICSS.1992.183333","url":null,"abstract":"One important concept established through research of persistent programming languages is orthogonal persistence. The techniques so far proposed for this concept are, however, limited to single language systems. This paper proposes a systematic method to achieve orthogonal persistence in a multilanguage system by combining a technique for higher-order remote procedure calls and a mechanism of orthogonal persistence in a single language system. The proposed method can be used to develop a multilanguage persistent type system, where any data of any types including higher-order functions can persist and can later be used from a different language. The necessary data conversion between languages is transparent to the user. In addition to an effective algorithm to implement a multilanguage persistent system, the authors system has rigorous type discipline and formal properties that enable them to show that multilanguage sharing preserves the intended semantics of persistent data.<<ETX>>","PeriodicalId":103288,"journal":{"name":"Proceedings of the Twenty-Fifth Hawaii International Conference on System Sciences","volume":"130 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124241023","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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