Pub Date : 1993-04-05DOI: 10.1109/FPGA.1993.279481
X. Ling, H. Amano
Virtual hardware is a technique to realize a large digital circuit with a small real hardware by using an extended Field Programmable Gate Array (FPGA) technology. Several configuration RAM modules are provided inside the FPGA chip, and the configuration of the gate array can be rapidly changed by replacing the active module. Data for configuration are transferred from an off-chip backup RAM to an unused configuration RAM module. A novel computation mechanism called the WASMII, which executes a target data flow graph directly, is proposed on the basis of the virtual hardware. A WASMII chip consists of the FPGA for virtual hardware and the additional mechanism to replace configuration RAM modules in the data driven manner. Configuration data are preloaded by the order which is assigned in advance with a static scheduling preprocessor. By connecting a number of WASMII chips, a highly parallel system can be easily constructed.<>
{"title":"WASMII: a data driven computer on a virtual hardware","authors":"X. Ling, H. Amano","doi":"10.1109/FPGA.1993.279481","DOIUrl":"https://doi.org/10.1109/FPGA.1993.279481","url":null,"abstract":"Virtual hardware is a technique to realize a large digital circuit with a small real hardware by using an extended Field Programmable Gate Array (FPGA) technology. Several configuration RAM modules are provided inside the FPGA chip, and the configuration of the gate array can be rapidly changed by replacing the active module. Data for configuration are transferred from an off-chip backup RAM to an unused configuration RAM module. A novel computation mechanism called the WASMII, which executes a target data flow graph directly, is proposed on the basis of the virtual hardware. A WASMII chip consists of the FPGA for virtual hardware and the additional mechanism to replace configuration RAM modules in the data driven manner. Configuration data are preloaded by the order which is assigned in advance with a static scheduling preprocessor. By connecting a number of WASMII chips, a highly parallel system can be easily constructed.<<ETX>>","PeriodicalId":104383,"journal":{"name":"[1993] Proceedings IEEE Workshop on FPGAs for Custom Computing Machines","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-04-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120911204","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-04-05DOI: 10.1109/FPGA.1993.279482
George Milne, Paul Cockshott, George McCaskill, P. Barrie, HardLab
Highly concurrent systems occur frequently in the physical world. This paper focuses on a class of systems characterised as being highly concurrent and which are composed out of many simple parts which interact with other parts in their locality. It discusses how to describe these systems and introduces a cellular automata type of architecture which is used to simulate these systems directly in hardware, with physical concurrency being realised by true hardware concurrency. The architecture of the SPACE machine (Scalable Parallel Architecture for Concurrency Experiments), which is constructed from reconfigurable FPGA logic, is introduced and it is demonstrated how to simulate road traffic systems using it.<>
高度并发的系统在物理世界中经常出现。本文主要研究一类具有高度并发性的系统，这些系统由许多简单的部分组成，这些部分与局部的其他部分相互作用。它讨论了如何描述这些系统，并介绍了一种元胞自动机类型的体系结构，该体系结构用于直接在硬件中模拟这些系统，通过真正的硬件并发实现物理并发。介绍了由可重构FPGA逻辑构成的SPACE机器(Scalable Parallel architecture for Concurrency Experiments)的体系结构，并演示了如何使用它来模拟道路交通系统。
{"title":"Realising massively concurrent systems on the SPACE machine","authors":"George Milne, Paul Cockshott, George McCaskill, P. Barrie, HardLab","doi":"10.1109/FPGA.1993.279482","DOIUrl":"https://doi.org/10.1109/FPGA.1993.279482","url":null,"abstract":"Highly concurrent systems occur frequently in the physical world. This paper focuses on a class of systems characterised as being highly concurrent and which are composed out of many simple parts which interact with other parts in their locality. It discusses how to describe these systems and introduces a cellular automata type of architecture which is used to simulate these systems directly in hardware, with physical concurrency being realised by true hardware concurrency. The architecture of the SPACE machine (Scalable Parallel Architecture for Concurrency Experiments), which is constructed from reconfigurable FPGA logic, is introduced and it is demonstrated how to simulate road traffic systems using it.<<ETX>>","PeriodicalId":104383,"journal":{"name":"[1993] Proceedings IEEE Workshop on FPGAs for Custom Computing Machines","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-04-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125187361","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-04-05DOI: 10.1109/FPGA.1993.279472
H. Herpel, N. Wehn, M. Gasteier, Manfred Glesner
The authors present a custom computer together with a software environment for rapid implementation of algorithms on reprogrammable hardware. The custom computer is based on FPGA boards embedded in a programmable interconnection network. The transformation of an algorithmic system specification into a configuration file for the FPGAs is supported through a set of high-level and structural synthesis tools. Hardware and software are tuned, but not limited to the application domain of real-time control. The presented approach is not a push-button approach, it takes advantage of the experience of the designer at several stages to reach a near optimal solution.<>
{"title":"A reconfigurable computer for embedded control applications","authors":"H. Herpel, N. Wehn, M. Gasteier, Manfred Glesner","doi":"10.1109/FPGA.1993.279472","DOIUrl":"https://doi.org/10.1109/FPGA.1993.279472","url":null,"abstract":"The authors present a custom computer together with a software environment for rapid implementation of algorithms on reprogrammable hardware. The custom computer is based on FPGA boards embedded in a programmable interconnection network. The transformation of an algorithmic system specification into a configuration file for the FPGAs is supported through a set of high-level and structural synthesis tools. Hardware and software are tuned, but not limited to the application domain of real-time control. The presented approach is not a push-button approach, it takes advantage of the experience of the designer at several stages to reach a near optimal solution.<<ETX>>","PeriodicalId":104383,"journal":{"name":"[1993] Proceedings IEEE Workshop on FPGAs for Custom Computing Machines","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-04-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128827201","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-04-05DOI: 10.1109/FPGA.1993.279466
V. Daniel, Pryor, Thistle, Nabeel Shirazi
The paper proposes a flexible, reprogrammable hardware solution to the acceleration of text-based keyword search problems. In these problems, a stream of input text is checked against a known list of keywords (a dictionary) for occurrences of those keywords in the text. The authors' solution employs an attached processor called Splash 2, which exploits the speed and reconfigurability of field programmable gate array technology. The Splash 2 system was designed and built at the SRC for a wide variety of applications. A Splash 2 system is comprised of an interface board to a Sun Sparc-2 host and up to 16 Splash boards, each of which contains 16 Xilinx 4010 FPGAs interconnected in a linear array and also through a 16-way full crossbar switch. Each Xilinx chip is coupled with a 4 Mbit static RAM through a dedicated interface. The text searching program implemented on a one-board Splash 2 system is capable of processing text at an estimated rate of 50 million characters per second.<>
{"title":"Text searching on Splash 2","authors":"V. Daniel, Pryor, Thistle, Nabeel Shirazi","doi":"10.1109/FPGA.1993.279466","DOIUrl":"https://doi.org/10.1109/FPGA.1993.279466","url":null,"abstract":"The paper proposes a flexible, reprogrammable hardware solution to the acceleration of text-based keyword search problems. In these problems, a stream of input text is checked against a known list of keywords (a dictionary) for occurrences of those keywords in the text. The authors' solution employs an attached processor called Splash 2, which exploits the speed and reconfigurability of field programmable gate array technology. The Splash 2 system was designed and built at the SRC for a wide variety of applications. A Splash 2 system is comprised of an interface board to a Sun Sparc-2 host and up to 16 Splash boards, each of which contains 16 Xilinx 4010 FPGAs interconnected in a linear array and also through a 16-way full crossbar switch. Each Xilinx chip is coupled with a 4 Mbit static RAM through a dedicated interface. The text searching program implemented on a one-board Splash 2 system is capable of processing text at an estimated rate of 50 million characters per second.<<ETX>>","PeriodicalId":104383,"journal":{"name":"[1993] Proceedings IEEE Workshop on FPGAs for Custom Computing Machines","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-04-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132982862","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-04-05DOI: 10.1109/FPGA.1993.279464
Dzung T. Hoang
The author describes two systolic arrays for computing the edit distance between two genetic sequences using a well-known dynamic programming algorithm. The systolic arrays have been implemented for the Splash 2 programmable logic array and are intended to be used for database searching. Simulations indicate that the faster Splash 2 implementation can search a database at a rate of 12 million characters per second, several orders of magnitude faster than implementations of the dynamic programming algorithm on conventional computers.<>
{"title":"Searching genetic databases on Splash 2","authors":"Dzung T. Hoang","doi":"10.1109/FPGA.1993.279464","DOIUrl":"https://doi.org/10.1109/FPGA.1993.279464","url":null,"abstract":"The author describes two systolic arrays for computing the edit distance between two genetic sequences using a well-known dynamic programming algorithm. The systolic arrays have been implemented for the Splash 2 programmable logic array and are intended to be used for database searching. Simulations indicate that the faster Splash 2 implementation can search a database at a rate of 12 million characters per second, several orders of magnitude faster than implementations of the dynamic programming algorithm on conventional computers.<<ETX>>","PeriodicalId":104383,"journal":{"name":"[1993] Proceedings IEEE Workshop on FPGAs for Custom Computing Machines","volume":"32 5","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-04-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131956731","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-04-05DOI: 10.1109/FPGA.1993.279479
P. French, R. Taylor
Recent developments in the design and fabrication of field programmable logic devices (FPGAs) may well change the way in which one designs and fabricates conventional microprocessors. The use of uncommitted logic whose function may be modified at run time makes the prospect of dynamic application specific integrated circuits closer to reality than ever before. Much of the work to date on reconfigurable logic has focussed on its application in co-processor and 'glue' roles. This paper discusses how complete processors might be fabricated with a minimum of 'fixed' or static logic. It is shown that in order to exploit FPGAs, a processor that is radically different from conventional architectures is required. The paper concludes by considering what evolutions of current logic families would favour this type of application.<>
{"title":"A self-reconfigurable processor","authors":"P. French, R. Taylor","doi":"10.1109/FPGA.1993.279479","DOIUrl":"https://doi.org/10.1109/FPGA.1993.279479","url":null,"abstract":"Recent developments in the design and fabrication of field programmable logic devices (FPGAs) may well change the way in which one designs and fabricates conventional microprocessors. The use of uncommitted logic whose function may be modified at run time makes the prospect of dynamic application specific integrated circuits closer to reality than ever before. Much of the work to date on reconfigurable logic has focussed on its application in co-processor and 'glue' roles. This paper discusses how complete processors might be fabricated with a minimum of 'fixed' or static logic. It is shown that in order to exploit FPGAs, a processor that is radically different from conventional architectures is required. The paper concludes by considering what evolutions of current logic families would favour this type of application.<<ETX>>","PeriodicalId":104383,"journal":{"name":"[1993] Proceedings IEEE Workshop on FPGAs for Custom Computing Machines","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-04-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122512020","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-04-05DOI: 10.1109/FPGA.1993.279476
S. Guccione, Mario J. Gonzalez
Recently, several machines have been built using field programmable gate array (FPGA) technology. These reconfigurable architectures have demonstrated very high performance for a variety of problems. The configuration of these machines typically rely on some form of hardware specification. The authors demonstrate that a more traditional software approach may be used. A vector based data-parallel model and its mapping to a reconfigurable architecture are introduced. Included in the model are parallel prefix or scan operators. The language supporting this model is a subset of the C programming language.<>
{"title":"A data-parallel programming model for reconfigurable architectures","authors":"S. Guccione, Mario J. Gonzalez","doi":"10.1109/FPGA.1993.279476","DOIUrl":"https://doi.org/10.1109/FPGA.1993.279476","url":null,"abstract":"Recently, several machines have been built using field programmable gate array (FPGA) technology. These reconfigurable architectures have demonstrated very high performance for a variety of problems. The configuration of these machines typically rely on some form of hardware specification. The authors demonstrate that a more traditional software approach may be used. A vector based data-parallel model and its mapping to a reconfigurable architecture are introduced. Included in the model are parallel prefix or scan operators. The language supporting this model is a subset of the C programming language.<<ETX>>","PeriodicalId":104383,"journal":{"name":"[1993] Proceedings IEEE Workshop on FPGAs for Custom Computing Machines","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-04-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128489243","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-04-05DOI: 10.1109/FPGA.1993.279465
M. E. Louie, M. Ercegovac
Creating efficient arithmetic processors requires a pairing of high speed arithmetic algorithms with optimal mapping strategies for a given technology. The authors propose bit reduction as key to an efficient pairing process for lookup table based field programmable gate arrays (FPGAs). Bit reduction simplifies the functions defining the original algorithm, thus permitting a mapping to fewer blocks and reducing the overall throughput delay. A mapping of a digit-recurrence square root algorithm to the Xilinx XC4010 FPGA illustrates the bit reduction process.<>
{"title":"A digit-recurrence square root implementation for field programmable gate arrays","authors":"M. E. Louie, M. Ercegovac","doi":"10.1109/FPGA.1993.279465","DOIUrl":"https://doi.org/10.1109/FPGA.1993.279465","url":null,"abstract":"Creating efficient arithmetic processors requires a pairing of high speed arithmetic algorithms with optimal mapping strategies for a given technology. The authors propose bit reduction as key to an efficient pairing process for lookup table based field programmable gate arrays (FPGAs). Bit reduction simplifies the functions defining the original algorithm, thus permitting a mapping to fewer blocks and reducing the overall throughput delay. A mapping of a digit-recurrence square root algorithm to the Xilinx XC4010 FPGA illustrates the bit reduction process.<<ETX>>","PeriodicalId":104383,"journal":{"name":"[1993] Proceedings IEEE Workshop on FPGAs for Custom Computing Machines","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-04-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132055085","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-04-05DOI: 10.1109/FPGA.1993.279473
S. Monaghan, C. Cowen
A PC-AT hosted DSP processor architecture implemented in SRAM-based field programmable gate arrays (FPGA) and static memories is described. Despite its simplicity, the processor circuits can be reconfigured under software control to tackle a class of multi-bit 'pixel' processing problems of current interest in the statistical physics of disordered materials, thereby offering some of the problem flexibility of a general purpose processor and the performance of custom hardware. The flexibility offered by the FPGA implementation is discussed in detail as is a particular application of the processor (to disordered superconductors). The performance of the processor is shown to compare well with similarly costing commercial DSP hardware. The low cost of the processor means it can be replicated to obtain dedicated supercomputer performance.<>
{"title":"Reconfigurable multi-bit processor for DSP applications in statistical physics","authors":"S. Monaghan, C. Cowen","doi":"10.1109/FPGA.1993.279473","DOIUrl":"https://doi.org/10.1109/FPGA.1993.279473","url":null,"abstract":"A PC-AT hosted DSP processor architecture implemented in SRAM-based field programmable gate arrays (FPGA) and static memories is described. Despite its simplicity, the processor circuits can be reconfigured under software control to tackle a class of multi-bit 'pixel' processing problems of current interest in the statistical physics of disordered materials, thereby offering some of the problem flexibility of a general purpose processor and the performance of custom hardware. The flexibility offered by the FPGA implementation is discussed in detail as is a particular application of the processor (to disordered superconductors). The performance of the processor is shown to compare well with similarly costing commercial DSP hardware. The low cost of the processor means it can be replicated to obtain dedicated supercomputer performance.<<ETX>>","PeriodicalId":104383,"journal":{"name":"[1993] Proceedings IEEE Workshop on FPGAs for Custom Computing Machines","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-04-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132092487","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-04-05DOI: 10.1109/FPGA.1993.279462
M. V. Daalen, P. Jeavons, J. Shawe-Taylor
The authors present an expandable digital architecture that provides an efficient real time implementation platform for large neural networks. The architecture makes heavy use of the techniques of bit serial stochastic computing to carry out the large number of required parallel synaptic calculations. In this design all real valued quantities are encoded on to stochastic bit streams in which the '1' density is proportional to the given quantity. The actual digital circuitry is simple and highly regular thus allowing very efficient space usage of fine grained FPGAs. Another feature of the design is that the large number of weights required by a neural network are generated by circuitry tailored to each of their specific values, thus saving valuable cells. Whenever one of these values is required to change, the appropriate circuitry must be dynamically reconfigured. This may always be achieved in a fixed and minimum number of cells for a given bit stream resolution.<>
{"title":"A stochastic neural architecture that exploits dynamically reconfigurable FPGAs","authors":"M. V. Daalen, P. Jeavons, J. Shawe-Taylor","doi":"10.1109/FPGA.1993.279462","DOIUrl":"https://doi.org/10.1109/FPGA.1993.279462","url":null,"abstract":"The authors present an expandable digital architecture that provides an efficient real time implementation platform for large neural networks. The architecture makes heavy use of the techniques of bit serial stochastic computing to carry out the large number of required parallel synaptic calculations. In this design all real valued quantities are encoded on to stochastic bit streams in which the '1' density is proportional to the given quantity. The actual digital circuitry is simple and highly regular thus allowing very efficient space usage of fine grained FPGAs. Another feature of the design is that the large number of weights required by a neural network are generated by circuitry tailored to each of their specific values, thus saving valuable cells. Whenever one of these values is required to change, the appropriate circuitry must be dynamically reconfigured. This may always be achieved in a fixed and minimum number of cells for a given bit stream resolution.<<ETX>>","PeriodicalId":104383,"journal":{"name":"[1993] Proceedings IEEE Workshop on FPGAs for Custom Computing Machines","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-04-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132992818","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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