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2006 14th IEEE International Conference on Advanced Thermal Processing of Semiconductors最新文献

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Flash Lamp Annealing Latest Technology for 45nm device and Future devices 45纳米器件及未来器件的闪光灯退火最新技术
H. Kiyama
FLA (flash lamp annealing) is used in 65nm generation devices manufacturing. For next 45nm and future generation devices, we have picked up 3 key subjects related to milli-second annealing: process controllability, S/D (source drain) activation, silicidation. No need to say, process controllability is very important for device manufacturing. And process requirement for S/D activation and silicidation controllability is becoming more and more severe. Under evaluation of these subjects, it became clear that FLA technology is still a hopeful candidate for 45nm device and future
FLA(闪光灯退火)用于65nm代器件的制造。对于下一代45nm和下一代器件,我们已经选择了与毫秒退火相关的3个关键主题:过程可控性,S/D(源漏)激活,硅化。不用说,过程可控性对于器件制造是非常重要的。对S/D活化和硅化可控性的工艺要求也越来越高。在这些主题的评估下,FLA技术仍然是45纳米器件和未来的有希望的候选技术
{"title":"Flash Lamp Annealing Latest Technology for 45nm device and Future devices","authors":"H. Kiyama","doi":"10.1109/RTP.2006.367983","DOIUrl":"https://doi.org/10.1109/RTP.2006.367983","url":null,"abstract":"FLA (flash lamp annealing) is used in 65nm generation devices manufacturing. For next 45nm and future generation devices, we have picked up 3 key subjects related to milli-second annealing: process controllability, S/D (source drain) activation, silicidation. No need to say, process controllability is very important for device manufacturing. And process requirement for S/D activation and silicidation controllability is becoming more and more severe. Under evaluation of these subjects, it became clear that FLA technology is still a hopeful candidate for 45nm device and future","PeriodicalId":114586,"journal":{"name":"2006 14th IEEE International Conference on Advanced Thermal Processing of Semiconductors","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116632814","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Optimization of annealing for ClusterBoron® and ClusterCarbon PMOS SDE ClusterBoron®和ClusterCarbon PMOS SDE的退火优化
K. Sekar, W. Krull, K. Verheyden, K. Funk
High dopant activation and low implant damage are crucial in realizing the formation of a low resistivity ultra shallow junction (USJ). Future annealing process requires diffusion less activation and has ultimately define the junction depth. Conventional boron implant at ultra-low energies perform poorly in throughput and in energy contamination. Molecular species (B18H22) can provide implants with no energy contamination and low beam divergence along with self-amorphization. Implantation of ClusterBoron in combination with ClusterCarbon can provide junction depths in the 15-20 nm regime and achieve a higher level of dopant activation with conventional spike anneal. We used various ClusterBoron and ClusterCarbon energies and doses along with various anneal techniques to arrive at an optimum resistivity and junction depth for PMOS SDE applications. We carried out various analytical measurements like SIMS, sheet-resistance to understand the self-amorphization, enhanced dopant activation and the damage level effect of the dopants after the anneals. The results are discussed in detail in the paper
高掺杂激活和低植入损伤是实现低电阻率超浅结形成的关键。未来的退火工艺需要较少活化的扩散,并最终确定结深度。传统的超低能量硼植入在通量和能量污染方面表现不佳。分子物种(B18H22)可以提供无能量污染、低光束发散和自非晶化的植入物。将ClusterBoron与ClusterCarbon结合注入,可以提供15-20 nm的结深,并通过传统的尖峰退火实现更高水平的掺杂激活。我们使用了不同的ClusterBoron和ClusterCarbon能量和剂量,以及各种退火技术,以达到PMOS SDE应用的最佳电阻率和结深。我们进行了SIMS、薄片电阻等多种分析测量,以了解掺杂剂在退火后的自非晶化、增强激活和损伤水平效应。本文对所得结果进行了详细的讨论
{"title":"Optimization of annealing for ClusterBoron® and ClusterCarbon PMOS SDE","authors":"K. Sekar, W. Krull, K. Verheyden, K. Funk","doi":"10.1109/RTP.2006.368008","DOIUrl":"https://doi.org/10.1109/RTP.2006.368008","url":null,"abstract":"High dopant activation and low implant damage are crucial in realizing the formation of a low resistivity ultra shallow junction (USJ). Future annealing process requires diffusion less activation and has ultimately define the junction depth. Conventional boron implant at ultra-low energies perform poorly in throughput and in energy contamination. Molecular species (B18H22) can provide implants with no energy contamination and low beam divergence along with self-amorphization. Implantation of ClusterBoron in combination with ClusterCarbon can provide junction depths in the 15-20 nm regime and achieve a higher level of dopant activation with conventional spike anneal. We used various ClusterBoron and ClusterCarbon energies and doses along with various anneal techniques to arrive at an optimum resistivity and junction depth for PMOS SDE applications. We carried out various analytical measurements like SIMS, sheet-resistance to understand the self-amorphization, enhanced dopant activation and the damage level effect of the dopants after the anneals. The results are discussed in detail in the paper","PeriodicalId":114586,"journal":{"name":"2006 14th IEEE International Conference on Advanced Thermal Processing of Semiconductors","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121338651","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Micro-Scale Sheet Resistance Measurements on Ultra Shallow Junctions 超浅结的微尺度薄片电阻测量
C. L. Petersen, R. Lin, D. H. Petersen, P. Nielsen
The paper reports a new method for measuring sheet resistance on implanted wafers by using micro-fabricated four-point probes with a tip-to-tip spacing of a few microns. These microscopic probes have a contact force five orders of magnitude smaller than conventional probes, and can perform local non-destructive ultra shallow junction (USJ) sheet resistance measurements on both blanket and patterned wafers. The authors demonstrate this new technique on laser annealed wafers, measuring micro-scale sheet resistance variations on wafers that appear homogeneous when mapped with conventional four-point probes. The microscopic four-point probes detect stitching effects caused by laser spot overlap/misalignment during the annealing process. The findings indicate that such local sheet resistance in-homogeneities average out in conventional four-point measurements, and that new metrology is therefore needed to fully characterize USJ wafers activated by laser anneal and other diffusion-less methods
本文报道了一种利用尖端间距为几微米的微制四点探针测量植入晶圆片表面电阻的新方法。这些微型探针的接触力比传统探针小5个数量级,并且可以在覆盖层和图案晶圆片上进行局部非破坏性超浅结(USJ)片电阻测量。作者在激光退火晶圆上展示了这种新技术,测量了用传统四点探针在晶圆上显示均匀的微尺度薄片电阻变化。显微四点探针检测退火过程中激光光斑重叠/错位引起的拼接效应。研究结果表明,在传统的四点测量中,这种局部薄片电阻均匀性平均,因此需要新的测量方法来充分表征激光退火和其他无扩散方法激活的USJ晶圆
{"title":"Micro-Scale Sheet Resistance Measurements on Ultra Shallow Junctions","authors":"C. L. Petersen, R. Lin, D. H. Petersen, P. Nielsen","doi":"10.1109/RTP.2006.367996","DOIUrl":"https://doi.org/10.1109/RTP.2006.367996","url":null,"abstract":"The paper reports a new method for measuring sheet resistance on implanted wafers by using micro-fabricated four-point probes with a tip-to-tip spacing of a few microns. These microscopic probes have a contact force five orders of magnitude smaller than conventional probes, and can perform local non-destructive ultra shallow junction (USJ) sheet resistance measurements on both blanket and patterned wafers. The authors demonstrate this new technique on laser annealed wafers, measuring micro-scale sheet resistance variations on wafers that appear homogeneous when mapped with conventional four-point probes. The microscopic four-point probes detect stitching effects caused by laser spot overlap/misalignment during the annealing process. The findings indicate that such local sheet resistance in-homogeneities average out in conventional four-point measurements, and that new metrology is therefore needed to fully characterize USJ wafers activated by laser anneal and other diffusion-less methods","PeriodicalId":114586,"journal":{"name":"2006 14th IEEE International Conference on Advanced Thermal Processing of Semiconductors","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114446974","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Process Integration Issues with Spike, Flash and Laser Anneal Implementation for 90 and 65 NM Technologies 90 NM和65 NM技术的脉冲、闪蒸和激光退火工艺集成问题
T. Feudel, M. Horstmann, L. Herrmann, M. Herden, M. Gerhardt, D. Greenlaw, P. Fisher, J. Kluth
With the need to reduce vertical and lateral device dimensions, submelt laser and flash anneal either with or without prior spike rapid thermal anneal (sRTA) has recently attracted attention. It combines improved active area activation with reduced gate poly depletion for a process that is essentially free of additional diffusion. This paper will focus on process integration issues during implementation into 90 and 65 nm SOI logic technologies: Transistor parameter fluctuation and pattern effects, power density limitations and the impact on the reliability of ultra-thin gate oxides, compatibility with new materials such as SiGe, transistor scaling and performance enhancement
由于需要减小垂直和横向器件尺寸,有或没有事先尖峰快速热退火(sRTA)的亚熔体激光和闪光退火最近引起了人们的关注。它结合了改进的活性区活化和减少栅极聚耗竭的过程,基本上没有额外的扩散。本文将重点讨论90纳米和65纳米SOI逻辑技术实施过程中的工艺集成问题:晶体管参数波动和模式效应,功率密度限制和对超薄栅极氧化物可靠性的影响,与SiGe等新材料的兼容性,晶体管缩放和性能增强
{"title":"Process Integration Issues with Spike, Flash and Laser Anneal Implementation for 90 and 65 NM Technologies","authors":"T. Feudel, M. Horstmann, L. Herrmann, M. Herden, M. Gerhardt, D. Greenlaw, P. Fisher, J. Kluth","doi":"10.1109/RTP.2006.367984","DOIUrl":"https://doi.org/10.1109/RTP.2006.367984","url":null,"abstract":"With the need to reduce vertical and lateral device dimensions, submelt laser and flash anneal either with or without prior spike rapid thermal anneal (sRTA) has recently attracted attention. It combines improved active area activation with reduced gate poly depletion for a process that is essentially free of additional diffusion. This paper will focus on process integration issues during implementation into 90 and 65 nm SOI logic technologies: Transistor parameter fluctuation and pattern effects, power density limitations and the impact on the reliability of ultra-thin gate oxides, compatibility with new materials such as SiGe, transistor scaling and performance enhancement","PeriodicalId":114586,"journal":{"name":"2006 14th IEEE International Conference on Advanced Thermal Processing of Semiconductors","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128103046","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Flash Annealing Technology for USJ: Modeling and Metrology USJ闪蒸退火技术:建模与计量
J. Gelpey, S. Mccoy, D. Camm, W. Lerch, S. Paul, P. Pichler, J. Borland, P. Timans
Millisecond annealing either by flash lamp or laser appears to be the leading approach to meet the needs of ultra-shallow junction annealing and polysilicon activation for advanced technology nodes. There are many advantages to this technology including high electrical activation, excellent lateral abruptness, controlled and limited dopant diffusion and the ability to engineer the extended defects remaining from the ion implantation. There are also many challenges such as potential pattern effects, local and global wafer stress and difficulty in process integration. Additional challenges include the need to extend the capabilities of process TCAD to allow accurate simulation and prediction of the ms processes. Modeling of diffusion, activation and defect evolution for a variety of technologically interesting doping conditions must be dependable to allow the device designer and process engineer to predict the device behavior after ms annealing. Existing models fall short or still need to be validated. Metrology for ultra-shallow junctions is also a challenge. The ability to accurately and repeatably measure sheet resistance and junction leakage on junctions of the order of 10nm deep is very difficult. This paper provides an overview of flash lamp annealing and deal with some promising extensions of process simulation to enable the predictive modeling of junction behavior under flash lamp annealing conditions. We also examine some of the new metrology techniques for characterization of these very shallow junctions and look at some of the trends exhibited for different junction formation details
闪光灯或激光毫秒退火似乎是满足先进技术节点的超浅结退火和多晶硅活化需求的主要方法。该技术有许多优点,包括高电活化、优异的横向突然性、可控和有限的掺杂扩散以及设计离子注入后遗留的扩展缺陷的能力。此外,还有许多挑战,如潜在的图案效应、局部和全局晶圆应力以及工艺集成的困难。其他挑战包括需要扩展过程TCAD的功能,以允许对ms过程进行准确的模拟和预测。对于各种技术上有趣的掺杂条件,扩散、激活和缺陷演变的建模必须是可靠的,以允许器件设计师和工艺工程师预测ms退火后的器件行为。现有的模型不足或仍然需要验证。超浅结的计量也是一个挑战。在10nm深的结上精确和重复测量片电阻和结漏的能力是非常困难的。本文概述了闪光灯退火,并讨论了过程模拟的一些有前途的扩展,以实现闪光灯退火条件下结行为的预测建模。我们还研究了一些新的计量技术,用于表征这些非常浅的结,并研究了不同结形成细节的一些趋势
{"title":"Flash Annealing Technology for USJ: Modeling and Metrology","authors":"J. Gelpey, S. Mccoy, D. Camm, W. Lerch, S. Paul, P. Pichler, J. Borland, P. Timans","doi":"10.1109/RTP.2006.367988","DOIUrl":"https://doi.org/10.1109/RTP.2006.367988","url":null,"abstract":"Millisecond annealing either by flash lamp or laser appears to be the leading approach to meet the needs of ultra-shallow junction annealing and polysilicon activation for advanced technology nodes. There are many advantages to this technology including high electrical activation, excellent lateral abruptness, controlled and limited dopant diffusion and the ability to engineer the extended defects remaining from the ion implantation. There are also many challenges such as potential pattern effects, local and global wafer stress and difficulty in process integration. Additional challenges include the need to extend the capabilities of process TCAD to allow accurate simulation and prediction of the ms processes. Modeling of diffusion, activation and defect evolution for a variety of technologically interesting doping conditions must be dependable to allow the device designer and process engineer to predict the device behavior after ms annealing. Existing models fall short or still need to be validated. Metrology for ultra-shallow junctions is also a challenge. The ability to accurately and repeatably measure sheet resistance and junction leakage on junctions of the order of 10nm deep is very difficult. This paper provides an overview of flash lamp annealing and deal with some promising extensions of process simulation to enable the predictive modeling of junction behavior under flash lamp annealing conditions. We also examine some of the new metrology techniques for characterization of these very shallow junctions and look at some of the trends exhibited for different junction formation details","PeriodicalId":114586,"journal":{"name":"2006 14th IEEE International Conference on Advanced Thermal Processing of Semiconductors","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128189021","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Low Thermal Budget Activation of B in Si B在Si中的低热收支活化
H. Bourdon, A. Halimaoui, A. Talbot, J. Venturini, O. Marcelot, D. Dutartre
Advanced devices may today require implantation and annealing steps after the metallic interconnection realization. Depending on the application, a thin p-doped layer has to be formed after wafer bonding. The issue, in such a case, is to correctly anneal the Boron implanted layer without degrading the buried devices and interconnections which lies at a depth around 3mum below the surface. Here, the authors propose to study different way to anneal this thin p-doped layer. Low energy and low dose implantations are performed without reaching the amorphisation threshold. Long thermal annealing at 400degC (RTP) and UV laser annealing are investigated through sheet resistance, thermal wave, SIMS or TEM. On one hand, a significant activation is obtained with RTP at temperature as low as 400degC and that Boron is activated with a better activation rate with B+ than with BF2 +. On the other hand, a much better activation was achieved with laser annealing as compared to RTP regardless of the implantation conditions
先进的器件在实现金属互连后可能需要植入和退火步骤。根据不同的应用,在晶圆键合后必须形成一层薄薄的掺杂p层。在这种情况下,问题是如何正确地退火硼植入层,而不破坏埋在地表以下约3米深处的设备和互连。在此,作者提出了不同的退火方法来研究这种薄掺杂p层。低能量和低剂量的植入在不达到非晶化阈值的情况下进行。通过片材电阻、热波、SIMS或TEM研究了400℃(RTP)长时间热退火和紫外激光退火。一方面,RTP在低至400℃的温度下具有明显的活化作用,并且B+比BF2 +具有更好的活化率。另一方面,与RTP相比,无论注入条件如何,激光退火都能获得更好的活化
{"title":"Low Thermal Budget Activation of B in Si","authors":"H. Bourdon, A. Halimaoui, A. Talbot, J. Venturini, O. Marcelot, D. Dutartre","doi":"10.1109/RTP.2006.368001","DOIUrl":"https://doi.org/10.1109/RTP.2006.368001","url":null,"abstract":"Advanced devices may today require implantation and annealing steps after the metallic interconnection realization. Depending on the application, a thin p-doped layer has to be formed after wafer bonding. The issue, in such a case, is to correctly anneal the Boron implanted layer without degrading the buried devices and interconnections which lies at a depth around 3mum below the surface. Here, the authors propose to study different way to anneal this thin p-doped layer. Low energy and low dose implantations are performed without reaching the amorphisation threshold. Long thermal annealing at 400degC (RTP) and UV laser annealing are investigated through sheet resistance, thermal wave, SIMS or TEM. On one hand, a significant activation is obtained with RTP at temperature as low as 400degC and that Boron is activated with a better activation rate with B+ than with BF2 +. On the other hand, a much better activation was achieved with laser annealing as compared to RTP regardless of the implantation conditions","PeriodicalId":114586,"journal":{"name":"2006 14th IEEE International Conference on Advanced Thermal Processing of Semiconductors","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133837603","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Laser Annealing Technology and Device Integration Challenges 激光退火技术和器件集成挑战
A. Shima
We have shown impacts of halo and deep source/drain (S/D) junction on the performance of devices that were fabricated by non-melt laser spike annealing (LSA). By optimizing both profiles, we achieved 10%-better performance and reduced hot carrier degradation compared to those by the conventional LSA that have only the optimized gate-S/D overlap structure. Gate pre-annealing by laser thermal process (LTP) was also investigated in conjunction with LSA S/D activation to effectively suppress poly-Si gate depletion while achieving highly activated ultra-shallow junctions in S/D, leading to improved transistor performance. Ioff was reduced more than one order of magnitude compared with conventional spike RTA devices
我们展示了光晕和深源/漏极(S/D)结对非熔体激光脉冲退火(LSA)制备器件性能的影响。通过优化这两种结构,与仅优化栅极- s /D重叠结构的传统LSA相比,我们的性能提高了10%,并减少了热载流子退化。通过激光热处理(LTP)的栅极预退火与LSA S/D激活也进行了研究,以有效抑制多晶硅栅极耗尽,同时在S/D中实现高度激活的超浅结,从而提高晶体管性能。与传统的尖峰RTA装置相比,Ioff降低了一个数量级以上
{"title":"Laser Annealing Technology and Device Integration Challenges","authors":"A. Shima","doi":"10.1109/RTP.2006.367976","DOIUrl":"https://doi.org/10.1109/RTP.2006.367976","url":null,"abstract":"We have shown impacts of halo and deep source/drain (S/D) junction on the performance of devices that were fabricated by non-melt laser spike annealing (LSA). By optimizing both profiles, we achieved 10%-better performance and reduced hot carrier degradation compared to those by the conventional LSA that have only the optimized gate-S/D overlap structure. Gate pre-annealing by laser thermal process (LTP) was also investigated in conjunction with LSA S/D activation to effectively suppress poly-Si gate depletion while achieving highly activated ultra-shallow junctions in S/D, leading to improved transistor performance. Ioff was reduced more than one order of magnitude compared with conventional spike RTA devices","PeriodicalId":114586,"journal":{"name":"2006 14th IEEE International Conference on Advanced Thermal Processing of Semiconductors","volume":"38 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125737834","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Rapid Thermal Processing Strategies for Highly Uniform and Repeatable Process Results on Patterned Wafers 快速热处理策略对高均匀和可重复的过程结果的图案晶圆
W. Yoo
Advantages and disadvantages of various types of temperature measurement techniques are reviewed in terms of potential temperature measurement errors and their impact on process consistency. Direct wafer temperature control and indirect wafer temperature control through control of the wafer environment are compared from the viewpoints of process accuracy and repeatability. The origin of both intrinsic and extrinsic pattern effects is identified and its impact on thermal non-uniformities in various wafer heating environments is analyzed. Based on the analysis, effective RTP strategies for highly uniform and repeatable process results on patterned wafers are proposed and discussed
从潜在的温度测量误差及其对过程一致性的影响方面综述了各种温度测量技术的优缺点。从工艺精度和可重复性的角度比较了直接控制晶圆温度和通过控制晶圆环境间接控制晶圆温度。确定了晶圆加热环境下的内禀和外禀图案效应的来源,并分析了其对热不均匀性的影响。在此基础上,提出并讨论了有效的RTP策略,以实现高均匀性和可重复性的工艺结果
{"title":"Rapid Thermal Processing Strategies for Highly Uniform and Repeatable Process Results on Patterned Wafers","authors":"W. Yoo","doi":"10.1109/RTP.2006.367997","DOIUrl":"https://doi.org/10.1109/RTP.2006.367997","url":null,"abstract":"Advantages and disadvantages of various types of temperature measurement techniques are reviewed in terms of potential temperature measurement errors and their impact on process consistency. Direct wafer temperature control and indirect wafer temperature control through control of the wafer environment are compared from the viewpoints of process accuracy and repeatability. The origin of both intrinsic and extrinsic pattern effects is identified and its impact on thermal non-uniformities in various wafer heating environments is analyzed. Based on the analysis, effective RTP strategies for highly uniform and repeatable process results on patterned wafers are proposed and discussed","PeriodicalId":114586,"journal":{"name":"2006 14th IEEE International Conference on Advanced Thermal Processing of Semiconductors","volume":"30 15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125860909","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Insertion Error in LPRT Temperature Measurements LPRT温度测量中的插入误差
Y. Qu, E. Puttitwong, J. Howell, O. Ezekoye
Accurate measurement of surface temperature distribution is of great concern in the semiconductor industries, particularly in rapid thermal processing (RTP). The International Technology Roadmap for Semiconductors 2004 (ITRS) has established requirements of uncertainties of plusmn1.5 degC at temperature of 1000 degC, with temperature calibration traceable to ITS-90 (International Temperature Scale-1990). Light-pipe radiation thermometers (LPRTs) are becoming increasingly important as an industrial tool for temperature measurement, especially in the semiconductor industry. However, there are several radiation issues associate with LPRTs, and without fully understanding them, achieving further accuracy could be hobbled. In this paper, we concentrate on the insertion error in the LPRTs temperature measurement. The "drawdown effect" and "shadow effect" are investigated. The "drawdown effect" is caused by the physical mass of the light-pipe probe acting as a heat sink for the measured object and the "shadow effect" is caused by distortion of radiosity due to the presence of the light-pipe probe. Monte Carlo simulation was conducted and compared to the experiment results
表面温度分布的精确测量在半导体工业,特别是在快速热加工(RTP)中是一个非常重要的问题。国际半导体技术路线图2004 (ITRS)建立了在1000℃温度下不确定度为±1.5℃的要求,温度校准可追溯到ITS-90(国际温标-1990)。光管辐射温度计(lprt)作为一种工业温度测量工具正变得越来越重要,特别是在半导体工业中。然而,有几个与lprt相关的辐射问题,如果不充分了解它们,可能会阻碍进一步的准确性。本文主要研究了lprt温度测量中的插入误差。研究了“收缩效应”和“阴影效应”。“衰减效应”是由光管探头的物理质量作为被测物体的散热器引起的,而“阴影效应”是由光管探头的存在引起的辐射失真引起的。进行了蒙特卡罗模拟,并与实验结果进行了比较
{"title":"Insertion Error in LPRT Temperature Measurements","authors":"Y. Qu, E. Puttitwong, J. Howell, O. Ezekoye","doi":"10.1109/RTP.2006.368012","DOIUrl":"https://doi.org/10.1109/RTP.2006.368012","url":null,"abstract":"Accurate measurement of surface temperature distribution is of great concern in the semiconductor industries, particularly in rapid thermal processing (RTP). The International Technology Roadmap for Semiconductors 2004 (ITRS) has established requirements of uncertainties of plusmn1.5 degC at temperature of 1000 degC, with temperature calibration traceable to ITS-90 (International Temperature Scale-1990). Light-pipe radiation thermometers (LPRTs) are becoming increasingly important as an industrial tool for temperature measurement, especially in the semiconductor industry. However, there are several radiation issues associate with LPRTs, and without fully understanding them, achieving further accuracy could be hobbled. In this paper, we concentrate on the insertion error in the LPRTs temperature measurement. The \"drawdown effect\" and \"shadow effect\" are investigated. The \"drawdown effect\" is caused by the physical mass of the light-pipe probe acting as a heat sink for the measured object and the \"shadow effect\" is caused by distortion of radiosity due to the presence of the light-pipe probe. Monte Carlo simulation was conducted and compared to the experiment results","PeriodicalId":114586,"journal":{"name":"2006 14th IEEE International Conference on Advanced Thermal Processing of Semiconductors","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133284765","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Raman Study on the Process of SI Advanced Integrated Circuits SI先进集成电路过程的拉曼研究
S. Nishibe, T. Sasaki, H. Harima, K. Kisoda, T. Yamazaki, W. Yoo
Precise control of fabrication processing is a key point for future integration technology of Si devices. Reliable characterization of Si wafers at each fabrication process is indispensable. Raman scattering has high-potential as a technique for noncontact and nondestructive characterization which yields valuable information on Si-based materials. Here, a patterned Si wafer for a modern electronic device is characterized by Raman microprobe to study the effect of different processes on residual stress, as well as other physical aspects
制造工艺的精确控制是未来硅器件集成技术的关键。在每个制造过程中,硅晶片的可靠特性是必不可少的。拉曼散射作为一种具有很高潜力的非接触和非破坏性表征技术,可以提供有价值的si基材料的信息。本文采用拉曼微探针对用于现代电子器件的图像化硅片进行表征,研究不同工艺对残余应力以及其他物理方面的影响
{"title":"Raman Study on the Process of SI Advanced Integrated Circuits","authors":"S. Nishibe, T. Sasaki, H. Harima, K. Kisoda, T. Yamazaki, W. Yoo","doi":"10.1109/RTP.2006.368002","DOIUrl":"https://doi.org/10.1109/RTP.2006.368002","url":null,"abstract":"Precise control of fabrication processing is a key point for future integration technology of Si devices. Reliable characterization of Si wafers at each fabrication process is indispensable. Raman scattering has high-potential as a technique for noncontact and nondestructive characterization which yields valuable information on Si-based materials. Here, a patterned Si wafer for a modern electronic device is characterized by Raman microprobe to study the effect of different processes on residual stress, as well as other physical aspects","PeriodicalId":114586,"journal":{"name":"2006 14th IEEE International Conference on Advanced Thermal Processing of Semiconductors","volume":"34 8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134222749","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
期刊
2006 14th IEEE International Conference on Advanced Thermal Processing of Semiconductors
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