S. Ogata, T. Oka, K. Tsuda, T. Nakayama, R. Kosugi
Effective NO passivation annealing for SiC MOSFET with extreme high temperature (>1400degC) at cold-wall oxidation furnace has been developed by AIST group. For this newly developed process, the thermal distribution and chemical reaction in the reactor are studied by computational numerical analysis. By comparing the experimental process and the simulated results, the spatial distribution of N atom on the wafer is suggested to be the key technology of nitridation process of SiO2/SiC interface
{"title":"Thermal Controllability of High Temperature (>1400°C) Rapid Thermal Oxidation for SiC MOSFET","authors":"S. Ogata, T. Oka, K. Tsuda, T. Nakayama, R. Kosugi","doi":"10.1109/RTP.2006.367994","DOIUrl":"https://doi.org/10.1109/RTP.2006.367994","url":null,"abstract":"Effective NO passivation annealing for SiC MOSFET with extreme high temperature (>1400degC) at cold-wall oxidation furnace has been developed by AIST group. For this newly developed process, the thermal distribution and chemical reaction in the reactor are studied by computational numerical analysis. By comparing the experimental process and the simulated results, the spatial distribution of N atom on the wafer is suggested to be the key technology of nitridation process of SiO2/SiC interface","PeriodicalId":114586,"journal":{"name":"2006 14th IEEE International Conference on Advanced Thermal Processing of Semiconductors","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125420034","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
An overview of the mechanical stress mechanisms observed within as deposited silicon oxide and nitride films deposited by the different techniques used for the CMOS transistors integration is presented in this paper. The evolution of the stress along the integration flow is described, with emphasize in the annealing steps. The impact of the film stress on the device is finally discussed especially in the case of integration of the shallow trench insulators and of the stress memorization technique
{"title":"Mechanical Stress in Silicon Based Materials: Evolution Upon Annealing and Impact on Devices Performances","authors":"P. Morin","doi":"10.1109/RTP.2006.367987","DOIUrl":"https://doi.org/10.1109/RTP.2006.367987","url":null,"abstract":"An overview of the mechanical stress mechanisms observed within as deposited silicon oxide and nitride films deposited by the different techniques used for the CMOS transistors integration is presented in this paper. The evolution of the stress along the integration flow is described, with emphasize in the annealing steps. The impact of the film stress on the device is finally discussed especially in the case of integration of the shallow trench insulators and of the stress memorization technique","PeriodicalId":114586,"journal":{"name":"2006 14th IEEE International Conference on Advanced Thermal Processing of Semiconductors","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114065324","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
T. Sasaki, S. Nishibe, H. Harima, T. Isshiki, M. Yoshimoto, K. Kisoda, W. Yoo, T. Fukada
Low-temperature formation processes of Ni silicide were studied by Raman scattering and cross-sectional transmission electron microscopy (TEM) using Si wafer samples deposited with thin Ni layers. Comparisons were made between two annealing methods; cold wall, lamp based rapid thermal process (lamp RTP) and a hot wall chamber RTP system. . The TEM and Raman observations showed good agreement on the Ni silicidation scheme at the Ni/Si interface. It is shown that Raman scattering spectroscopy is a convenient, non-contact and non-destructive characterization tool to probe and investigate the Ni-silicide formation process in the top nm-order surface of metal/Si contact, as well as to monitor the grain size variation of the silicides and residual stress in the Si wafer
{"title":"Raman Study of Low-Temperature Formation of Nickel Silicide Layers","authors":"T. Sasaki, S. Nishibe, H. Harima, T. Isshiki, M. Yoshimoto, K. Kisoda, W. Yoo, T. Fukada","doi":"10.1109/RTP.2006.368003","DOIUrl":"https://doi.org/10.1109/RTP.2006.368003","url":null,"abstract":"Low-temperature formation processes of Ni silicide were studied by Raman scattering and cross-sectional transmission electron microscopy (TEM) using Si wafer samples deposited with thin Ni layers. Comparisons were made between two annealing methods; cold wall, lamp based rapid thermal process (lamp RTP) and a hot wall chamber RTP system. . The TEM and Raman observations showed good agreement on the Ni silicidation scheme at the Ni/Si interface. It is shown that Raman scattering spectroscopy is a convenient, non-contact and non-destructive characterization tool to probe and investigate the Ni-silicide formation process in the top nm-order surface of metal/Si contact, as well as to monitor the grain size variation of the silicides and residual stress in the Si wafer","PeriodicalId":114586,"journal":{"name":"2006 14th IEEE International Conference on Advanced Thermal Processing of Semiconductors","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123911989","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The investigation results of the RTP enhanced diffusion of P in Si and Zn in GaAs, the mechanism, models and the role of quantum effects are presented in this paper. Shallow and ultra-shallow p+-n, n--p junctions have been obtained and analyzed. The experimental concentration profiles were simulated based on the dissociative diffusion mechanism. The diffusion coefficients and activation energies of the RTP enhanced diffusion and conventional furnace annealing was analyzed. The activation energy of RTP diffusion is lower than the conventional furnace diffusion and diffusion coefficient is higher by 1-3 order of magnitude. The p-n junctions with depth of 0.02 - 0.4 mum have been obtained by RTP for 0.1 - 3min diffusion time
{"title":"RTP Diffusion and Junction Formation in Si and GaAs","authors":"S. Shishiyanu","doi":"10.1109/RTP.2006.368000","DOIUrl":"https://doi.org/10.1109/RTP.2006.368000","url":null,"abstract":"The investigation results of the RTP enhanced diffusion of P in Si and Zn in GaAs, the mechanism, models and the role of quantum effects are presented in this paper. Shallow and ultra-shallow p+-n, n--p junctions have been obtained and analyzed. The experimental concentration profiles were simulated based on the dissociative diffusion mechanism. The diffusion coefficients and activation energies of the RTP enhanced diffusion and conventional furnace annealing was analyzed. The activation energy of RTP diffusion is lower than the conventional furnace diffusion and diffusion coefficient is higher by 1-3 order of magnitude. The p-n junctions with depth of 0.02 - 0.4 mum have been obtained by RTP for 0.1 - 3min diffusion time","PeriodicalId":114586,"journal":{"name":"2006 14th IEEE International Conference on Advanced Thermal Processing of Semiconductors","volume":"104 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122625603","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Narihiro, T. Iwamoto, T. Yamamoto, T. Ikezawa, K. Yako, M. Tanaka, A. Mineji, Y. Okuda, K. Uejima, S. Shishiguchi, M. Hane
Sub-30nm MOSFET fabrication technology is proposed based on a dedicated process redesign suitable for a non-melt laser annealing technique. Two major features of the laser annealing (LA), i.e. diffusion-less and higher dopant activation enable us to apply more elaborate channel engineering, involving multiple halo implantations and optimized gate-predoping, that contributes further scaling of a functional gate-length (Lg) and effective gate-insulator thickness (Tinv), maintaining sufficient current drivability prior to any local stress engineering applied, for instance, ION = 650/340 [muA/mum] (nMOS/pMOS) at IOFF = 100 nA/mum, Vdd = 0.9V, were obtained for sub-30nm Lg (and also sidewall length) devices
{"title":"Sub-30nm Mosfet Fabrication Technology Incorporating Precise Dopant Profile Design using Diffusion-Less High-Activation Laser Annealing","authors":"M. Narihiro, T. Iwamoto, T. Yamamoto, T. Ikezawa, K. Yako, M. Tanaka, A. Mineji, Y. Okuda, K. Uejima, S. Shishiguchi, M. Hane","doi":"10.1109/RTP.2006.367995","DOIUrl":"https://doi.org/10.1109/RTP.2006.367995","url":null,"abstract":"Sub-30nm MOSFET fabrication technology is proposed based on a dedicated process redesign suitable for a non-melt laser annealing technique. Two major features of the laser annealing (LA), i.e. diffusion-less and higher dopant activation enable us to apply more elaborate channel engineering, involving multiple halo implantations and optimized gate-predoping, that contributes further scaling of a functional gate-length (Lg) and effective gate-insulator thickness (Tinv), maintaining sufficient current drivability prior to any local stress engineering applied, for instance, ION = 650/340 [muA/mum] (nMOS/pMOS) at IOFF = 100 nA/mum, Vdd = 0.9V, were obtained for sub-30nm Lg (and also sidewall length) devices","PeriodicalId":114586,"journal":{"name":"2006 14th IEEE International Conference on Advanced Thermal Processing of Semiconductors","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129992663","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
K. Tsutsui, Y. Sasaki, C. Jin, H. Sauddin, K. Majima, Y. Fukagawa, I. Aiba, H. Ito, B. Mizuno, K. Kakushima, P. Ahmet, H. Iwai
Ultra-shallow P+/N junctions were formed by boron doping using plasma doping method combined with activation annealing using spike-RTA, flash lamp annealing or laser annealing. The junctions formed with flash lamp annealing or laser annealing were promising and superior to those formed by conventional low energy ion implantation method from the viewpoints of shallowness, abruptness and low sheet resistance. The pre-amorphization by He plasma treatment (He-PA process) played an important role for the successful formation or these junctions. Electrical properties were analyzed by not only sheet resistance but also Hall measurements and junction leakage measurement
{"title":"Ultra-Shallow Junction Formation by Plasma Doping and Flash Lamp Annealing","authors":"K. Tsutsui, Y. Sasaki, C. Jin, H. Sauddin, K. Majima, Y. Fukagawa, I. Aiba, H. Ito, B. Mizuno, K. Kakushima, P. Ahmet, H. Iwai","doi":"10.1109/RTP.2006.367980","DOIUrl":"https://doi.org/10.1109/RTP.2006.367980","url":null,"abstract":"Ultra-shallow P+/N junctions were formed by boron doping using plasma doping method combined with activation annealing using spike-RTA, flash lamp annealing or laser annealing. The junctions formed with flash lamp annealing or laser annealing were promising and superior to those formed by conventional low energy ion implantation method from the viewpoints of shallowness, abruptness and low sheet resistance. The pre-amorphization by He plasma treatment (He-PA process) played an important role for the successful formation or these junctions. Electrical properties were analyzed by not only sheet resistance but also Hall measurements and junction leakage measurement","PeriodicalId":114586,"journal":{"name":"2006 14th IEEE International Conference on Advanced Thermal Processing of Semiconductors","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130718230","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Nickel silicide was formed by heating sputtered Ni film on Si wafers in a stacked hotplate-based low temperature annealing system under 1 atm N2. The annealing temperature was varied in the range of 200 ~ 450degC. Sheet resistance, spectral reflectance and spectral absorbance of Ni film on Si wafers were measured before and after annealing. Formation of desirable stoichiometric NiSi was observed by sheet resistance measurement, X-ray diffraction and cross-sectional transmission electron microscopy over the wide temperature range of 300 ~ 450degC. Phase change from Ni2Si to NiSi was observed at approximately 300 ~ 350degC. The optical properties of nickel film, in particular spectral reflectance and absorbance, showed dramatic change during various stages of nickel silicide formation. Strong diffraction was observed from the patterned wafers. Microscopic reflectance and absorbance variation was observed from the patterned wafers as a result of the selective nature of silicidation. To minimize the negative impact of changes in optical properties during silicidation, radiation-based heating should be avoided as much as possible
{"title":"Changes in Optical Properties during Nickel Silicide Formation and Potential Impact on Process Results using Various Heating Methods","authors":"W. Yoo, T. Fukada, I. J. Malik","doi":"10.1109/RTP.2006.368007","DOIUrl":"https://doi.org/10.1109/RTP.2006.368007","url":null,"abstract":"Nickel silicide was formed by heating sputtered Ni film on Si wafers in a stacked hotplate-based low temperature annealing system under 1 atm N2. The annealing temperature was varied in the range of 200 ~ 450degC. Sheet resistance, spectral reflectance and spectral absorbance of Ni film on Si wafers were measured before and after annealing. Formation of desirable stoichiometric NiSi was observed by sheet resistance measurement, X-ray diffraction and cross-sectional transmission electron microscopy over the wide temperature range of 300 ~ 450degC. Phase change from Ni2Si to NiSi was observed at approximately 300 ~ 350degC. The optical properties of nickel film, in particular spectral reflectance and absorbance, showed dramatic change during various stages of nickel silicide formation. Strong diffraction was observed from the patterned wafers. Microscopic reflectance and absorbance variation was observed from the patterned wafers as a result of the selective nature of silicidation. To minimize the negative impact of changes in optical properties during silicidation, radiation-based heating should be avoided as much as possible","PeriodicalId":114586,"journal":{"name":"2006 14th IEEE International Conference on Advanced Thermal Processing of Semiconductors","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124388161","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
CMOS scaling laws have already lost the physical bases, and the merest results induced by scaling laws are still utilized for requirements from technology users. In this paper, the actual situation of CMOS shrinkage and a forecast are discussed
{"title":"Process-Integration Challenges with Up-To-Date Modulation of Scaling Laws","authors":"S. Nakai","doi":"10.1109/RTP.2006.367974","DOIUrl":"https://doi.org/10.1109/RTP.2006.367974","url":null,"abstract":"CMOS scaling laws have already lost the physical bases, and the merest results induced by scaling laws are still utilized for requirements from technology users. In this paper, the actual situation of CMOS shrinkage and a forecast are discussed","PeriodicalId":114586,"journal":{"name":"2006 14th IEEE International Conference on Advanced Thermal Processing of Semiconductors","volume":"1174 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121051816","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
I. J. Malik, M. Ouaknine, T. Ueda, T. Fukada, W. Yoo, D. Erbetta, T. Marangon
Thin cobalt silicide formation, including two phase transitions, was studied using a single-wafer rapid thermal furnace (SRTF) system. TiN-capped cobalt films on four types of wafer surfaces (monocrystalline Si, amorphous Si, n+ amorphous Si, and p+ amorphous Si) were investigated. Cobalt silicide process sensitivity was investigated in nitrogen ambient as a function of process temperature (350~700degC) and wafer surface condition. Process time (wafer residence time in a preheated near-isothermal process chamber) was fixed at 90s for simplicity. The cobalt silicidation showed two characteristic transition regions, one at about 450degC, and the other at between ~500degC and ~630degC, representing the two phase transitions during the silicidation sequence. The first transition temperature was at about 450degC regardless of wafer surface type. However, the second transition temperature was strongly influenced by the type of wafer surface. The authors focus their analysis on sheet resistance (sheet rho) and sheet rho uniformity of TiN-capped 9 nm thick cobalt films. Except for the phase transition regions around 450degC and 500~630degC, the sheet rho uniformity has improved as a result of annealing
{"title":"Cobalt Silicide Formation Characteristics in a Single Wafer Rapid Thermal Furnace (SRTF) System","authors":"I. J. Malik, M. Ouaknine, T. Ueda, T. Fukada, W. Yoo, D. Erbetta, T. Marangon","doi":"10.1109/RTP.2006.368005","DOIUrl":"https://doi.org/10.1109/RTP.2006.368005","url":null,"abstract":"Thin cobalt silicide formation, including two phase transitions, was studied using a single-wafer rapid thermal furnace (SRTF) system. TiN-capped cobalt films on four types of wafer surfaces (monocrystalline Si, amorphous Si, n+ amorphous Si, and p+ amorphous Si) were investigated. Cobalt silicide process sensitivity was investigated in nitrogen ambient as a function of process temperature (350~700degC) and wafer surface condition. Process time (wafer residence time in a preheated near-isothermal process chamber) was fixed at 90s for simplicity. The cobalt silicidation showed two characteristic transition regions, one at about 450degC, and the other at between ~500degC and ~630degC, representing the two phase transitions during the silicidation sequence. The first transition temperature was at about 450degC regardless of wafer surface type. However, the second transition temperature was strongly influenced by the type of wafer surface. The authors focus their analysis on sheet resistance (sheet rho) and sheet rho uniformity of TiN-capped 9 nm thick cobalt films. Except for the phase transition regions around 450degC and 500~630degC, the sheet rho uniformity has improved as a result of annealing","PeriodicalId":114586,"journal":{"name":"2006 14th IEEE International Conference on Advanced Thermal Processing of Semiconductors","volume":"4 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125842676","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Y. Setiawan, P. Lee, K. Pey, X.C. Wang, G. Lim, F. L. Chow
Effect of Ti alloying during both RTA and LTA on Ni silicide formation is studied. In the RTA annealed samples, Ni3Si2 was found to be the first silicide formed at 600degC and stable up to 900degC. On the other hand, unique triple layer microstructures were found in the sample after single-pulsed LTA at high laser fluence. Ti rapidly segregates from the alloy melt and forms a protective TiOx overlayer on the surface during rapid solidification
{"title":"Laser Annealed Ni(Ti) Silicides Formation","authors":"Y. Setiawan, P. Lee, K. Pey, X.C. Wang, G. Lim, F. L. Chow","doi":"10.1109/RTP.2006.368004","DOIUrl":"https://doi.org/10.1109/RTP.2006.368004","url":null,"abstract":"Effect of Ti alloying during both RTA and LTA on Ni silicide formation is studied. In the RTA annealed samples, Ni3Si2 was found to be the first silicide formed at 600degC and stable up to 900degC. On the other hand, unique triple layer microstructures were found in the sample after single-pulsed LTA at high laser fluence. Ti rapidly segregates from the alloy melt and forms a protective TiOx overlayer on the surface during rapid solidification","PeriodicalId":114586,"journal":{"name":"2006 14th IEEE International Conference on Advanced Thermal Processing of Semiconductors","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130818271","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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