T. Huelsmann, J. Niess, W. Lerch, O. Fursenko, D. Bolze
The effects of different initial Ni layer thickness and various anneal times during the nickel silicidation process have been investigated as a function of rapid thermal annealing temperature between 200 and 800degC. By means of electrical and optical measurements the Ni silicide phase transformations are explained. Spectroscopic ellipsometry has been used to measure Ni and Ni silicide thickness. An oxide on the Ni layer was found to be generated, if the time between Ni deposition and annealing is not short enough. Also a method to monitor the Ni silicidation process on RTP systems was introduced
{"title":"Impact of NI Layer Thickness and Anneal Time on Nickel Silicide Formation by Rapid Thermal Processing","authors":"T. Huelsmann, J. Niess, W. Lerch, O. Fursenko, D. Bolze","doi":"10.1109/RTP.2006.368006","DOIUrl":"https://doi.org/10.1109/RTP.2006.368006","url":null,"abstract":"The effects of different initial Ni layer thickness and various anneal times during the nickel silicidation process have been investigated as a function of rapid thermal annealing temperature between 200 and 800degC. By means of electrical and optical measurements the Ni silicide phase transformations are explained. Spectroscopic ellipsometry has been used to measure Ni and Ni silicide thickness. An oxide on the Ni layer was found to be generated, if the time between Ni deposition and annealing is not short enough. Also a method to monitor the Ni silicidation process on RTP systems was introduced","PeriodicalId":114586,"journal":{"name":"2006 14th IEEE International Conference on Advanced Thermal Processing of Semiconductors","volume":"127 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129894910","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Tanaka, S. Koyama, E. Hasegawa, C. Olsen, S. Shishiguchi, M. Hane
Nitrogen-rich and thin SiON gate dielectrics process using first plasma nitridation approach has been examined for 45nm-node CMOS application. This new process provides Tinv 1.8 nm with almost no degradation of the gm and no shift of Vth, and especially exhibits the higher immunity of the negative bias temperature instability (NBTI) even though the interfacial nitrogen concentration was observed to be higher than that of the conventional SiON process
{"title":"NBTI Immune First Plasma Nitridation SiON with Multiple Single-Wafer Tools for 45nm node Gate Dielectrics","authors":"M. Tanaka, S. Koyama, E. Hasegawa, C. Olsen, S. Shishiguchi, M. Hane","doi":"10.1109/RTP.2006.367992","DOIUrl":"https://doi.org/10.1109/RTP.2006.367992","url":null,"abstract":"Nitrogen-rich and thin SiON gate dielectrics process using first plasma nitridation approach has been examined for 45nm-node CMOS application. This new process provides Tinv 1.8 nm with almost no degradation of the gm and no shift of Vth, and especially exhibits the higher immunity of the negative bias temperature instability (NBTI) even though the interfacial nitrogen concentration was observed to be higher than that of the conventional SiON process","PeriodicalId":114586,"journal":{"name":"2006 14th IEEE International Conference on Advanced Thermal Processing of Semiconductors","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126007135","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
For chips with vertical flow of electrical current, an ohmic contact and/or emitter on the backside of the wafer are required. The formation of this electrical contact can be done using a laser annealing method in overlapping mode. Test on bare wafers and on productive chips were carried out using an excimer laser (lambda = 308 nm) with a laser energy density of more than 2 J/cm2 and a laser pulse duration of 180ns. Owing to the long pulse duration, deep melt activation with a molten zone with up to 400nm could be reached and an efficient emitter could be achieved
{"title":"Laser Thermal Annealing for Power Field Effect Transistor by using Deep Melt Activation","authors":"T. Gutt, H. Schulze, T. Rupp, J. Venturini","doi":"10.1109/RTP.2006.367999","DOIUrl":"https://doi.org/10.1109/RTP.2006.367999","url":null,"abstract":"For chips with vertical flow of electrical current, an ohmic contact and/or emitter on the backside of the wafer are required. The formation of this electrical contact can be done using a laser annealing method in overlapping mode. Test on bare wafers and on productive chips were carried out using an excimer laser (lambda = 308 nm) with a laser energy density of more than 2 J/cm2 and a laser pulse duration of 180ns. Owing to the long pulse duration, deep melt activation with a molten zone with up to 400nm could be reached and an efficient emitter could be achieved","PeriodicalId":114586,"journal":{"name":"2006 14th IEEE International Conference on Advanced Thermal Processing of Semiconductors","volume":"305 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122538161","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
K. Saki, M. Tamaoki, T. Shimizu, S. Ito, S. Mori, A. Shimazaki, I. Mizushima, A. Yamamoto
Influence of the atmosphere on ultra-thin oxynitride film was investigated for the precisely controlled plasma nitridation process. Some organic contaminant adsorb on the wafer before plasma nitridation process in clean room atmosphere. The adsorbed organic contaminant reduces the efficiency of plasma nitridation and increases the electrical thickness. The TDDB characteristic of ultra-thin oxynitride film was degraded due to the adsorbed organic contaminant. On the other hand, nitrogen concentration decreases due to exposure to an atmosphere after plasma nitridation process. The drop of nitrogen concentration causes Vth shift and Vth variation in MOSFET. The atmosphere and waiting time for post nitridation anneal affect on the drop of nitrogen concentration. It was demonstrated that the suppression of organic contamination before plasma nitridation and the control of the waiting time and atmosphere before post nitridation are the most important factors for the precise control of ultra-thin oxynitride film
{"title":"Influence of the Atmosphere on Ultra - Thin Oxynitride Film for Precisely Controled Plasma Nitridation Process","authors":"K. Saki, M. Tamaoki, T. Shimizu, S. Ito, S. Mori, A. Shimazaki, I. Mizushima, A. Yamamoto","doi":"10.1109/RTP.2006.367977","DOIUrl":"https://doi.org/10.1109/RTP.2006.367977","url":null,"abstract":"Influence of the atmosphere on ultra-thin oxynitride film was investigated for the precisely controlled plasma nitridation process. Some organic contaminant adsorb on the wafer before plasma nitridation process in clean room atmosphere. The adsorbed organic contaminant reduces the efficiency of plasma nitridation and increases the electrical thickness. The TDDB characteristic of ultra-thin oxynitride film was degraded due to the adsorbed organic contaminant. On the other hand, nitrogen concentration decreases due to exposure to an atmosphere after plasma nitridation process. The drop of nitrogen concentration causes Vth shift and Vth variation in MOSFET. The atmosphere and waiting time for post nitridation anneal affect on the drop of nitrogen concentration. It was demonstrated that the suppression of organic contamination before plasma nitridation and the control of the waiting time and atmosphere before post nitridation are the most important factors for the precise control of ultra-thin oxynitride film","PeriodicalId":114586,"journal":{"name":"2006 14th IEEE International Conference on Advanced Thermal Processing of Semiconductors","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125401590","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
H. Kennel, M. Giles, M. Diebel, P. Keys, J. Hwang, S. Govindaraju, M. Liu, A. Budrevich
Forming highly active shallow junctions is a key component enabling low external resistance and high transistor performance. Millisecond flash or scanning laser anneals can be used to contain diffusion and optimize activation, either directly by leveraging temperatures exceeding 1200C, or in combination with non-equilibrium processes such as amorphization plus solid phase epitaxy or liquid phase epitaxy. Diffusionless profiles can be obtained, but may not be optimal for devices. Consideration of deactivation physics is crucial to incorporation of any process leveraging superactive doping, since relaxation of doping is frequently very rapid, and may be crucially influenced by implant damage effects. Developing an understanding of dominant mechanisms is essential for the exploitation of millisecond or faster anneals to form superactive doping
{"title":"Kinetics of Shallow Junction Activation: Physical Mechanisms","authors":"H. Kennel, M. Giles, M. Diebel, P. Keys, J. Hwang, S. Govindaraju, M. Liu, A. Budrevich","doi":"10.1109/RTP.2006.367986","DOIUrl":"https://doi.org/10.1109/RTP.2006.367986","url":null,"abstract":"Forming highly active shallow junctions is a key component enabling low external resistance and high transistor performance. Millisecond flash or scanning laser anneals can be used to contain diffusion and optimize activation, either directly by leveraging temperatures exceeding 1200C, or in combination with non-equilibrium processes such as amorphization plus solid phase epitaxy or liquid phase epitaxy. Diffusionless profiles can be obtained, but may not be optimal for devices. Consideration of deactivation physics is crucial to incorporation of any process leveraging superactive doping, since relaxation of doping is frequently very rapid, and may be crucially influenced by implant damage effects. Developing an understanding of dominant mechanisms is essential for the exploitation of millisecond or faster anneals to form superactive doping","PeriodicalId":114586,"journal":{"name":"2006 14th IEEE International Conference on Advanced Thermal Processing of Semiconductors","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121819387","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We have investigated the crystalline and electrical properties of Ni silicide/Si and SiGeC contacts for ULSI applications. NiSi/Si contacts promises the contact resistivity as low as 10-8 Omegacm2 for both n+- and p+-Si. Degradation of the sheet resistance of NiSi layers critically depends on the annealing time particularly at temperatures ranging from 650degC to 750degC. The enlargement of the Si-exposed region concomitant with the NiSi agglomeration is a dominant factor responsible for the increase in sheet resistance and the activation energy of this process is estimated to be 2.8plusmn0.4 eV. Incorporation of Ge into Ni/Si systems is effective in raising the transformation temperature from NiSi to NiSi2. Incorporation of C into NiSi/Si system effectively suppresses the NiSi agglomeration. C introduction also causes the pile-up of B atoms at the NiSi/Si interface, which promises the reduction of the contact resistivity
{"title":"Ni-Silicide/Si and SiGe(C) Contact Technology for ULSI Applications","authors":"O. Nakatsuka, S. Zaima, A. Sakai, M. Ogawa","doi":"10.1109/RTP.2006.367979","DOIUrl":"https://doi.org/10.1109/RTP.2006.367979","url":null,"abstract":"We have investigated the crystalline and electrical properties of Ni silicide/Si and SiGeC contacts for ULSI applications. NiSi/Si contacts promises the contact resistivity as low as 10-8 Omegacm2 for both n+- and p+-Si. Degradation of the sheet resistance of NiSi layers critically depends on the annealing time particularly at temperatures ranging from 650degC to 750degC. The enlargement of the Si-exposed region concomitant with the NiSi agglomeration is a dominant factor responsible for the increase in sheet resistance and the activation energy of this process is estimated to be 2.8plusmn0.4 eV. Incorporation of Ge into Ni/Si systems is effective in raising the transformation temperature from NiSi to NiSi2. Incorporation of C into NiSi/Si system effectively suppresses the NiSi agglomeration. C introduction also causes the pile-up of B atoms at the NiSi/Si interface, which promises the reduction of the contact resistivity","PeriodicalId":114586,"journal":{"name":"2006 14th IEEE International Conference on Advanced Thermal Processing of Semiconductors","volume":"287 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124570536","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We investigated ultra-shallow junction prepared by plasma doping (PLAD) and laser annealing (LA). Although PLAD is promising doping technology for the sub-45nm technology node due to the high dose rate at low energy, it has problems which is related with hydrogen or fluorine. The implanted hydrogen generally increases damage in the Si substrate. The fluorine also retards dopant activation and increases dopant deactivation during post-annealing step. Conventional one step annealing processes such as rapid thermal annealing (RTA) or excimer laser annealing (LA) are not effective method for high dopant activation. To minimize the effect of hydrogen or fluorine, we propose additional pre-annealing followed by conventional laser annealing. By employing low temperature pre-annealing, we can improve electrical characteristics such as low sheet resistance, high activation rates, shallow junction depth and reduced dopant deactivation. The improvement can be explained by reduced defect density and out-diffusion of fluorine or hydrogen which in turn enhances dopant activation during ELA
{"title":"Ultra-shallow Junction Formed by Plasma Doping and Laser Annealing","authors":"S. Heo, H. Hwang","doi":"10.1109/RTP.2006.367985","DOIUrl":"https://doi.org/10.1109/RTP.2006.367985","url":null,"abstract":"We investigated ultra-shallow junction prepared by plasma doping (PLAD) and laser annealing (LA). Although PLAD is promising doping technology for the sub-45nm technology node due to the high dose rate at low energy, it has problems which is related with hydrogen or fluorine. The implanted hydrogen generally increases damage in the Si substrate. The fluorine also retards dopant activation and increases dopant deactivation during post-annealing step. Conventional one step annealing processes such as rapid thermal annealing (RTA) or excimer laser annealing (LA) are not effective method for high dopant activation. To minimize the effect of hydrogen or fluorine, we propose additional pre-annealing followed by conventional laser annealing. By employing low temperature pre-annealing, we can improve electrical characteristics such as low sheet resistance, high activation rates, shallow junction depth and reduced dopant deactivation. The improvement can be explained by reduced defect density and out-diffusion of fluorine or hydrogen which in turn enhances dopant activation during ELA","PeriodicalId":114586,"journal":{"name":"2006 14th IEEE International Conference on Advanced Thermal Processing of Semiconductors","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129952712","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
New applications of the double-pulsed laser annealing (DPLA) technologies were opened up in the coming-generation high-performance devices: insulated gate bipolar transistors (IGBTs) and low-temperature polycrystalline silicon thin-film transistors (LTPS-TFTs). The DPLA system was equipped with two solid-state lasers of a green wavelength as pulse laser sources. The line-beam irradiation was done in the same way as conventional excimer laser annealing (ELA) by making a sample stage scan at a constant speed while emitting the double-pulsed laser at 1kHz. The IGBTs demand deep PN junction in high electrical activation, while the LTPS-TFTs do high quality silicon thin films like a single crystal. The low-thermal budget annealing process enabled only the B- and P-implant layers within a depth of about 2mum to be activated without heating the whole wafer. The PN junction consisting of a B-implant layer and a P-implant layer reached more than 80% in activation ratios to adjust a delay time between double laser pulses. The advanced lateral crystal growth (ALCG) process enabled Si grains to be laterally and sequentially grown. The n-channel TFTs (L/W: 5mum/5mum) made of the ALCG-Si thin films reached a level of 600cm2/Vs in average mobility when the drain current flowed along the lateral-growth direction
{"title":"Double-Pulsed Laser Annealing Technologies and Related Applications","authors":"T. Kudo","doi":"10.1109/RTP.2006.367978","DOIUrl":"https://doi.org/10.1109/RTP.2006.367978","url":null,"abstract":"New applications of the double-pulsed laser annealing (DPLA) technologies were opened up in the coming-generation high-performance devices: insulated gate bipolar transistors (IGBTs) and low-temperature polycrystalline silicon thin-film transistors (LTPS-TFTs). The DPLA system was equipped with two solid-state lasers of a green wavelength as pulse laser sources. The line-beam irradiation was done in the same way as conventional excimer laser annealing (ELA) by making a sample stage scan at a constant speed while emitting the double-pulsed laser at 1kHz. The IGBTs demand deep PN junction in high electrical activation, while the LTPS-TFTs do high quality silicon thin films like a single crystal. The low-thermal budget annealing process enabled only the B- and P-implant layers within a depth of about 2mum to be activated without heating the whole wafer. The PN junction consisting of a B-implant layer and a P-implant layer reached more than 80% in activation ratios to adjust a delay time between double laser pulses. The advanced lateral crystal growth (ALCG) process enabled Si grains to be laterally and sequentially grown. The n-channel TFTs (L/W: 5mum/5mum) made of the ALCG-Si thin films reached a level of 600cm2/Vs in average mobility when the drain current flowed along the lateral-growth direction","PeriodicalId":114586,"journal":{"name":"2006 14th IEEE International Conference on Advanced Thermal Processing of Semiconductors","volume":"32 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123671205","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
KyungWon Lee, S. Kim, P. Frisella, B. Jacobs, G. Cai, R. Reece, N. Kwak, Chulyoung Ham, K. Joo, Dongho Lee, SangWook Park, Sungki Park
This paper presents a method to minimize cross-wafer threshold voltage variation, specifically radial variation, on device wafers using the inherent characteristics and repeatability of a bell-jar hot wall RTP system. The temperature uniformity of Axcelis' bell-jar hot wall RTP is controlled by a three-zone temperature gradient. It is possible to change the cross-wafer thermal uniformity from a flat or uniform distribution to either edge-hot, or edge-cold. The settings are characterized and optimized using sheet resistance monitors. It is demonstrated that by optimizing the power levels of the three-zone furnace, an optimized temperature gradient can be repeatedly formed and visualized by convex or concave sheet resistance maps. As results of the radial uniformity tuning, the RTP user can minimize the affect of process variations from other FEOL processes, such as etch or lithography as it is compensated by RTP process. This capability could enhance wafer yield below 80nm technology flash device through better control and uniformity of device parameters
{"title":"Improvement of within Wafer Uniformity of Device Parameters by Gradient Temperature Control with Bell Jar Hot Wall RTP","authors":"KyungWon Lee, S. Kim, P. Frisella, B. Jacobs, G. Cai, R. Reece, N. Kwak, Chulyoung Ham, K. Joo, Dongho Lee, SangWook Park, Sungki Park","doi":"10.1109/RTP.2006.368010","DOIUrl":"https://doi.org/10.1109/RTP.2006.368010","url":null,"abstract":"This paper presents a method to minimize cross-wafer threshold voltage variation, specifically radial variation, on device wafers using the inherent characteristics and repeatability of a bell-jar hot wall RTP system. The temperature uniformity of Axcelis' bell-jar hot wall RTP is controlled by a three-zone temperature gradient. It is possible to change the cross-wafer thermal uniformity from a flat or uniform distribution to either edge-hot, or edge-cold. The settings are characterized and optimized using sheet resistance monitors. It is demonstrated that by optimizing the power levels of the three-zone furnace, an optimized temperature gradient can be repeatedly formed and visualized by convex or concave sheet resistance maps. As results of the radial uniformity tuning, the RTP user can minimize the affect of process variations from other FEOL processes, such as etch or lithography as it is compensated by RTP process. This capability could enhance wafer yield below 80nm technology flash device through better control and uniformity of device parameters","PeriodicalId":114586,"journal":{"name":"2006 14th IEEE International Conference on Advanced Thermal Processing of Semiconductors","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117040889","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Statistical process control (SPC) has been widely practiced as a quality control method in the semiconductor industry. SPC is a system for monitoring, controlling, and improving a process through statistical analysis of monitored data. Control charts are widely used for process monitoring, but they are often misinterpreted. To improve process capability, the source of process variations must be properly identified from the control charts for proper feedback. Since the process tolerance is getting increasingly narrow, the importance of fundamental understanding of the source of process variations is an imperative. By eliminating or reducing process variation, a small improvement in process capability, can have a very significant business impact
{"title":"Growing Importance of Fundamental Understanding of the Source of Process Variations","authors":"S. Sato","doi":"10.1109/RTP.2006.367975","DOIUrl":"https://doi.org/10.1109/RTP.2006.367975","url":null,"abstract":"Statistical process control (SPC) has been widely practiced as a quality control method in the semiconductor industry. SPC is a system for monitoring, controlling, and improving a process through statistical analysis of monitored data. Control charts are widely used for process monitoring, but they are often misinterpreted. To improve process capability, the source of process variations must be properly identified from the control charts for proper feedback. Since the process tolerance is getting increasingly narrow, the importance of fundamental understanding of the source of process variations is an imperative. By eliminating or reducing process variation, a small improvement in process capability, can have a very significant business impact","PeriodicalId":114586,"journal":{"name":"2006 14th IEEE International Conference on Advanced Thermal Processing of Semiconductors","volume":"179 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115178192","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：