Pub Date : 2024-09-11DOI: 10.3390/electronics13183614
Junfeng Liu, Qinghua Zhao
Technology mapping is an essential process in the Electronic Design Automation (EDA) flow which aims to find an optimal implementation of a logic network from a technology library. In application-specific integrated circuit (ASIC) designs, the non-linear delay behaviors of cells in the library essentially guide the search direction of technology mappers. Existing methods for cell delay estimation, however, rely on approximate simplifications that significantly compromise accuracy, thereby limiting the achievement of better Quality-of-Result (QoR). To address this challenge, we propose formulating cell delay estimation as a regression learning task by incorporating multiple perspective features, such as the structure of logic networks and non-linear cell delays, to guide the mapper search. We design a learning model that incorporates a customized attention mechanism to be aware of the pin delay and jointly learns the hierarchy between the logic network and library through a Neural Tensor Network, with the help of proposed parameterizable strategies to generate learning labels. Experimental results show that (i) our proposed method noticeably improves area by 9.3% and delay by 1.5%, and (ii) improves area by 12.0% for delay-oriented mapping, compared with the well-known mapper.
{"title":"AiMap+: Guiding Technology Mapping for ASICs via Learning Delay Prediction","authors":"Junfeng Liu, Qinghua Zhao","doi":"10.3390/electronics13183614","DOIUrl":"https://doi.org/10.3390/electronics13183614","url":null,"abstract":"Technology mapping is an essential process in the Electronic Design Automation (EDA) flow which aims to find an optimal implementation of a logic network from a technology library. In application-specific integrated circuit (ASIC) designs, the non-linear delay behaviors of cells in the library essentially guide the search direction of technology mappers. Existing methods for cell delay estimation, however, rely on approximate simplifications that significantly compromise accuracy, thereby limiting the achievement of better Quality-of-Result (QoR). To address this challenge, we propose formulating cell delay estimation as a regression learning task by incorporating multiple perspective features, such as the structure of logic networks and non-linear cell delays, to guide the mapper search. We design a learning model that incorporates a customized attention mechanism to be aware of the pin delay and jointly learns the hierarchy between the logic network and library through a Neural Tensor Network, with the help of proposed parameterizable strategies to generate learning labels. Experimental results show that (i) our proposed method noticeably improves area by 9.3% and delay by 1.5%, and (ii) improves area by 12.0% for delay-oriented mapping, compared with the well-known mapper.","PeriodicalId":11646,"journal":{"name":"Electronics","volume":null,"pages":null},"PeriodicalIF":2.9,"publicationDate":"2024-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142209200","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-11DOI: 10.3390/electronics13183604
Zijie Xu, Erfu Wang
In recent years, the advancement of digital image processing technology and the proliferation of image editing software have reduced the technical barriers to digital image processing, enabling individuals without professional training to modify and edit images at their discretion. Consequently, the integrity and authenticity of the original image content assume greater significance. The current techniques for detecting tampering in watermark embedding are inadequate in terms of security, efficiency, and image restoration quality. In light of the aforementioned considerations, this paper puts forth an algorithm for the detection and restoration of tampered images, which employs a chaotic watermark embedding technique. The algorithm employs a chaotic system to establish a mapping relationship between image sub-blocks, thereby ensuring the randomness of the watermark information with respect to the positioning of the original image block and enhancing the security of the algorithm. Furthermore, the detection algorithm utilizes layered tampering detection to enhance the overall accuracy of the detection process and facilitate the extraction of the fundamental information required for image restoration. The restoration algorithm partially designs a weight assignment function to distinguish between the original image block and the main restored image block, thereby enhancing restoration efficiency and quality. The experimental results demonstrate that the proposed algorithm exhibits superior tamper detection accuracy compared to traditional algorithms, and the quality of the restored images is also enhanced under various simulated tamper attacks.
{"title":"An Algorithm for Detecting and Restoring Tampered Images Using Chaotic Watermark Embedding","authors":"Zijie Xu, Erfu Wang","doi":"10.3390/electronics13183604","DOIUrl":"https://doi.org/10.3390/electronics13183604","url":null,"abstract":"In recent years, the advancement of digital image processing technology and the proliferation of image editing software have reduced the technical barriers to digital image processing, enabling individuals without professional training to modify and edit images at their discretion. Consequently, the integrity and authenticity of the original image content assume greater significance. The current techniques for detecting tampering in watermark embedding are inadequate in terms of security, efficiency, and image restoration quality. In light of the aforementioned considerations, this paper puts forth an algorithm for the detection and restoration of tampered images, which employs a chaotic watermark embedding technique. The algorithm employs a chaotic system to establish a mapping relationship between image sub-blocks, thereby ensuring the randomness of the watermark information with respect to the positioning of the original image block and enhancing the security of the algorithm. Furthermore, the detection algorithm utilizes layered tampering detection to enhance the overall accuracy of the detection process and facilitate the extraction of the fundamental information required for image restoration. The restoration algorithm partially designs a weight assignment function to distinguish between the original image block and the main restored image block, thereby enhancing restoration efficiency and quality. The experimental results demonstrate that the proposed algorithm exhibits superior tamper detection accuracy compared to traditional algorithms, and the quality of the restored images is also enhanced under various simulated tamper attacks.","PeriodicalId":11646,"journal":{"name":"Electronics","volume":null,"pages":null},"PeriodicalIF":2.9,"publicationDate":"2024-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142209066","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-11DOI: 10.3390/electronics13183611
Qimao Zhang, Keyu Zhou, Ming Deng, Qisheng Zhang, Yongqiang Feng, Leisong Liu
The high-precision magnetic survey system is crucial for ocean exploration. However, most existing systems face challenges such as high noise levels, low sensitivity, and inadequate magnetic compensation effects. To address these issues, we developed a high-precision magnetic survey system based on the manned submersible “Deep Sea Warrior” for deep-ocean magnetic exploration. This system incorporates a compact optically pumped cesium (Cs) magnetometer sensor to measure the total strength of the external magnetic field. Additionally, a magnetic compensation sensor is included at the front end to measure real-time attitude changes of the platform. The measured data are then transmitted to a magnetic signal processor, where an algorithm compensates for the platform’s magnetic interference. We also designed a deep pressure chamber to allow for a maximum working depth of 4500 m. Experiments conducted in both indoor and field environments verified the performance of the proposed magnetic survey system. The results showed that the system’s sensitivity is ≤0.5 nT, the noise level of the magnetometer sensor is ≤1 pT/√Hz at 1 Hz, and the sampling rate is 10 Hz. The proposed system has potential applications in ocean and geophysical exploration.
{"title":"Development of a High-Precision Deep-Sea Magnetic Survey System for Human-Occupied Vehicles","authors":"Qimao Zhang, Keyu Zhou, Ming Deng, Qisheng Zhang, Yongqiang Feng, Leisong Liu","doi":"10.3390/electronics13183611","DOIUrl":"https://doi.org/10.3390/electronics13183611","url":null,"abstract":"The high-precision magnetic survey system is crucial for ocean exploration. However, most existing systems face challenges such as high noise levels, low sensitivity, and inadequate magnetic compensation effects. To address these issues, we developed a high-precision magnetic survey system based on the manned submersible “Deep Sea Warrior” for deep-ocean magnetic exploration. This system incorporates a compact optically pumped cesium (Cs) magnetometer sensor to measure the total strength of the external magnetic field. Additionally, a magnetic compensation sensor is included at the front end to measure real-time attitude changes of the platform. The measured data are then transmitted to a magnetic signal processor, where an algorithm compensates for the platform’s magnetic interference. We also designed a deep pressure chamber to allow for a maximum working depth of 4500 m. Experiments conducted in both indoor and field environments verified the performance of the proposed magnetic survey system. The results showed that the system’s sensitivity is ≤0.5 nT, the noise level of the magnetometer sensor is ≤1 pT/√Hz at 1 Hz, and the sampling rate is 10 Hz. The proposed system has potential applications in ocean and geophysical exploration.","PeriodicalId":11646,"journal":{"name":"Electronics","volume":null,"pages":null},"PeriodicalIF":2.9,"publicationDate":"2024-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142209064","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-11DOI: 10.3390/electronics13183603
Peiming Zhang, Jie Zhao, Qiaohong Liu, Xiao Liu, Xinyu Li, Yimeng Gao, Weiqi Li
To detect fundus diseases, for instance, diabetic retinopathy (DR) at an early stage, thereby providing timely intervention and treatment, a new diabetic retinopathy grading method based on a convolutional neural network is proposed. First, data cleaning and enhancement are conducted to improve the image quality and reduce unnecessary interference. Second, a new conditional generative adversarial network with a self-attention mechanism named SACGAN is proposed to augment the number of diabetic retinopathy fundus images, thereby addressing the problems of insufficient and imbalanced data samples. Next, an improved convolutional neural network named DRMC Net, which combines ResNeXt-50 with the channel attention mechanism and multi-branch convolutional residual module, is proposed to classify diabetic retinopathy. Finally, gradient-weighted class activation mapping (Grad-CAM) is utilized to prove the proposed model’s interpretability. The outcomes of the experiment illustrates that the proposed method has high accuracy, specificity, and sensitivity, with specific results of 92.3%, 92.5%, and 92.5%, respectively.
{"title":"Fundus Image Generation and Classification of Diabetic Retinopathy Based on Convolutional Neural Network","authors":"Peiming Zhang, Jie Zhao, Qiaohong Liu, Xiao Liu, Xinyu Li, Yimeng Gao, Weiqi Li","doi":"10.3390/electronics13183603","DOIUrl":"https://doi.org/10.3390/electronics13183603","url":null,"abstract":"To detect fundus diseases, for instance, diabetic retinopathy (DR) at an early stage, thereby providing timely intervention and treatment, a new diabetic retinopathy grading method based on a convolutional neural network is proposed. First, data cleaning and enhancement are conducted to improve the image quality and reduce unnecessary interference. Second, a new conditional generative adversarial network with a self-attention mechanism named SACGAN is proposed to augment the number of diabetic retinopathy fundus images, thereby addressing the problems of insufficient and imbalanced data samples. Next, an improved convolutional neural network named DRMC Net, which combines ResNeXt-50 with the channel attention mechanism and multi-branch convolutional residual module, is proposed to classify diabetic retinopathy. Finally, gradient-weighted class activation mapping (Grad-CAM) is utilized to prove the proposed model’s interpretability. The outcomes of the experiment illustrates that the proposed method has high accuracy, specificity, and sensitivity, with specific results of 92.3%, 92.5%, and 92.5%, respectively.","PeriodicalId":11646,"journal":{"name":"Electronics","volume":null,"pages":null},"PeriodicalIF":2.9,"publicationDate":"2024-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142209060","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-11DOI: 10.3390/electronics13183610
Li Yang, Qiaoni Zhao
Flywheel energy storage systems (FESSs) are widely used for power regulation in wind farms as they can balance the wind farms’ output power and improve the wind power grid connection rate. Due to the complex environment of wind farms, it is costly and time-consuming to repeatedly debug the system on-site. To save research costs and shorten research cycles, a hardware-in-the-loop (HIL) testing system was built to provide a convenient testing environment for the research of FESSs on wind farms. The focus of this study is the construction of mathematical models in the HIL testing system. Firstly, a mathematical model of the FESS main circuit is established using a hierarchical method. Secondly, the principle of the permanent magnet synchronous motor (PMSM) is analyzed, and a nonlinear dq mathematical model of the PMSM is established by referring to the relationship among d-axis inductance, q-axis inductance, and permanent magnet flux change with respect to the motor’s current. Then, the power grid and wind farm test models are established. Finally, the established mathematical models are applied to the HIL testing system. The experimental results indicated that the HIL testing system can provide a convenient testing environment for the optimization of FESS control algorithms.
飞轮储能系统（FESS）可平衡风电场的输出功率，提高风电并网率，因此被广泛用于风电场的功率调节。由于风电场环境复杂，现场反复调试成本高、耗时长。为了节约研究成本，缩短研究周期，我们建立了硬件在环（HIL）测试系统，为风电场 FESS 的研究提供了便捷的测试环境。本研究的重点是在 HIL 测试系统中构建数学模型。首先，采用分层方法建立了 FESS 主电路的数学模型。其次，分析了永磁同步电机（PMSM）的原理，并参考 d 轴电感、q 轴电感和永磁磁通随电机电流变化的关系，建立了 PMSM 的非线性 dq 数学模型。然后，建立电网和风电场测试模型。最后，将建立的数学模型应用于 HIL 测试系统。实验结果表明，HIL 测试系统可为 FESS 控制算法的优化提供便利的测试环境。
{"title":"Hardware-in-the-Loop Simulation of Flywheel Energy Storage Systems for Power Control in Wind Farms","authors":"Li Yang, Qiaoni Zhao","doi":"10.3390/electronics13183610","DOIUrl":"https://doi.org/10.3390/electronics13183610","url":null,"abstract":"Flywheel energy storage systems (FESSs) are widely used for power regulation in wind farms as they can balance the wind farms’ output power and improve the wind power grid connection rate. Due to the complex environment of wind farms, it is costly and time-consuming to repeatedly debug the system on-site. To save research costs and shorten research cycles, a hardware-in-the-loop (HIL) testing system was built to provide a convenient testing environment for the research of FESSs on wind farms. The focus of this study is the construction of mathematical models in the HIL testing system. Firstly, a mathematical model of the FESS main circuit is established using a hierarchical method. Secondly, the principle of the permanent magnet synchronous motor (PMSM) is analyzed, and a nonlinear dq mathematical model of the PMSM is established by referring to the relationship among d-axis inductance, q-axis inductance, and permanent magnet flux change with respect to the motor’s current. Then, the power grid and wind farm test models are established. Finally, the established mathematical models are applied to the HIL testing system. The experimental results indicated that the HIL testing system can provide a convenient testing environment for the optimization of FESS control algorithms.","PeriodicalId":11646,"journal":{"name":"Electronics","volume":null,"pages":null},"PeriodicalIF":2.9,"publicationDate":"2024-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142209114","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-11DOI: 10.3390/electronics13183617
Daniel Spiekermann, Tobias Eggendorfer, Jörg Keller
As organizations increasingly adopt virtualized environments for enhanced flexibility and scalability, securing virtual networks has become a critical part of current infrastructures. This research paper addresses the challenges related to intrusion detection in virtual networks, with a focus on various deep learning techniques. Since physical networks do not use encapsulation, but virtual networks do, packet analysis based on rules or machine learning outcomes for physical networks cannot be transferred directly to virtual environments. Encapsulation methods in current virtual networks include VXLAN (Virtual Extensible LAN), an EVPN (Ethernet Virtual Private Network), and NVGRE (Network Virtualization using Generic Routing Encapsulation). This paper analyzes the performance and effectiveness of network intrusion detection in virtual networks. It delves into challenges inherent in virtual network intrusion detection with deep learning, including issues such as traffic encapsulation, VM migration, and changing network internals inside the infrastructure. Experiments on detection performance demonstrate the differences between intrusion detection in virtual and physical networks.
{"title":"Deep Learning for Network Intrusion Detection in Virtual Networks","authors":"Daniel Spiekermann, Tobias Eggendorfer, Jörg Keller","doi":"10.3390/electronics13183617","DOIUrl":"https://doi.org/10.3390/electronics13183617","url":null,"abstract":"As organizations increasingly adopt virtualized environments for enhanced flexibility and scalability, securing virtual networks has become a critical part of current infrastructures. This research paper addresses the challenges related to intrusion detection in virtual networks, with a focus on various deep learning techniques. Since physical networks do not use encapsulation, but virtual networks do, packet analysis based on rules or machine learning outcomes for physical networks cannot be transferred directly to virtual environments. Encapsulation methods in current virtual networks include VXLAN (Virtual Extensible LAN), an EVPN (Ethernet Virtual Private Network), and NVGRE (Network Virtualization using Generic Routing Encapsulation). This paper analyzes the performance and effectiveness of network intrusion detection in virtual networks. It delves into challenges inherent in virtual network intrusion detection with deep learning, including issues such as traffic encapsulation, VM migration, and changing network internals inside the infrastructure. Experiments on detection performance demonstrate the differences between intrusion detection in virtual and physical networks.","PeriodicalId":11646,"journal":{"name":"Electronics","volume":null,"pages":null},"PeriodicalIF":2.9,"publicationDate":"2024-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142209068","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-11DOI: 10.3390/electronics13183615
Muhammad Furqan Javed, Muhammad Osama Imam, Muhammad Adnan, Iqbal Murtza, Jin-Young Kim
Object detection in maritime environments is a challenging problem because of the continuously changing background and moving objects resulting in shearing, occlusion, noise, etc. Unluckily, this problem is of critical importance since such failure may result in significant loss of human lives and economic loss. The available object detection methods rely on radar and sonar sensors. Even with the advances in electro-optical sensors, their employment in maritime object detection is rarely considered. The proposed research aims to employ both electro-optical and near-infrared sensors for effective maritime object detection. For this, dedicated deep learning detection models are trained on electro-optical and near-infrared (NIR) sensor datasets. For this, (ResNet-50, ResNet-101, and SSD MobileNet) are utilized in both electro-optical and near-infrared space. Then, dedicated ensemble classifications are constructed on each collection of base learners from electro-optical and near-infrared spaces. After this, decisions about object detection from these spaces are combined using logical-disjunction-based final ensemble classification. This strategy is utilized to reduce false negatives effectively. To evaluate the performance of the proposed methodology, the publicly available standard Singapore Maritime Dataset is used and the results show that the proposed methodology outperforms the contemporary maritime object detection techniques with a significantly improved mean average precision.
{"title":"Maritime Object Detection by Exploiting Electro-Optical and Near-Infrared Sensors Using Ensemble Learning","authors":"Muhammad Furqan Javed, Muhammad Osama Imam, Muhammad Adnan, Iqbal Murtza, Jin-Young Kim","doi":"10.3390/electronics13183615","DOIUrl":"https://doi.org/10.3390/electronics13183615","url":null,"abstract":"Object detection in maritime environments is a challenging problem because of the continuously changing background and moving objects resulting in shearing, occlusion, noise, etc. Unluckily, this problem is of critical importance since such failure may result in significant loss of human lives and economic loss. The available object detection methods rely on radar and sonar sensors. Even with the advances in electro-optical sensors, their employment in maritime object detection is rarely considered. The proposed research aims to employ both electro-optical and near-infrared sensors for effective maritime object detection. For this, dedicated deep learning detection models are trained on electro-optical and near-infrared (NIR) sensor datasets. For this, (ResNet-50, ResNet-101, and SSD MobileNet) are utilized in both electro-optical and near-infrared space. Then, dedicated ensemble classifications are constructed on each collection of base learners from electro-optical and near-infrared spaces. After this, decisions about object detection from these spaces are combined using logical-disjunction-based final ensemble classification. This strategy is utilized to reduce false negatives effectively. To evaluate the performance of the proposed methodology, the publicly available standard Singapore Maritime Dataset is used and the results show that the proposed methodology outperforms the contemporary maritime object detection techniques with a significantly improved mean average precision.","PeriodicalId":11646,"journal":{"name":"Electronics","volume":null,"pages":null},"PeriodicalIF":2.9,"publicationDate":"2024-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142226534","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-11DOI: 10.3390/electronics13183602
Konstantinos Koniavitis, Vassilis Alimisis, Nikolaos Uzunoglu, Paul P. Sotiriadis
This paper introduces a multiloop stabilized low-dropout regulator with a DC power supply rejection ratio of 85 dB and a phase margin of 80°. It is suitable for low-power, low-voltage and area-efficient applications since it consumes less than 100 μA. The dropout voltage is only 400 mV and the power supply rails are 1 V. Furthermore, a full mathematical analysis is conducted for stability and noise before the circuit verification. To confirm the proper operation of the implementation process, voltage and temperature corner variation simulations are extracted. The proposed regulator is designed and verified utilizing the Cadence IC Suite in a TSMC 90 nm CMOS process.
本文介绍了一种多环路稳定低压差稳压器，其直流电源抑制比为 85 dB，相位裕度为 80°。它适用于低功耗、低电压和节省面积的应用，因为其功耗低于 100 μA。压降电压仅为 400 mV，电源轨电压为 1 V。此外，在电路验证之前，还对稳定性和噪声进行了全面的数学分析。为确认实现过程的正常运行，还提取了电压和温度角变化模拟。所提议的稳压器是在 TSMC 90 纳米 CMOS 工艺中利用 Cadence IC Suite 设计和验证的。
{"title":"An Analog Integrated Multiloop LDO: From Analysis to Design","authors":"Konstantinos Koniavitis, Vassilis Alimisis, Nikolaos Uzunoglu, Paul P. Sotiriadis","doi":"10.3390/electronics13183602","DOIUrl":"https://doi.org/10.3390/electronics13183602","url":null,"abstract":"This paper introduces a multiloop stabilized low-dropout regulator with a DC power supply rejection ratio of 85 dB and a phase margin of 80°. It is suitable for low-power, low-voltage and area-efficient applications since it consumes less than 100 μA. The dropout voltage is only 400 mV and the power supply rails are 1 V. Furthermore, a full mathematical analysis is conducted for stability and noise before the circuit verification. To confirm the proper operation of the implementation process, voltage and temperature corner variation simulations are extracted. The proposed regulator is designed and verified utilizing the Cadence IC Suite in a TSMC 90 nm CMOS process.","PeriodicalId":11646,"journal":{"name":"Electronics","volume":null,"pages":null},"PeriodicalIF":2.9,"publicationDate":"2024-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142209056","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-11DOI: 10.3390/electronics13183607
Bassam Al-Masri, Nader Bakir, Ali El-Zaart, Khouloud Samrouth
Malware attacks have a cascading effect, causing financial harm, compromising privacy, operations and interrupting. By preventing these attacks, individuals and organizations can safeguard the valuable assets of their operations, and gain more trust. In this paper, we propose a dual convolutional neural network (DCNN) based architecture for malware classification. It consists first of converting malware binary files into 2D grayscale images and then training a customized dual CNN for malware multi-classification. This paper proposes an efficient approach for malware classification using dual CNNs. The model leverages the complementary strengths of a custom structure extraction branch and a pre-trained ResNet-50 model for malware image classification. By combining features extracted from both branches, the model achieved superior performance compared to a single-branch approach.
{"title":"Dual Convolutional Malware Network (DCMN): An Image-Based Malware Classification Using Dual Convolutional Neural Networks","authors":"Bassam Al-Masri, Nader Bakir, Ali El-Zaart, Khouloud Samrouth","doi":"10.3390/electronics13183607","DOIUrl":"https://doi.org/10.3390/electronics13183607","url":null,"abstract":"Malware attacks have a cascading effect, causing financial harm, compromising privacy, operations and interrupting. By preventing these attacks, individuals and organizations can safeguard the valuable assets of their operations, and gain more trust. In this paper, we propose a dual convolutional neural network (DCNN) based architecture for malware classification. It consists first of converting malware binary files into 2D grayscale images and then training a customized dual CNN for malware multi-classification. This paper proposes an efficient approach for malware classification using dual CNNs. The model leverages the complementary strengths of a custom structure extraction branch and a pre-trained ResNet-50 model for malware image classification. By combining features extracted from both branches, the model achieved superior performance compared to a single-branch approach.","PeriodicalId":11646,"journal":{"name":"Electronics","volume":null,"pages":null},"PeriodicalIF":2.9,"publicationDate":"2024-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142209062","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A single-phase grounding fault often occurs in 10 kV distribution networks, seriously affecting the safety of equipment and personnel. With the popularization of urban cables, the low-resistance grounding system gradually replaced arc suppression coils in some large cities. Compared to arc suppression coils, the low-resistance grounding system features simplicity and reliability. However, when a high-resistance grounding fault occurs, a lower amount of fault characteristics cannot trigger the zero-sequence protection action, so this type of fault will exist for a long time, which poses a threat to the power grid. To address this kind of problem, in this paper, a hybrid grounding system combining the low-resistance protection device and fully controlled power module is proposed. During a low-resistance grounding fault, the fault isolation is achieved through the zero-sequence current protection with the low-resistance grounding system itself, while, during a high-resistance grounding fault, the reliable arc extinction is achieved by regulating the neutral-point voltage with a fully controlled power module. Firstly, this paper introduces the principles, topology, and coordination control of the hybrid grounding system for active voltage arc extinction. Subsequently, a dual-loop-based control method is proposed to suppress the fault phase voltage. Furthermore, a faulty feeder selection method based on the Kepler optimization algorithm and convolutional neural network is proposed for the timely removal of permanent faults. Lastly, the simulation and HIL-based emulated results verify the rationality and effectiveness of the proposed method.
10 千伏配电网中经常发生单相接地故障，严重影响设备和人员的安全。随着城市电缆的普及，在一些大城市，低电阻接地系统逐渐取代了消弧线圈。与消弧线圈相比，低电阻接地系统具有简单可靠的特点。但是，当发生高阻接地故障时，较低的故障量特性无法触发零序保护动作，因此这类故障会长期存在，对电网造成威胁。针对此类问题，本文提出了一种低阻保护装置与全控功率模块相结合的混合接地系统。在低电阻接地故障中，通过低电阻接地系统本身的零序电流保护实现故障隔离；而在高电阻接地故障中，通过全控功率模块调节中性点电压实现可靠灭弧。本文首先介绍了主动电压灭弧混合接地系统的原理、拓扑结构和协调控制。随后，提出了一种基于双回路的控制方法来抑制故障相电压。此外，还提出了一种基于开普勒优化算法和卷积神经网络的故障馈线选择方法，以及时消除永久性故障。最后，仿真和基于 HIL 的模拟结果验证了所提方法的合理性和有效性。
{"title":"Neutral-Point Voltage Regulation and Control Strategy for Hybrid Grounding System Combining Power Module and Low Resistance in 10 kV Distribution Network","authors":"Yu Zhou, Kangli Liu, Wanglong Ding, Zitong Wang, Yuchen Yao, Tinghuang Wang, Yuhan Zhou","doi":"10.3390/electronics13183608","DOIUrl":"https://doi.org/10.3390/electronics13183608","url":null,"abstract":"A single-phase grounding fault often occurs in 10 kV distribution networks, seriously affecting the safety of equipment and personnel. With the popularization of urban cables, the low-resistance grounding system gradually replaced arc suppression coils in some large cities. Compared to arc suppression coils, the low-resistance grounding system features simplicity and reliability. However, when a high-resistance grounding fault occurs, a lower amount of fault characteristics cannot trigger the zero-sequence protection action, so this type of fault will exist for a long time, which poses a threat to the power grid. To address this kind of problem, in this paper, a hybrid grounding system combining the low-resistance protection device and fully controlled power module is proposed. During a low-resistance grounding fault, the fault isolation is achieved through the zero-sequence current protection with the low-resistance grounding system itself, while, during a high-resistance grounding fault, the reliable arc extinction is achieved by regulating the neutral-point voltage with a fully controlled power module. Firstly, this paper introduces the principles, topology, and coordination control of the hybrid grounding system for active voltage arc extinction. Subsequently, a dual-loop-based control method is proposed to suppress the fault phase voltage. Furthermore, a faulty feeder selection method based on the Kepler optimization algorithm and convolutional neural network is proposed for the timely removal of permanent faults. Lastly, the simulation and HIL-based emulated results verify the rationality and effectiveness of the proposed method.","PeriodicalId":11646,"journal":{"name":"Electronics","volume":null,"pages":null},"PeriodicalIF":2.9,"publicationDate":"2024-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142209063","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：