In this work we present a SPICE-based RTL subthreshold leakage model analyzing components built in 70nm technology. We present a separation approach regarding inter- and intra-die threshold variations, temperature, supply-voltage, and state dependence. The body-effect and differences between NMOS and PMOS introduce a leakage state dependence of one order of magnitude (Mukhopadhyay, 2003). We show that the leakage of RT-components still shows state dependencies between 20% and 80%. A leakage model not regarding the state can never be more accurate than this. The proposed state aware model has an average error of 6.7% for the RT-components analyzed
{"title":"Analysis and Modeling of Subthreshold Leakage of RT-Components under PTV and State Variation","authors":"D. Helms, Günter Ehmen, W. Nebel","doi":"10.1145/1165573.1165628","DOIUrl":"https://doi.org/10.1145/1165573.1165628","url":null,"abstract":"In this work we present a SPICE-based RTL subthreshold leakage model analyzing components built in 70nm technology. We present a separation approach regarding inter- and intra-die threshold variations, temperature, supply-voltage, and state dependence. The body-effect and differences between NMOS and PMOS introduce a leakage state dependence of one order of magnitude (Mukhopadhyay, 2003). We show that the leakage of RT-components still shows state dependencies between 20% and 80%. A leakage model not regarding the state can never be more accurate than this. The proposed state aware model has an average error of 6.7% for the RT-components analyzed","PeriodicalId":119229,"journal":{"name":"ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132470205","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper addresses the problem of low-power fanout optimization. We show that due to neglecting short-circuit current, previous analytical techniques proposed to optimize the area of a fanout tree may result in excessive power consumption. This show to achieve a low-power fanout tree, an accurate power consumption model should be used as the objective function. Moreover, we propose an efficient method to minimize the total power consumption of a fanout tree by using MTCMOS and multi-Vt techniques. Experimental results show that depending on the activity factor of the circuit, the proposed technique can reduce the power consumption of the fanout tree 18% to 45%
{"title":"Low-power Fanout Optimization Using MTCMOS and Multi-Vt Techniques","authors":"B. Amelifard, F. Fallah, Massoud Pedram","doi":"10.1145/1165573.1165652","DOIUrl":"https://doi.org/10.1145/1165573.1165652","url":null,"abstract":"This paper addresses the problem of low-power fanout optimization. We show that due to neglecting short-circuit current, previous analytical techniques proposed to optimize the area of a fanout tree may result in excessive power consumption. This show to achieve a low-power fanout tree, an accurate power consumption model should be used as the objective function. Moreover, we propose an efficient method to minimize the total power consumption of a fanout tree by using MTCMOS and multi-Vt techniques. Experimental results show that depending on the activity factor of the circuit, the proposed technique can reduce the power consumption of the fanout tree 18% to 45%","PeriodicalId":119229,"journal":{"name":"ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128335635","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Qinru Qiu, Qing Wu, Daniel J. Burns, Douglas J. Holzhauer
In this work we consider lifetime-aware resource management for sensor network using distributed genetic algorithm (GA). Our goal is to allocate different detection methods to different sensor nodes in the way such that the required detection probability can be achieved while the network lifetime is maximized. The contribution of this paper is twofold. Firstly, the resource management problem is formulated as a constraint optimization problem and is solved using a distributed GA. Secondly, empirical analysis results are provided that reveals the relationship between the configuration parameters and the quality of the search. A regression model is designed to estimate the runtime of the distributed GA given the configuration parameters. The model is utilized to find energy efficient configurations of the algorithm
{"title":"Lifetime Aware Resource Management for Sensor Network Using Distributed Genetic Algorithm","authors":"Qinru Qiu, Qing Wu, Daniel J. Burns, Douglas J. Holzhauer","doi":"10.1145/1165573.1165618","DOIUrl":"https://doi.org/10.1145/1165573.1165618","url":null,"abstract":"In this work we consider lifetime-aware resource management for sensor network using distributed genetic algorithm (GA). Our goal is to allocate different detection methods to different sensor nodes in the way such that the required detection probability can be achieved while the network lifetime is maximized. The contribution of this paper is twofold. Firstly, the resource management problem is formulated as a constraint optimization problem and is solved using a distributed GA. Secondly, empirical analysis results are provided that reveals the relationship between the configuration parameters and the quality of the search. A regression model is designed to estimate the runtime of the distributed GA given the configuration parameters. The model is utilized to find energy efficient configurations of the algorithm","PeriodicalId":119229,"journal":{"name":"ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128769360","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, we identify the key challenges that oppose sub-threshold circuit design and describe fabricated chips that verify techniques for overcoming the challenges
在本文中，我们确定了反对亚阈值电路设计的关键挑战，并描述了验证克服这些挑战的技术的制造芯片
{"title":"Sub-Threshold Design: The Challenges of Minimizing Circuit Energy","authors":"B. Calhoun, Alice Wang, N. Verma, A. Chandrakasan","doi":"10.1145/1165573.1165661","DOIUrl":"https://doi.org/10.1145/1165573.1165661","url":null,"abstract":"In this paper, we identify the key challenges that oppose sub-threshold circuit design and describe fabricated chips that verify techniques for overcoming the challenges","PeriodicalId":119229,"journal":{"name":"ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131256404","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In a mobile computer the hard disk consumes a considerable amount of energy. Existing dynamic power management policies usually take conservative approaches to save disk energy, and disk energy consumption remains a serious issue. Meanwhile, the flash drive is becoming a must-have portable storage device for almost every laptop user on travel. In this paper, we propose to make another highly desired use of the flash drive - saving disk energy. This is achieved by using the flash drive as a standby buffer for caching and prefetching disk data. Our design significantly extends disk idle times with careful and deliberate consideration of the particular characteristics of the flash drive. Trace-driven simulations show that up to 41% of disk energy can be saved with a relatively small amount of data written to the flash drive
{"title":"SmartSaver: Turning Flash Drive into a Disk Energy Saver for Mobile Computers","authors":"Feng Chen, Song Jiang, Xiaodong Zhang","doi":"10.1145/1165573.1165674","DOIUrl":"https://doi.org/10.1145/1165573.1165674","url":null,"abstract":"In a mobile computer the hard disk consumes a considerable amount of energy. Existing dynamic power management policies usually take conservative approaches to save disk energy, and disk energy consumption remains a serious issue. Meanwhile, the flash drive is becoming a must-have portable storage device for almost every laptop user on travel. In this paper, we propose to make another highly desired use of the flash drive - saving disk energy. This is achieved by using the flash drive as a standby buffer for caching and prefetching disk data. Our design significantly extends disk idle times with careful and deliberate consideration of the particular characteristics of the flash drive. Trace-driven simulations show that up to 41% of disk energy can be saved with a relatively small amount of data written to the flash drive","PeriodicalId":119229,"journal":{"name":"ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122309073","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
H. Singh, R. Senger, D. Sylvester, Richard B. Brown, K. Nowka
In this paper, we propose a new dual-VDD bus technique that is well suited for low power operation. This technique adapts a static pulsed bus architecture to use dual-VDD power supplies. During quiescent periods, the bus system idles at the lower of the two VDD supplies, thereby lowering static power dissipation. When actively transitioning, the inverters in the bus system are temporarily boosted to the higher VDD supply to provide the needed drive strength for performance. Since the VDD boosting is done in a pulsed manner, the bus system is in a high VDD state only when required, ensuring lower power operation without sacrificing performance. This technique yields up to a 50% reduction in total power over traditional static buses and up to a 35% reduction in total power over standard static pulsed buses, with a 12-15% delay improvement
{"title":"A Dual-VDD Boosted Pulsed Bus Technique for Low Power and Low Leakage Operation","authors":"H. Singh, R. Senger, D. Sylvester, Richard B. Brown, K. Nowka","doi":"10.1145/1165573.1165591","DOIUrl":"https://doi.org/10.1145/1165573.1165591","url":null,"abstract":"In this paper, we propose a new dual-VDD bus technique that is well suited for low power operation. This technique adapts a static pulsed bus architecture to use dual-VDD power supplies. During quiescent periods, the bus system idles at the lower of the two VDD supplies, thereby lowering static power dissipation. When actively transitioning, the inverters in the bus system are temporarily boosted to the higher VDD supply to provide the needed drive strength for performance. Since the VDD boosting is done in a pulsed manner, the bus system is in a high VDD state only when required, ensuring lower power operation without sacrificing performance. This technique yields up to a 50% reduction in total power over traditional static buses and up to a 35% reduction in total power over standard static pulsed buses, with a 12-15% delay improvement","PeriodicalId":119229,"journal":{"name":"ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124496910","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Hong-Wei Huang, Hsin-Hsin Ho, Ke-Horng Chen, S. Kuo
Dithering skip mode with a novel load sensor for DC-DC converters is proposed to maintain a high efficiency over a wide load range. Due to the efficiency drop of the transition from the pulse-width modulation (PWM) to pulse-frequency modulation (PFM), a novel dithering skip modulation (DSM) is introduced to smooth the efficiency curve. Importantly, DSM mode can dynamically skip the number of gate driving pulses, which is inverse proportional to load current. Besides, a novel proposed load sensor can automatically select the optimum modulation method from these three modulation methods without an external selection pin. Simulation results shows DSM can maintain the efficiency of converters as high as about 89% over a wide load current range from 3mA to 500mA
{"title":"Dithering Skip Modulator with a Novel Load Sensor for Ultra-wide-load High-Efficiency DC-DC Converters","authors":"Hong-Wei Huang, Hsin-Hsin Ho, Ke-Horng Chen, S. Kuo","doi":"10.1145/1165573.1165669","DOIUrl":"https://doi.org/10.1145/1165573.1165669","url":null,"abstract":"Dithering skip mode with a novel load sensor for DC-DC converters is proposed to maintain a high efficiency over a wide load range. Due to the efficiency drop of the transition from the pulse-width modulation (PWM) to pulse-frequency modulation (PFM), a novel dithering skip modulation (DSM) is introduced to smooth the efficiency curve. Importantly, DSM mode can dynamically skip the number of gate driving pulses, which is inverse proportional to load current. Besides, a novel proposed load sensor can automatically select the optimum modulation method from these three modulation methods without an external selection pin. Simulation results shows DSM can maintain the efficiency of converters as high as about 89% over a wide load current range from 3mA to 500mA","PeriodicalId":119229,"journal":{"name":"ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131372984","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Presented in this paper is the thread-associative memory microarchitecture for multicore and multithreaded processor design. Memory contention among concurrent threads in chip multithreaded processing has become a limiting factor for performance improvement. The proposed thread-associative memory addresses this challenge by incorporating thread-specific information explicitly into on-chip memory hardware. The proposed technique can be utilized at different levels of memory hierarchy. Furthermore, it is not just a technique for performance enhancement but also a solution for energy efficiency. Trace-driven simulations on a 32KB L1 data cache demonstrate 36.6% maximum performance improvement and up to 15.1% total energy reduction, with 20.3% dynamic energy reduction and 9.9% leakage energy reduction
{"title":"Thread-Associative Memory for Multicore and Multithreaded Computing","authors":"Shuo Wang, Lei Wang","doi":"10.1145/1165573.1165606","DOIUrl":"https://doi.org/10.1145/1165573.1165606","url":null,"abstract":"Presented in this paper is the thread-associative memory microarchitecture for multicore and multithreaded processor design. Memory contention among concurrent threads in chip multithreaded processing has become a limiting factor for performance improvement. The proposed thread-associative memory addresses this challenge by incorporating thread-specific information explicitly into on-chip memory hardware. The proposed technique can be utilized at different levels of memory hierarchy. Furthermore, it is not just a technique for performance enhancement but also a solution for energy efficiency. Trace-driven simulations on a 32KB L1 data cache demonstrate 36.6% maximum performance improvement and up to 15.1% total energy reduction, with 20.3% dynamic energy reduction and 9.9% leakage energy reduction","PeriodicalId":119229,"journal":{"name":"ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125255072","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Off-chip data bus consumes a significant part of system power. Recent works use small caches (value cache) at each side of the off-chip data bus, and transmit cache indexes instead of data values to reduce bus switching activity. A larger VC has a higher VC hit rate, but it also incurs more switching activity on a VC hit. In this paper, we propose the hierarchical VC design concept that provides a good tradeoff between VC capacity and bus switching activity. Our experimental results show that the proposed hierarchical VC design reduces the off-chip data bus energy by 60.2%
{"title":"Hierarchical Value Cache Encoding for Off-Chip Data Bus","authors":"Chung-Hsiang Lin, Chia-Lin Yang, K. King","doi":"10.1145/1165573.1165607","DOIUrl":"https://doi.org/10.1145/1165573.1165607","url":null,"abstract":"Off-chip data bus consumes a significant part of system power. Recent works use small caches (value cache) at each side of the off-chip data bus, and transmit cache indexes instead of data values to reduce bus switching activity. A larger VC has a higher VC hit rate, but it also incurs more switching activity on a VC hit. In this paper, we propose the hierarchical VC design concept that provides a good tradeoff between VC capacity and bus switching activity. Our experimental results show that the proposed hierarchical VC design reduces the off-chip data bus energy by 60.2%","PeriodicalId":119229,"journal":{"name":"ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126876784","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We present an innovative geometric programming (GP) approach for minimizing the power dissipation of an interconnect with repeater insertion, subject to delay, bandwidth and area constraints. Repeater sizes and segment lengths are globally optimized in various technology nodes with respect to International Technology Roadmap for Semiconductors (ITRS). Relative power dissipation due to different power components is analyzed. We show that, on average, the power dissipation per unit length can be reduced by over 30% when the timing constraint is relaxed by 5%. The optimum number of repeaters is always given as an integer in our design flow. The relationships between power dissipation and respective design constraints are easily visualized in tradeoff curves. Additional design criteria, such as reliability of the interconnect delay against process variations, are easily incorporated into the optimization
{"title":"Power Optimization In A Repeater-Inserted Interconnect Via Geometric Programming","authors":"W. Cheung, N. Wong","doi":"10.1145/1165573.1165629","DOIUrl":"https://doi.org/10.1145/1165573.1165629","url":null,"abstract":"We present an innovative geometric programming (GP) approach for minimizing the power dissipation of an interconnect with repeater insertion, subject to delay, bandwidth and area constraints. Repeater sizes and segment lengths are globally optimized in various technology nodes with respect to International Technology Roadmap for Semiconductors (ITRS). Relative power dissipation due to different power components is analyzed. We show that, on average, the power dissipation per unit length can be reduced by over 30% when the timing constraint is relaxed by 5%. The optimum number of repeaters is always given as an integer in our design flow. The relationships between power dissipation and respective design constraints are easily visualized in tradeoff curves. Additional design criteria, such as reliability of the interconnect delay against process variations, are easily incorporated into the optimization","PeriodicalId":119229,"journal":{"name":"ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116415309","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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