It is seen that power dissipation during test mode is quite high compared to that during the functional mode of operation of a digital circuit. This may lead to damage of certain chips only because they are tested, leading to unnecessary loss of yield. This paper presents a simple yet efficient low power scheme for scan-based BIST. It reduces test length and switching-activity in CUTs reducing power dissipation during test mode without compromising fault coverage. Experiments conducted on ISCAS89 benchmark circuits demonstrate that proposed scheme gives better fault coverage with a large reduction in transitions reducing power dissipation during testing
{"title":"Efficient Scan-Based BIST Scheme for Low Power Testing of VLSI Chips","authors":"Malav Shah","doi":"10.1145/1165573.1165667","DOIUrl":"https://doi.org/10.1145/1165573.1165667","url":null,"abstract":"It is seen that power dissipation during test mode is quite high compared to that during the functional mode of operation of a digital circuit. This may lead to damage of certain chips only because they are tested, leading to unnecessary loss of yield. This paper presents a simple yet efficient low power scheme for scan-based BIST. It reduces test length and switching-activity in CUTs reducing power dissipation during test mode without compromising fault coverage. Experiments conducted on ISCAS89 benchmark circuits demonstrate that proposed scheme gives better fault coverage with a large reduction in transitions reducing power dissipation during testing","PeriodicalId":119229,"journal":{"name":"ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design","volume":"378 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124719799","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a novel backlight driving technique for liquid crystal displays. By scaling the intensity, frequency, and duty cycle of the backlight, this technique not only increases the perceived brightness but also prolongs the service time of rechargeable batteries. The increased brightness comes from a perceptual effect of temporal vision - a brief flash appears brighter than a steady light of the same intensity, called Brucke brightness enhancement effect. The prolonged service time comes from the relaxation phenomenon - a lithium-ion battery lasts longer by pulsed discharge. Combining these two effects, a great amount of service time can be obtained at the cost of flickering. We performed visual experiments to parameterize the Brucke effect and derived an optimization algorithm accordingly. To demonstrate the potential energy savings of this technique, we profiled the power consumption of an Apple iPod and fabricated an LED driving module. Based on experimental data, 75% of energy consumption can be saved and the service time can be extended to 300%
{"title":"Temporal Vision-Guided Energy Minimization for Portable Displays","authors":"W. Cheng, Chih-Fu Hsu, Chain-Fu Chao","doi":"10.1145/1165573.1165595","DOIUrl":"https://doi.org/10.1145/1165573.1165595","url":null,"abstract":"This paper presents a novel backlight driving technique for liquid crystal displays. By scaling the intensity, frequency, and duty cycle of the backlight, this technique not only increases the perceived brightness but also prolongs the service time of rechargeable batteries. The increased brightness comes from a perceptual effect of temporal vision - a brief flash appears brighter than a steady light of the same intensity, called Brucke brightness enhancement effect. The prolonged service time comes from the relaxation phenomenon - a lithium-ion battery lasts longer by pulsed discharge. Combining these two effects, a great amount of service time can be obtained at the cost of flickering. We performed visual experiments to parameterize the Brucke effect and derived an optimization algorithm accordingly. To demonstrate the potential energy savings of this technique, we profiled the power consumption of an Apple iPod and fabricated an LED driving module. Based on experimental data, 75% of energy consumption can be saved and the service time can be extended to 300%","PeriodicalId":119229,"journal":{"name":"ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125874441","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Hakduran Koc, O. Ozturk, M. Kandemir, S. Narayanan, E. Ercanli
Banking has been identified as one of the effective methods using which memory energy can be reduced. We propose a novel approach that improves the energy effectiveness of banked memory architecture by performing extra computations if doing so makes it unnecessary to reactivate a bank which is in the low-power operating mode. More specifically, when an access to a bank, which is in the low-power mode, is to be made, our approach first checks whether the data required from that bank can be recomputed by using the data that are currently stored in already active banks. If this is the case, we do not turn on the bank in question, and instead, recalculate the value of the requested data using the values of the data stored in the active banks. Given the fact that the contribution of the leakage consumption to overall energy budget keeps increasing, the proposed approach has the potential of being even more attractive in the future. Our experimental results collected so far clearly show that this recomputation based approach can reduce energy consumption significantly
{"title":"Minimizing Energy Consumption of Banked Memories Using Data Recomputation","authors":"Hakduran Koc, O. Ozturk, M. Kandemir, S. Narayanan, E. Ercanli","doi":"10.1145/1165573.1165658","DOIUrl":"https://doi.org/10.1145/1165573.1165658","url":null,"abstract":"Banking has been identified as one of the effective methods using which memory energy can be reduced. We propose a novel approach that improves the energy effectiveness of banked memory architecture by performing extra computations if doing so makes it unnecessary to reactivate a bank which is in the low-power operating mode. More specifically, when an access to a bank, which is in the low-power mode, is to be made, our approach first checks whether the data required from that bank can be recomputed by using the data that are currently stored in already active banks. If this is the case, we do not turn on the bank in question, and instead, recalculate the value of the requested data using the values of the data stored in the active banks. Given the fact that the contribution of the leakage consumption to overall energy budget keeps increasing, the proposed approach has the potential of being even more attractive in the future. Our experimental results collected so far clearly show that this recomputation based approach can reduce energy consumption significantly","PeriodicalId":119229,"journal":{"name":"ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133192074","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Peter Wintermayr, R. Hartenstein, H. Meyr, S. Leibson
Both configurable computing paradigms as well as re-configurable computing paradigms have gained significant impact within the last few years. Both paradigms have shown to be effective when power consumption is a major design constraint even though the philosophies behind are quite different: configurable approaches aim to adapt an embedded processor to an application through, for example, an extensible instruction set plus other parameters that are determined during design time. They come in two basic flavors: starting with a fixed core that is extended by the system designer or; designing the instruction set from scratch for a specific application. Re-configurable approaches on the other side gain most of their benefits through run-time re-configuration. A high degree of parallelism is needed to overcome the physical deficiencies of re-configurable fabrics (e.g. FPGAs), though. The panel will discuss advantages and disadvantages of these paradigms with respect to low power
{"title":"Flexibility and Low Power; A Contradiction in Terms; Can Configurable or Re-Configurable Computing Offer Solutions?","authors":"Peter Wintermayr, R. Hartenstein, H. Meyr, S. Leibson","doi":"10.1145/1165573.1165665","DOIUrl":"https://doi.org/10.1145/1165573.1165665","url":null,"abstract":"Both configurable computing paradigms as well as re-configurable computing paradigms have gained significant impact within the last few years. Both paradigms have shown to be effective when power consumption is a major design constraint even though the philosophies behind are quite different: configurable approaches aim to adapt an embedded processor to an application through, for example, an extensible instruction set plus other parameters that are determined during design time. They come in two basic flavors: starting with a fixed core that is extended by the system designer or; designing the instruction set from scratch for a specific application. Re-configurable approaches on the other side gain most of their benefits through run-time re-configuration. A high degree of parallelism is needed to overcome the physical deficiencies of re-configurable fabrics (e.g. FPGAs), though. The panel will discuss advantages and disadvantages of these paradigms with respect to low power","PeriodicalId":119229,"journal":{"name":"ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129687199","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/SISPAD.2006.282826
S. Nassif
With the semiconductor industry pushing past the 65nm node and forward to 45nm and beyond, a host of phenomena are becoming prominent. For some time now, manufacturing variability and its impact on power and performance has captured the attention of the CAD research community, and is now transitioning to the commercial EDA market. Simultaneously, however, our ability to reliably predict the outcome of a semiconductor manufacturing process has been steadily deteriorating. This is happening because the rapidly increasing process complexity which is introducing a host of systematic sources of variation, as well as a natural increase in core random variability due to scaling. These factors increase the error in our performance predictions, and thus lead to a gap in model to hardware matching. In this tutorial, we will review the sources and impacts of model to hardware mismatch, and show examples of potential solutions to currently under development
{"title":"Model to Hardware Matching For nano-meter Scale Technologies","authors":"S. Nassif","doi":"10.1109/SISPAD.2006.282826","DOIUrl":"https://doi.org/10.1109/SISPAD.2006.282826","url":null,"abstract":"With the semiconductor industry pushing past the 65nm node and forward to 45nm and beyond, a host of phenomena are becoming prominent. For some time now, manufacturing variability and its impact on power and performance has captured the attention of the CAD research community, and is now transitioning to the commercial EDA market. Simultaneously, however, our ability to reliably predict the outcome of a semiconductor manufacturing process has been steadily deteriorating. This is happening because the rapidly increasing process complexity which is introducing a host of systematic sources of variation, as well as a natural increase in core random variability due to scaling. These factors increase the error in our performance predictions, and thus lead to a gap in model to hardware matching. In this tutorial, we will review the sources and impacts of model to hardware mismatch, and show examples of potential solutions to currently under development","PeriodicalId":119229,"journal":{"name":"ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127740055","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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