An integrated switched-capacitor (SC) DC-DC converter with a digital interleaving regulation scheme is presented. By interleaving the newly-structured charge pump (CP) cells in multiple phases, the input current ripple and output voltage ripple are reduced significantly. The converter exhibits excellent robustness, even when one of the CP cells fails to operate. A fully digital controller is employed with a hysteretic control algorithm. It features dead-beat system stability and fast transient response. Hspice post-layout simulation shows that, with a 1.5 V input power supply, the SC converter accurately provides an adjustable regulated power output in a range of 1.6 to 2.7 V. The maximum output ripple is 40 mV when a full load of 0.54 W is supplied. Transient response of 1.8 mus is observed when the load current switches from half- to full-load (from 100 to 200 mA)
{"title":"Robust Multiple-Phase Switched-Capacitor DC-DC, Converter with Digital Interleaving Regulation Scheme","authors":"D. Ma","doi":"10.1145/1165573.1165671","DOIUrl":"https://doi.org/10.1145/1165573.1165671","url":null,"abstract":"An integrated switched-capacitor (SC) DC-DC converter with a digital interleaving regulation scheme is presented. By interleaving the newly-structured charge pump (CP) cells in multiple phases, the input current ripple and output voltage ripple are reduced significantly. The converter exhibits excellent robustness, even when one of the CP cells fails to operate. A fully digital controller is employed with a hysteretic control algorithm. It features dead-beat system stability and fast transient response. Hspice post-layout simulation shows that, with a 1.5 V input power supply, the SC converter accurately provides an adjustable regulated power output in a range of 1.6 to 2.7 V. The maximum output ripple is 40 mV when a full load of 0.54 W is supplied. Transient response of 1.8 mus is observed when the load current switches from half- to full-load (from 100 to 200 mA)","PeriodicalId":119229,"journal":{"name":"ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116580173","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Due to the exponential increase in subthreshold leakage and gate leakage with technology scaling, leakage power is becoming a major fraction of total VLSI chip power in active mode. We present a novel active leakage power reduction technique, called the dynamic power cutoff technique (DPCT). First, the switching window for each gate, during which a gate makes its transitions, is identified by static timing analysis. Then, the circuit is optimally partitioned into different groups based on the minimal switching window (MSW) of each gate. Finally, power cutoff transistors are inserted into each group to control the power connections of that group. Each group is turned on only long enough for a wavefront of changing signals to propagate through that group. Since each gate is only turned on during a small timing window within each clock cycle, this significantly reduces active leakage power. This technique can also save standby leakage and dynamic power. Results on ISCAS'85 benchmark circuits modeled using 70 nm Berkeley predictive models (Cao et al., 2000) show up to 90% active leakage, 99% standby leakage, 54% dynamic power, and 72% total power savings
由于亚阈值泄漏和栅极泄漏随着技术的缩放呈指数级增长，在有源模式下，泄漏功率正在成为VLSI芯片总功率的主要部分。提出了一种新的有源泄漏功率降低技术，即动态功率切断技术(DPCT)。首先，通过静态时序分析确定每个门的切换窗口，在此期间一个门进行转换。然后，根据每个栅极的最小开关窗(MSW)将电路优化划分为不同的组。最后，在每一组中插入电源切断晶体管来控制该组的电源连接。每一组被打开的时间只够变化信号的波前在该组中传播。由于每个门只在每个时钟周期内的一个小定时窗口开启，这大大降低了有源泄漏功率。该技术还可以节省待机泄漏和动态功率。使用70 nm Berkeley预测模型(Cao et al.， 2000)建模的ISCAS’85基准电路的结果显示，高达90%的有源泄漏，99%的待机泄漏，54%的动态功率和72%的总功耗节省
{"title":"A Novel Dynamic Power Cutoff Technique (DPCT) for Active Leakage Reduction in Deep Submicron CMOS Circuits","authors":"Baozhen Yu, M. Bushnell","doi":"10.1145/1165573.1165627","DOIUrl":"https://doi.org/10.1145/1165573.1165627","url":null,"abstract":"Due to the exponential increase in subthreshold leakage and gate leakage with technology scaling, leakage power is becoming a major fraction of total VLSI chip power in active mode. We present a novel active leakage power reduction technique, called the dynamic power cutoff technique (DPCT). First, the switching window for each gate, during which a gate makes its transitions, is identified by static timing analysis. Then, the circuit is optimally partitioned into different groups based on the minimal switching window (MSW) of each gate. Finally, power cutoff transistors are inserted into each group to control the power connections of that group. Each group is turned on only long enough for a wavefront of changing signals to propagate through that group. Since each gate is only turned on during a small timing window within each clock cycle, this significantly reduces active leakage power. This technique can also save standby leakage and dynamic power. Results on ISCAS'85 benchmark circuits modeled using 70 nm Berkeley predictive models (Cao et al., 2000) show up to 90% active leakage, 99% standby leakage, 54% dynamic power, and 72% total power savings","PeriodicalId":119229,"journal":{"name":"ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design","volume":"30 15","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113942679","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We present our approach for a new macromodule power model library which can be used in high-level dynamic power estimation for FPGA technologies. The approach adapts a previously published high-level estimation flow for ASIC technologies. Due to the different architectures (ASIC vs. FPGA) the presented approach builds on an iterative optimization step during the model generation phase
{"title":"Modelling Macromodules for High-Level Dynamic Power Estimation of FPGA-based Digital Designs","authors":"A. Reimer, Arne Schulz, W. Nebel","doi":"10.1145/1165573.1165609","DOIUrl":"https://doi.org/10.1145/1165573.1165609","url":null,"abstract":"We present our approach for a new macromodule power model library which can be used in high-level dynamic power estimation for FPGA technologies. The approach adapts a previously published high-level estimation flow for ASIC technologies. Due to the different architectures (ASIC vs. FPGA) the presented approach builds on an iterative optimization step during the model generation phase","PeriodicalId":119229,"journal":{"name":"ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130915671","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Harvesting energy from the environment is a desirable and increasingly important capability in several emerging applications of embedded systems such as sensor networks, biomedical implants, etc. While energy harvesting has the potential to enable near-perpetual system operation, designing an efficient energy harvesting system that actually realizes this potential requires an in-depth understanding of several complex tradeoffs. These tradeoffs arise due to the interaction of numerous factors such as the characteristics of the harvesting transducers, chemistry and capacity of the batteries used (if any), power supply requirements and power management features of the embedded system, application behavior, etc. This paper surveys the various issues and tradeoffs involved in designing and operating energy harvesting embedded systems. System design techniques are described that target high conversion and storage efficiency by extracting the most energy from the environment and making it maximally available for consumption. Harvesting aware power management techniques are also described, which reconcile the very different spatio-temporal characteristics of energy availability and energy usage within a system and across a network
{"title":"Design and Power Management of Energy Harvesting Embedded Systems","authors":"V. Raghunathan, P. Chou","doi":"10.1145/1165573.1165663","DOIUrl":"https://doi.org/10.1145/1165573.1165663","url":null,"abstract":"Harvesting energy from the environment is a desirable and increasingly important capability in several emerging applications of embedded systems such as sensor networks, biomedical implants, etc. While energy harvesting has the potential to enable near-perpetual system operation, designing an efficient energy harvesting system that actually realizes this potential requires an in-depth understanding of several complex tradeoffs. These tradeoffs arise due to the interaction of numerous factors such as the characteristics of the harvesting transducers, chemistry and capacity of the batteries used (if any), power supply requirements and power management features of the embedded system, application behavior, etc. This paper surveys the various issues and tradeoffs involved in designing and operating energy harvesting embedded systems. System design techniques are described that target high conversion and storage efficiency by extracting the most energy from the environment and making it maximally available for consumption. Harvesting aware power management techniques are also described, which reconcile the very different spatio-temporal characteristics of energy availability and energy usage within a system and across a network","PeriodicalId":119229,"journal":{"name":"ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122180172","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper different logic circuit families operating in the subthreshold region are analyzed. Their performance in terms of power and speed are of particular interest. The study complements existing work that has reported static CMOS circuit performance under different body biasing schemes in the subthreshold region. Further it offers assurances on noise margins with scaling going beyond the 100 nm technology node. Simulations have been performed at the 180 nm technology node using a 6 metal layer TSMC process. A tunable body biasing scheme that allows bulk CMOS circuits to operate efficiently at subthreshold as well as above threshold voltages is introduced. The scheme improves a five-stage NAND ring oscillator switching speed 6times better than the static CMOS configuration while dissipating 18% less power
{"title":"Logic Circuits Operating in Subthreshold Voltages","authors":"J. Nyathi, B. Bero","doi":"10.1145/1165573.1165604","DOIUrl":"https://doi.org/10.1145/1165573.1165604","url":null,"abstract":"In this paper different logic circuit families operating in the subthreshold region are analyzed. Their performance in terms of power and speed are of particular interest. The study complements existing work that has reported static CMOS circuit performance under different body biasing schemes in the subthreshold region. Further it offers assurances on noise margins with scaling going beyond the 100 nm technology node. Simulations have been performed at the 180 nm technology node using a 6 metal layer TSMC process. A tunable body biasing scheme that allows bulk CMOS circuits to operate efficiently at subthreshold as well as above threshold voltages is introduced. The scheme improves a five-stage NAND ring oscillator switching speed 6times better than the static CMOS configuration while dissipating 18% less power","PeriodicalId":119229,"journal":{"name":"ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122664776","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, we propose an effective dynamic thermal management (DTM) scheme for MPEG-2 decoding by allowing some degree of spatiotemporal quality degradation. Given a target MPEG-2 decoding time, we dynamically select either an intra-frame spatial degradation or an inter-frame temporal degradation strategy in order to make sure that the microprocessor chip continues to stay in a thermally safe state of operation, albeit with certain amount of image/video quality loss. For our experiments, we use the MPEG-2 decoder program of MediaBench and modify/combine Wattch and HotSpot for the power and thermal simulations and measurements, respectively. Our experimental results show that we achieve thermally safe state with spatial quality degradation of 0.12 root mean square error (RMSE) and with frame drop rate of 12.5% on average
{"title":"Dynamic Thermal Management for MPEG-2 Decoding","authors":"Wonbok Lee, Kimish Patel, Massoud Pedram","doi":"10.1145/1165573.1165647","DOIUrl":"https://doi.org/10.1145/1165573.1165647","url":null,"abstract":"In this paper, we propose an effective dynamic thermal management (DTM) scheme for MPEG-2 decoding by allowing some degree of spatiotemporal quality degradation. Given a target MPEG-2 decoding time, we dynamically select either an intra-frame spatial degradation or an inter-frame temporal degradation strategy in order to make sure that the microprocessor chip continues to stay in a thermally safe state of operation, albeit with certain amount of image/video quality loss. For our experiments, we use the MPEG-2 decoder program of MediaBench and modify/combine Wattch and HotSpot for the power and thermal simulations and measurements, respectively. Our experimental results show that we achieve thermally safe state with spatial quality degradation of 0.12 root mean square error (RMSE) and with frame drop rate of 12.5% on average","PeriodicalId":119229,"journal":{"name":"ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124375736","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Challenges in multicore processor design include meeting demands for performance, power, and reliability. The progression towards deep submicron process technologies entails increasing challenges of process variability resulting in timing instabilities and leakage power variation. This work introduces an analytical approach for ensuring timing reliability while meeting the appropriate performance and power demands in spite of process variation. We validate our analytical model using Turandot to simulate an 8-core PowerPCtrade processor. We first examine a simplified case of our model on a platform running independent multiprogrammed workloads consisting of all 26 of the SPEC 2000 benchmarks. Our simple model accurately predicts the cutoff point with a mean error less than 0.5 W. Next, we extend our analysis to parallel programming by incorporating Amdahl's law in our equations. We use this relation to establish limit properties of power-performance for scaling parallel applications, and validate our findings using 8 applications from the SPLASH-2 benchmark suite
{"title":"Power Efficiency for Variation-Tolerant Multicore Processors","authors":"J. Donald, M. Martonosi","doi":"10.1145/1165573.1165645","DOIUrl":"https://doi.org/10.1145/1165573.1165645","url":null,"abstract":"Challenges in multicore processor design include meeting demands for performance, power, and reliability. The progression towards deep submicron process technologies entails increasing challenges of process variability resulting in timing instabilities and leakage power variation. This work introduces an analytical approach for ensuring timing reliability while meeting the appropriate performance and power demands in spite of process variation. We validate our analytical model using Turandot to simulate an 8-core PowerPCtrade processor. We first examine a simplified case of our model on a platform running independent multiprogrammed workloads consisting of all 26 of the SPEC 2000 benchmarks. Our simple model accurately predicts the cutoff point with a mean error less than 0.5 W. Next, we extend our analysis to parallel programming by incorporating Amdahl's law in our equations. We use this relation to establish limit properties of power-performance for scaling parallel applications, and validate our findings using 8 applications from the SPLASH-2 benchmark suite","PeriodicalId":119229,"journal":{"name":"ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design","volume":"346 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133790482","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Three DRAM technologies, which are a leakage- and soft-error-free planar-capacitor SOI cell, a data-line shielded twin (2-T) cell array, and an offset-free dynamic-VT sense amplifier suitable for low-voltage mid-point sensing, are presented and evaluated. New noise-generation mechanisms are also shown. Using the experimental data of an ultrathin BOX double-gate fully-depleted SOI MOST, a 1.5-ns cycle-time 65-nm 2-kb subarray was found to be feasible for embedded applications, even at 0.5 V
{"title":"A 0.5-V FD-SOI Twin-Cell DRAM with Offset-Free Dynamic-VT Sense Amplifiers","authors":"R. Takemura, K. Itoh, T. Sekiguchi","doi":"10.1145/1165573.1165602","DOIUrl":"https://doi.org/10.1145/1165573.1165602","url":null,"abstract":"Three DRAM technologies, which are a leakage- and soft-error-free planar-capacitor SOI cell, a data-line shielded twin (2-T) cell array, and an offset-free dynamic-VT sense amplifier suitable for low-voltage mid-point sensing, are presented and evaluated. New noise-generation mechanisms are also shown. Using the experimental data of an ultrathin BOX double-gate fully-depleted SOI MOST, a 1.5-ns cycle-time 65-nm 2-kb subarray was found to be feasible for embedded applications, even at 0.5 V","PeriodicalId":119229,"journal":{"name":"ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134096451","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Mobile applications with battery lifetimes on the order of thousands of days have placed stringent energy requirements on circuits. In this paper, we propose a new energy optimization technique for ultra-low energy circuits operating in the sub threshold regime. Our technique uses simultaneous gate sizing and supply voltage scaling to reduce energy. We demonstrate the effectiveness of our technique on benchmark circuits and offer insight on the roles of the timing distribution and wire capacitance in determining the achievable energy reductions
{"title":"A New Technique for Jointly Optimizing Gate Sizing and Supply Voltage in Ultra-Low Energy Circuits","authors":"S. Hanson, D. Sylvester, D. Blaauw","doi":"10.1145/1165573.1165653","DOIUrl":"https://doi.org/10.1145/1165573.1165653","url":null,"abstract":"Mobile applications with battery lifetimes on the order of thousands of days have placed stringent energy requirements on circuits. In this paper, we propose a new energy optimization technique for ultra-low energy circuits operating in the sub threshold regime. Our technique uses simultaneous gate sizing and supply voltage scaling to reduce energy. We demonstrate the effectiveness of our technique on benchmark circuits and offer insight on the roles of the timing distribution and wire capacitance in determining the achievable energy reductions","PeriodicalId":119229,"journal":{"name":"ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125668708","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper proposes a simple, yet accurate, analytical model for the effect of opamp gain and dynamics (slew rate and bandwidth) on the transfer function of switched-capacitor (SC) amplifiers and integrators. Furthermore, it demonstrates the detrimental effects of: a) the nonlinear variation in the opamp dc gain; and b) the feedforward transmission of the feedback capacitor, on the harmonic distortion and settling behavior of these SC stages. These effects, typically ignored in the behavioral simulations of SC stages, are analyzed and modeled. Thus, accurate behavioral simulations of DeltaSigma modulators or pipelined analog-to-digital converters (ADCs) can be performed in SIMULINK, using the proposed models for their SC building blocks (integrators or amplifiers). The proposed behavioral models are validated in HSPICE. Behavioral simulation examples are presented to illustrate the importance of such accurate modeling for low-power design
{"title":"Behavioral Modeling of Opamp Gain and Dynamic Effects for Power Optimization of Delta-Sigma Modulators and Pipelined ADCs","authors":"A. Hamoui, T. Alhajj, M. Taherzadeh‐Sani","doi":"10.1145/1165573.1165651","DOIUrl":"https://doi.org/10.1145/1165573.1165651","url":null,"abstract":"This paper proposes a simple, yet accurate, analytical model for the effect of opamp gain and dynamics (slew rate and bandwidth) on the transfer function of switched-capacitor (SC) amplifiers and integrators. Furthermore, it demonstrates the detrimental effects of: a) the nonlinear variation in the opamp dc gain; and b) the feedforward transmission of the feedback capacitor, on the harmonic distortion and settling behavior of these SC stages. These effects, typically ignored in the behavioral simulations of SC stages, are analyzed and modeled. Thus, accurate behavioral simulations of DeltaSigma modulators or pipelined analog-to-digital converters (ADCs) can be performed in SIMULINK, using the proposed models for their SC building blocks (integrators or amplifiers). The proposed behavioral models are validated in HSPICE. Behavioral simulation examples are presented to illustrate the importance of such accurate modeling for low-power design","PeriodicalId":119229,"journal":{"name":"ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131504523","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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