Each generation of semiconductor process technology enables increased levels of integration and density on a single chip, Moores Law continues to prevail and the users of portable and hand held communications and entertainment products enjoy greater functionality and features. Lifestyles and user paradigms indicate that no matter how many features are added, service providers and manufacturers think of more and users cannot wait to acquire the latest products. Features, performance, fashion and, of course, fierce competition, drive the market and thereby set the challenge for the semiconductor designer. The challenge for designers is to create systems on a single chip (SoC) to provide these features for the user and to enable service and content providers to realize new emerging market opportunities. This has been a challenge for many years but, now that nanometer process technologies form the enabling process technology, the design challenge is much greater. Nanometer design effects must be considered from the initial SoC architecture all the way through to manufacturing where design for manufacturing (DFM) effects must be overcome to enable reliable, high volume production. At the silicon level the features demanded by the users require extensive efforts to provide acceptable performance and reliability. Users of cell phones, PDAs and MP3 players will be most familiar with the need for long battery life while, to achieve this, the SoC designer worries about how to design with lower supply voltages, higher leakage currents, on chip power density and reliability. Packaging techniques which assemble multiple chips to form systems in package (SiP) also create signal integrity and power dissipation issues. At the same time designers must be able to design with EDA design tools and methodology's that are still emerging and where no standards for low power design exist today to make the task easier. This keynote will talk about the low power design techniques available to SoC designers, how they are implemented in SoCs and how they are implemented in existing and new designs. The talk will end with a view on the challenges coming up next and what needs to be done to prepare for them
{"title":"Low Power Design from Technology Challenge to Great Products","authors":"Barry Dennington","doi":"10.1145/1165573.1165625","DOIUrl":"https://doi.org/10.1145/1165573.1165625","url":null,"abstract":"Each generation of semiconductor process technology enables increased levels of integration and density on a single chip, Moores Law continues to prevail and the users of portable and hand held communications and entertainment products enjoy greater functionality and features. Lifestyles and user paradigms indicate that no matter how many features are added, service providers and manufacturers think of more and users cannot wait to acquire the latest products. Features, performance, fashion and, of course, fierce competition, drive the market and thereby set the challenge for the semiconductor designer. The challenge for designers is to create systems on a single chip (SoC) to provide these features for the user and to enable service and content providers to realize new emerging market opportunities. This has been a challenge for many years but, now that nanometer process technologies form the enabling process technology, the design challenge is much greater. Nanometer design effects must be considered from the initial SoC architecture all the way through to manufacturing where design for manufacturing (DFM) effects must be overcome to enable reliable, high volume production. At the silicon level the features demanded by the users require extensive efforts to provide acceptable performance and reliability. Users of cell phones, PDAs and MP3 players will be most familiar with the need for long battery life while, to achieve this, the SoC designer worries about how to design with lower supply voltages, higher leakage currents, on chip power density and reliability. Packaging techniques which assemble multiple chips to form systems in package (SiP) also create signal integrity and power dissipation issues. At the same time designers must be able to design with EDA design tools and methodology's that are still emerging and where no standards for low power design exist today to make the task easier. This keynote will talk about the low power design techniques available to SoC designers, how they are implemented in SoCs and how they are implemented in existing and new designs. The talk will end with a view on the challenges coming up next and what needs to be done to prepare for them","PeriodicalId":119229,"journal":{"name":"ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124962825","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Sub-threshold operation is a compelling approach for energy-constrained applications, but increased sensitivity to variation must be mitigated. We explore variability metrics and the variation sensitivity of stacked device topologies. We show that upsizing is necessary to achieve robustness at reduced voltages and propose a design methodology to meet yield constraints. The need for upsizing imposes an energy-overhead, influencing the optimal supply voltage to minimize energy. Finally, we characterize performance variability by summing delay distributions of each stage in an arbitrary critical path and achieve results accurate to within 10% of Monte Carlo simulation
{"title":"Variation-Driven Device Sizing for Minimum Energy Sub-threshold Circuits","authors":"Joyce Kwong, A. Chandrakasan","doi":"10.1145/1165573.1165578","DOIUrl":"https://doi.org/10.1145/1165573.1165578","url":null,"abstract":"Sub-threshold operation is a compelling approach for energy-constrained applications, but increased sensitivity to variation must be mitigated. We explore variability metrics and the variation sensitivity of stacked device topologies. We show that upsizing is necessary to achieve robustness at reduced voltages and propose a design methodology to meet yield constraints. The need for upsizing imposes an energy-overhead, influencing the optimal supply voltage to minimize energy. Finally, we characterize performance variability by summing delay distributions of each stage in an arbitrary critical path and achieve results accurate to within 10% of Monte Carlo simulation","PeriodicalId":119229,"journal":{"name":"ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131382330","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The paper discusses the design of the analog frontend of a passive UHF RFID tag, compatible with ISO/IEC 18000-6b standard. An efficient ESD-protected power retrieving circuit, based on the antenna features, a rectifier bridge and a charge pump, is introduced, as well as an auto-calibrated clock generator. The chip, implemented in a 0.18mum digital CMOS technology, does not need any post-fabrication trimming or external component besides the antenna; according to simulations, a correct communication is achieved at a distance of several meters between reader and tag
{"title":"A CMOS Analog Frontend for a Passive UHF RFID Tag","authors":"A. Facen, A. Boni","doi":"10.1145/1165573.1165640","DOIUrl":"https://doi.org/10.1145/1165573.1165640","url":null,"abstract":"The paper discusses the design of the analog frontend of a passive UHF RFID tag, compatible with ISO/IEC 18000-6b standard. An efficient ESD-protected power retrieving circuit, based on the antenna features, a rectifier bridge and a charge pump, is introduced, as well as an auto-calibrated clock generator. The chip, implemented in a 0.18mum digital CMOS technology, does not need any post-fabrication trimming or external component besides the antenna; according to simulations, a correct communication is achieved at a distance of several meters between reader and tag","PeriodicalId":119229,"journal":{"name":"ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130013521","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper proposes a power-efficient PWM DC/DC converter design with a novel zero voltage switching (ZVS) control technique. The ZVS control is realized by an inner feedback loop which is implemented by simple digital circuitry between the input and output of the power transistors and achieves real-time zero voltage switching (ZVS) for various loading and device parameters with power efficiencies over 90.0%. In addition, an outer feedback loop is used to ensure that the output precisely tracks a reference voltage level. We have also built the relationship between the output voltage ripple and the speed of the voltage comparators which has shown to introduce new low-frequency signals to the loops and cause significant output voltage ripples. Experiment results show that the output ripple could be reduced by 4times by carefully handling the generation and propagation of these low frequency signals
{"title":"Power-Efficient Pulse Width Modulation DC/DC Converters with Zero Voltage Switching Control","authors":"C. Long, S. Reddy, S. Pamarti, Lei He, T. Karnik","doi":"10.1145/1165573.1165650","DOIUrl":"https://doi.org/10.1145/1165573.1165650","url":null,"abstract":"This paper proposes a power-efficient PWM DC/DC converter design with a novel zero voltage switching (ZVS) control technique. The ZVS control is realized by an inner feedback loop which is implemented by simple digital circuitry between the input and output of the power transistors and achieves real-time zero voltage switching (ZVS) for various loading and device parameters with power efficiencies over 90.0%. In addition, an outer feedback loop is used to ensure that the output precisely tracks a reference voltage level. We have also built the relationship between the output voltage ripple and the speed of the voltage comparators which has shown to introduce new low-frequency signals to the loops and cause significant output voltage ripples. Experiment results show that the output ripple could be reduced by 4times by carefully handling the generation and propagation of these low frequency signals","PeriodicalId":119229,"journal":{"name":"ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130410913","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Process variations will increasingly impact the operational characteristics of integrated circuits in nanoscale semiconductor technologies. Researchers have proposed various design techniques to address process variations at the mask, circuit, and logic levels. However, as the magnitude of process variations increases, their effects will need to be addressed earlier in the design cycle. In this paper, we propose techniques for accurately and efficiently incorporating the effects of process variations into system-level power estimation tools. To motivate our work, we first study the impact of process variations on the power consumption of an example system-on-chip (SoC). We consider simple extensions of current approaches to system-level power estimation (spreadsheet-based and simulation-based power estimation), and demonstrate their limitations in performing variation-aware power estimation. We propose a system-level power estimation methodology that can accurately and efficiently analyze the impact of process variations on SoC power. The proposed methodology combines efficient trace-based analysis, power-state based leakage modeling, and Monte Carlo sampling. The key benefit of the proposed methodology is that it captures the necessary inter-dependencies while avoiding iterative system-level simulation. Our implementation of the proposed techniques within an in-house system-level power estimation framework indicates 2-5 orders of magnitude efficiency gains, with negligible loss in accuracy, compared to direct Monte Carlo techniques that require iterative system simulation
{"title":"Considering Process Variations During System-Level Power Analysis","authors":"Saumya Chandra, K. Lahiri, A. Raghunathan, S. Dey","doi":"10.1145/1165573.1165654","DOIUrl":"https://doi.org/10.1145/1165573.1165654","url":null,"abstract":"Process variations will increasingly impact the operational characteristics of integrated circuits in nanoscale semiconductor technologies. Researchers have proposed various design techniques to address process variations at the mask, circuit, and logic levels. However, as the magnitude of process variations increases, their effects will need to be addressed earlier in the design cycle. In this paper, we propose techniques for accurately and efficiently incorporating the effects of process variations into system-level power estimation tools. To motivate our work, we first study the impact of process variations on the power consumption of an example system-on-chip (SoC). We consider simple extensions of current approaches to system-level power estimation (spreadsheet-based and simulation-based power estimation), and demonstrate their limitations in performing variation-aware power estimation. We propose a system-level power estimation methodology that can accurately and efficiently analyze the impact of process variations on SoC power. The proposed methodology combines efficient trace-based analysis, power-state based leakage modeling, and Monte Carlo sampling. The key benefit of the proposed methodology is that it captures the necessary inter-dependencies while avoiding iterative system-level simulation. Our implementation of the proposed techniques within an in-house system-level power estimation framework indicates 2-5 orders of magnitude efficiency gains, with negligible loss in accuracy, compared to direct Monte Carlo techniques that require iterative system simulation","PeriodicalId":119229,"journal":{"name":"ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131778853","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
K. Bowman, J. Tschanz, M. Khellah, M. Ghoneima, Y. Ismail, V. De
Insertion of time-borrowing (TB) flip-flops in multi-cycle repeater-based on-chip interconnects enables significant improvements in mean performance and energy by averaging systematic and random within-die (WID) delay variations across multiple interconnect segments. A statistically-based analytical model is derived to design a TB N-cycle interconnects with optimal delay variation tolerance. The model elucidates the dependency of the transparency window required to achieve data delay averaging on the delay variation mismatch between interconnect segments. Statistical circuit simulations and analyses in a 65nm process technology demonstrate that TB multi-cycle interconnects enable a 4-6% mean maximum clock frequency (FMAX) improvement and a corresponding 10% average energy savings over optimally designed multi-cycle interconnects with conventional master-slave flip-flops. The maximum mean FMAX benefit ranges from 4.0-7.5%, corresponding to approximately a bin-split shift in the FMAX distribution. For 1.41X larger WID delay variations, the maximum mean FMAX gain rises to 5-10%
{"title":"Time-Borrowing Multi-Cycle On-Chip Interconnects for Delay Variation Tolerance","authors":"K. Bowman, J. Tschanz, M. Khellah, M. Ghoneima, Y. Ismail, V. De","doi":"10.1145/1165573.1165592","DOIUrl":"https://doi.org/10.1145/1165573.1165592","url":null,"abstract":"Insertion of time-borrowing (TB) flip-flops in multi-cycle repeater-based on-chip interconnects enables significant improvements in mean performance and energy by averaging systematic and random within-die (WID) delay variations across multiple interconnect segments. A statistically-based analytical model is derived to design a TB N-cycle interconnects with optimal delay variation tolerance. The model elucidates the dependency of the transparency window required to achieve data delay averaging on the delay variation mismatch between interconnect segments. Statistical circuit simulations and analyses in a 65nm process technology demonstrate that TB multi-cycle interconnects enable a 4-6% mean maximum clock frequency (FMAX) improvement and a corresponding 10% average energy savings over optimally designed multi-cycle interconnects with conventional master-slave flip-flops. The maximum mean FMAX benefit ranges from 4.0-7.5%, corresponding to approximately a bin-split shift in the FMAX distribution. For 1.41X larger WID delay variations, the maximum mean FMAX gain rises to 5-10%","PeriodicalId":119229,"journal":{"name":"ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130048603","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper describes a supercapacitor-operated, solar-powered wireless sensor node called Everlast. Unlike traditional wireless sensors that store energy in batteries, Everlast's use of supercapacitors enables the system to operate for an estimated lifetime of 20 years without any maintenance. The novelty of this system lies in the feedforward, PFM (pulse frequency modulated) converter and open-circuit solar voltage method for maximum power point tracking, enabling the solar cell to efficiently charge the supercapacitor and power the node. Experimental results show that Everlast can achieve low power consumption, long operational lifetime, and high transmission rates, something that traditional sensor nodes cannot achieve simultaneously and must trade-off
{"title":"Everlast: Long-life, Supercapacitor-operated Wireless Sensor Node","authors":"Farhan Simjee, Pai H. Chou","doi":"10.1145/1165573.1165619","DOIUrl":"https://doi.org/10.1145/1165573.1165619","url":null,"abstract":"This paper describes a supercapacitor-operated, solar-powered wireless sensor node called Everlast. Unlike traditional wireless sensors that store energy in batteries, Everlast's use of supercapacitors enables the system to operate for an estimated lifetime of 20 years without any maintenance. The novelty of this system lies in the feedforward, PFM (pulse frequency modulated) converter and open-circuit solar voltage method for maximum power point tracking, enabling the solar cell to efficiently charge the supercapacitor and power the node. Experimental results show that Everlast can achieve low power consumption, long operational lifetime, and high transmission rates, something that traditional sensor nodes cannot achieve simultaneously and must trade-off","PeriodicalId":119229,"journal":{"name":"ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design","volume":"279 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134344090","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Interprocessor synchronization, while extremely important for ensuring execution correctness, can be very costly in terms of both power and performance overheads. Unfortunately, many parallelizing compilers are very conservative in inserting barrier synchronizations at the end of each and every parallel loop. This can lead to significant power consumption in chip multiprocessor based execution environments. This paper proposes a compiler-directed approach for eliminating such synchronization calls between neighboring parallel loops. It achieves its goal by partitioning loop iterations across processors such that each processor executes iterations from both the loops that access the same set of array elements. We implemented the proposed approach using an experimental compilation framework and made experiments with ten SPEC benchmark codes. Our experiments clearly show that the proposed compiler-directed approach is very effective and reduces energy overheads due to synchronizations by about 75.5%, and this corresponds to around 5.48% saving on average in overall energy consumption
{"title":"Reducing Power through Compiler-Directed Barrier Synchronization Elimination","authors":"M. Kandemir, S. Son","doi":"10.1145/1165573.1165657","DOIUrl":"https://doi.org/10.1145/1165573.1165657","url":null,"abstract":"Interprocessor synchronization, while extremely important for ensuring execution correctness, can be very costly in terms of both power and performance overheads. Unfortunately, many parallelizing compilers are very conservative in inserting barrier synchronizations at the end of each and every parallel loop. This can lead to significant power consumption in chip multiprocessor based execution environments. This paper proposes a compiler-directed approach for eliminating such synchronization calls between neighboring parallel loops. It achieves its goal by partitioning loop iterations across processors such that each processor executes iterations from both the loops that access the same set of array elements. We implemented the proposed approach using an experimental compilation framework and made experiments with ten SPEC benchmark codes. Our experiments clearly show that the proposed compiler-directed approach is very effective and reduces energy overheads due to synchronizations by about 75.5%, and this corresponds to around 5.48% saving on average in overall energy consumption","PeriodicalId":119229,"journal":{"name":"ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115926419","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Summary form only given. System on chips (SoC) for mobile devices, such as GSM/EDGE/UMTS, have strongly conflicting requirements. On one hand the demand for processing performance is steadily increasing with every new standard and on the other hand extremely low power dissipation is demanded. The performance demands vary strongly, depending on the phone modes and activities e.g. stand-by mode vs. talk mode vs. high performance application modes such as video processing and gaming. Next to the development of new telecommunication standards the silicon technologies develop according to the shrink path. Scaling of physical structures, especially the gate thickness, induces larger leakage in DSM technologies. The shrink is accompanied with a further reduction of supply voltage that helps to reduce the dynamic power dissipation but also reduces the leverage of performance improvement. To reduce the leakage and to reach the targets of design projects new low power measures have to be defined and implemented by integration into technology, libraries, design tools, and the design flow. In recent years several low power features have been developed to address both the static leakage power consumption and the dynamic active power consumption. These features, or a combination of them, can be tailored to dynamically varying performance needs of the SoC in different modes meaning different use cases
{"title":"Design Challenges for Mobile Communication Devices","authors":"C. Kutter","doi":"10.1145/1165573.1165575","DOIUrl":"https://doi.org/10.1145/1165573.1165575","url":null,"abstract":"Summary form only given. System on chips (SoC) for mobile devices, such as GSM/EDGE/UMTS, have strongly conflicting requirements. On one hand the demand for processing performance is steadily increasing with every new standard and on the other hand extremely low power dissipation is demanded. The performance demands vary strongly, depending on the phone modes and activities e.g. stand-by mode vs. talk mode vs. high performance application modes such as video processing and gaming. Next to the development of new telecommunication standards the silicon technologies develop according to the shrink path. Scaling of physical structures, especially the gate thickness, induces larger leakage in DSM technologies. The shrink is accompanied with a further reduction of supply voltage that helps to reduce the dynamic power dissipation but also reduces the leverage of performance improvement. To reduce the leakage and to reach the targets of design projects new low power measures have to be defined and implemented by integration into technology, libraries, design tools, and the design flow. In recent years several low power features have been developed to address both the static leakage power consumption and the dynamic active power consumption. These features, or a combination of them, can be tailored to dynamically varying performance needs of the SoC in different modes meaning different use cases","PeriodicalId":119229,"journal":{"name":"ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115987683","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We propose a synergistic temperature and energy management scheme for GALS processors. Localized DVS is applied in domains that contain hotspots, permitting other critical domains to run unabated, thereby reducing performance cost relative to global DVS, and also creating execution slack in peripheral cooler domains that can be exploited to save energy. The reduction in energy in turn creates a steeper temperature gradient between the domains, permitting heat to flow more easily out of the hotspot domain. This symbiotic cyclical relationship between temperature and energy management leads to both significantly better performance, and lower energy, than the use of DTM alone
{"title":"Synergistic Temperature and Energy Management in GALS Processor Architectures","authors":"Yongkang Zhu, D. Albonesi","doi":"10.1145/1165573.1165587","DOIUrl":"https://doi.org/10.1145/1165573.1165587","url":null,"abstract":"We propose a synergistic temperature and energy management scheme for GALS processors. Localized DVS is applied in domains that contain hotspots, permitting other critical domains to run unabated, thereby reducing performance cost relative to global DVS, and also creating execution slack in peripheral cooler domains that can be exploited to save energy. The reduction in energy in turn creates a steeper temperature gradient between the domains, permitting heat to flow more easily out of the hotspot domain. This symbiotic cyclical relationship between temperature and energy management leads to both significantly better performance, and lower energy, than the use of DTM alone","PeriodicalId":119229,"journal":{"name":"ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126350416","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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