Computer-Aided Design (CAD) tools play an essential role in modern microelectronics. A comparison between two of the available CAD tool suites, OCTTOOLS and OASIS, is presented along with detailed description of their features and advantages. These tools utilize full-custom or the standard cells semi-custom approaches. This paper is intended to facilitate proper choice of the tools for best VLSIC designs. At the Microelectronics System Design Lab (MSDL), Oakland University, several VLSIC chips have been designed and implemented based on: the ease of transfer among the various hierarchical design levels of the OCTTOOLS and the efficient compaction available in OASIS. An example of a six-bit multiplier is presented to illustrate the design and implementation. The pros and limitations of each tool address: specification language, logic and switch level simulations, placement and routing, design verification and testability, as well as compaction.
{"title":"Pros and cons of public domain VLSIC design suites","authors":"H. Abdel-Aty-Zohdy","doi":"10.1109/MSE.1997.612522","DOIUrl":"https://doi.org/10.1109/MSE.1997.612522","url":null,"abstract":"Computer-Aided Design (CAD) tools play an essential role in modern microelectronics. A comparison between two of the available CAD tool suites, OCTTOOLS and OASIS, is presented along with detailed description of their features and advantages. These tools utilize full-custom or the standard cells semi-custom approaches. This paper is intended to facilitate proper choice of the tools for best VLSIC designs. At the Microelectronics System Design Lab (MSDL), Oakland University, several VLSIC chips have been designed and implemented based on: the ease of transfer among the various hierarchical design levels of the OCTTOOLS and the efficient compaction available in OASIS. An example of a six-bit multiplier is presented to illustrate the design and implementation. The pros and limitations of each tool address: specification language, logic and switch level simulations, placement and routing, design verification and testability, as well as compaction.","PeriodicalId":120048,"journal":{"name":"Proceedings of International Conference on Microelectronic Systems Education","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1997-07-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113977993","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A Microcomputer Applications in Construction course was developed to provide computer literacy for undergraduate construction students. The course topics and the results of construction industry computer literacy expectations research are presented. A critical issue was the question of the extent to which multimedia application development should be included in the course. It is recommended that there be continuous monitoring of computer courses and adaptation to change.
{"title":"Meeting the computer competency expectations of the construction industry","authors":"A. Wiezel, C. Schexnayder, K. Walsh","doi":"10.1109/MSE.1997.612538","DOIUrl":"https://doi.org/10.1109/MSE.1997.612538","url":null,"abstract":"A Microcomputer Applications in Construction course was developed to provide computer literacy for undergraduate construction students. The course topics and the results of construction industry computer literacy expectations research are presented. A critical issue was the question of the extent to which multimedia application development should be included in the course. It is recommended that there be continuous monitoring of computer courses and adaptation to change.","PeriodicalId":120048,"journal":{"name":"Proceedings of International Conference on Microelectronic Systems Education","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1997-07-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114093394","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper describes our experience with using Mentor Graphics electronic design automation software and Xilinx field programmable gate arrays at the introductory level. The Department of Electrical Engineering at the University of Missouri-Rolla has been a member of Mentor's Higher Education Program for almost ten years. We have been successfully introducing students to the tools by using a series of tutorial exercises in classroom, laboratory, and workshop settings. Until recently however our experience has been mainly with either upper level students including graduate students or with one or two sections of selected classes. Our use of field programmable gate arrays has been limited to upper level design courses. Beginning with the winter 1997 semester we decided to expand our offering and use both industrial strength design automation tools and field programmable gate arrays in all sections of a required introductory computer engineering laboratory.
{"title":"Industrial strength design automation tools in an introductory computer engineering laboratory","authors":"H. Pottinger","doi":"10.1109/MSE.1997.612568","DOIUrl":"https://doi.org/10.1109/MSE.1997.612568","url":null,"abstract":"This paper describes our experience with using Mentor Graphics electronic design automation software and Xilinx field programmable gate arrays at the introductory level. The Department of Electrical Engineering at the University of Missouri-Rolla has been a member of Mentor's Higher Education Program for almost ten years. We have been successfully introducing students to the tools by using a series of tutorial exercises in classroom, laboratory, and workshop settings. Until recently however our experience has been mainly with either upper level students including graduate students or with one or two sections of selected classes. Our use of field programmable gate arrays has been limited to upper level design courses. Beginning with the winter 1997 semester we decided to expand our offering and use both industrial strength design automation tools and field programmable gate arrays in all sections of a required introductory computer engineering laboratory.","PeriodicalId":120048,"journal":{"name":"Proceedings of International Conference on Microelectronic Systems Education","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1997-07-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114481834","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Educators continue to face pressure from students and industry to employ the newest technology in the classroom. With regard to VLSI design and the role of CAD tools, a balance must be struck between fundamentals and training to a particular software package. This paper describes a semester project, suitable for an undergraduate VLSI course, which emphasized the design process, rather than individual tools. This process and the experiences associated with producing a pipelined, two's complement binary multiplier are presented.
{"title":"An industrial-strength design flow in just fifteen easy weeks!","authors":"J. Frenzel","doi":"10.1109/MSE.1997.612544","DOIUrl":"https://doi.org/10.1109/MSE.1997.612544","url":null,"abstract":"Educators continue to face pressure from students and industry to employ the newest technology in the classroom. With regard to VLSI design and the role of CAD tools, a balance must be struck between fundamentals and training to a particular software package. This paper describes a semester project, suitable for an undergraduate VLSI course, which emphasized the design process, rather than individual tools. This process and the experiences associated with producing a pipelined, two's complement binary multiplier are presented.","PeriodicalId":120048,"journal":{"name":"Proceedings of International Conference on Microelectronic Systems Education","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1997-07-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127150804","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Jacomet, Roger Wälti, L. Winzenried, Jaime Perez, M. Gysel
The test bench methodology helps the design engineer to structure the simulation of his circuit. As showed in this paper, the test bench methodology can further be developed in, order to efficiently reuse simulation stimuli and response for the real device under test. As FPGAs are very often used to prototype an ASIC design, an easy switch between simulation and real hardware test is necessary to establish a rapid prototyping design and test environment. Our ProTest system closes the gap between the simulation and the test environment with a low cost and easy to use computer-aided-test environment.
{"title":"ProTest: a low cost rapid prototyping and test system for ASICs and FPGAs","authors":"M. Jacomet, Roger Wälti, L. Winzenried, Jaime Perez, M. Gysel","doi":"10.1109/MSE.1997.612547","DOIUrl":"https://doi.org/10.1109/MSE.1997.612547","url":null,"abstract":"The test bench methodology helps the design engineer to structure the simulation of his circuit. As showed in this paper, the test bench methodology can further be developed in, order to efficiently reuse simulation stimuli and response for the real device under test. As FPGAs are very often used to prototype an ASIC design, an easy switch between simulation and real hardware test is necessary to establish a rapid prototyping design and test environment. Our ProTest system closes the gap between the simulation and the test environment with a low cost and easy to use computer-aided-test environment.","PeriodicalId":120048,"journal":{"name":"Proceedings of International Conference on Microelectronic Systems Education","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1997-07-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129672798","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The goal of high assurance design is to correctly design, implement and verify an information processing system, from the component level to the system level. We are unable to build high assurance systems today because of our inability to cover the entire design process from specification to implementation with a high degree of certainty that errors or misinterpretations of the specification have not been introduced into the final product. While tremendous amounts of simulation and testing may produce an implementation that functions correctly for the test data, these systems often fail in the operational world. The US Air Force's Rome Laboratory and DARPA's Information Technology Office, (ITO), is establishing the 21st Century Engineering Consortium. The reason for establishing the consortium is to develop the engineering capability necessary to build highly assured systems. In short, Rome Laboratory and DARPA's ITO would like to see a larger number of students trained in engineering based upon formal methods, e.g. hardware verification (VHDL models), software verification (Ada, C, C++ code), requirements/specification analysis, as well as applying this technology to other problem domains.
{"title":"The 21st Century Engineering Consortium","authors":"M. P. Nassif","doi":"10.1109/MSE.1997.612550","DOIUrl":"https://doi.org/10.1109/MSE.1997.612550","url":null,"abstract":"The goal of high assurance design is to correctly design, implement and verify an information processing system, from the component level to the system level. We are unable to build high assurance systems today because of our inability to cover the entire design process from specification to implementation with a high degree of certainty that errors or misinterpretations of the specification have not been introduced into the final product. While tremendous amounts of simulation and testing may produce an implementation that functions correctly for the test data, these systems often fail in the operational world. The US Air Force's Rome Laboratory and DARPA's Information Technology Office, (ITO), is establishing the 21st Century Engineering Consortium. The reason for establishing the consortium is to develop the engineering capability necessary to build highly assured systems. In short, Rome Laboratory and DARPA's ITO would like to see a larger number of students trained in engineering based upon formal methods, e.g. hardware verification (VHDL models), software verification (Ada, C, C++ code), requirements/specification analysis, as well as applying this technology to other problem domains.","PeriodicalId":120048,"journal":{"name":"Proceedings of International Conference on Microelectronic Systems Education","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1997-07-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123141438","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Cache memory design in embedded systems can take advantage from the analysis of the software that runs on that system, which usually remains the same for its whole life. Programs can be characterized, in respect of the memory hierarchy, using locality analysis. We propose an environment which permits one to analyze the locality of a program and the effects on the target system performance. The student can thus figure out the best tradeoff between costs and performance for cache memory and timings, exploring different system configurations. A fully graphical interface permits one to observe the program behavior from many points of view: locality surface, working set evolution, and performance metrics. The tool is currently used as a teaching tool at our University and it is distributed as part of a commercial development environment for embedded systems.
{"title":"Cache memory design for embedded systems based on program locality analysis","authors":"R. Giorgi, C. Prete, G. Prina","doi":"10.1109/MSE.1997.612528","DOIUrl":"https://doi.org/10.1109/MSE.1997.612528","url":null,"abstract":"Cache memory design in embedded systems can take advantage from the analysis of the software that runs on that system, which usually remains the same for its whole life. Programs can be characterized, in respect of the memory hierarchy, using locality analysis. We propose an environment which permits one to analyze the locality of a program and the effects on the target system performance. The student can thus figure out the best tradeoff between costs and performance for cache memory and timings, exploring different system configurations. A fully graphical interface permits one to observe the program behavior from many points of view: locality surface, working set evolution, and performance metrics. The tool is currently used as a teaching tool at our University and it is distributed as part of a commercial development environment for embedded systems.","PeriodicalId":120048,"journal":{"name":"Proceedings of International Conference on Microelectronic Systems Education","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1997-07-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126917366","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Modern embedded system designs include elements described using schematics, hardware description languages, timing diagrams, and various programming languages. We have developed a set of Java applets that facilitate the documentation of designs for dissemination over the Web. These tools enable the specification of multiple layers of active regions on diagrams and on text so that different mouse-over comments and/or hyper-text links can be attached to elements on each layer. This layering supports multiple hierarchical views of the same design. The tools, thus provide a highly expressive and modular system for navigating design documentation. These same tools can be used to provide a medium for delivering comments on students' work. We would expect such functionality to eventually be directly supported by EDA tool vendors.
{"title":"Tools for documenting digital designs on the Web","authors":"G. Borriello, Douglas Beal, Tianyu Li","doi":"10.1109/MSE.1997.612524","DOIUrl":"https://doi.org/10.1109/MSE.1997.612524","url":null,"abstract":"Modern embedded system designs include elements described using schematics, hardware description languages, timing diagrams, and various programming languages. We have developed a set of Java applets that facilitate the documentation of designs for dissemination over the Web. These tools enable the specification of multiple layers of active regions on diagrams and on text so that different mouse-over comments and/or hyper-text links can be attached to elements on each layer. This layering supports multiple hierarchical views of the same design. The tools, thus provide a highly expressive and modular system for navigating design documentation. These same tools can be used to provide a medium for delivering comments on students' work. We would expect such functionality to eventually be directly supported by EDA tool vendors.","PeriodicalId":120048,"journal":{"name":"Proceedings of International Conference on Microelectronic Systems Education","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1997-07-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115821972","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
At South Dakota State University (SDSU), resources are scarce and student enrollment is limited. However, interested faculty and eager to learn students made VLSI education at SDSU a reality. The implementation of the VLSI education program, that started in 1994, is presented in this paper. Factors such as meeting needs and expectations of Industry, limited capabilities, and increasing constraints of the University are also discussed.
{"title":"Implementation of the VLSI education program at South Dakota State University","authors":"M. Andrawis","doi":"10.1109/MSE.1997.612573","DOIUrl":"https://doi.org/10.1109/MSE.1997.612573","url":null,"abstract":"At South Dakota State University (SDSU), resources are scarce and student enrollment is limited. However, interested faculty and eager to learn students made VLSI education at SDSU a reality. The implementation of the VLSI education program, that started in 1994, is presented in this paper. Factors such as meeting needs and expectations of Industry, limited capabilities, and increasing constraints of the University are also discussed.","PeriodicalId":120048,"journal":{"name":"Proceedings of International Conference on Microelectronic Systems Education","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1997-07-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116660039","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
"Logic and Digital Design" is an introductory level course for electrical engineering students at the Department of Electrical Engineering, University of Wisconsin-Platteville. This paper describes the development of using design automation tools in the course. Since Fall 1993, a realistic design environment has been created. Through laboratory work and a comprehensive final project, not only students have learned fundamental knowledge of the logic and digital design, but also they have used the extensive facilities in the laboratory to undertake the design and integration of state machine. In the course, several tools have been introduced gradually, which include schematic capture tools (OrCAD, MAX+PLUS II), simulation tool (SYNOPSYS, MAX+PLUS II) hardware design language and synthesis (AHDL, Programmer). At the end of the course, each student is required to design, test and implement and demonstrate his/her own state machine using CPLD devices (ALTERA). This paper also describes the accomplishments of the student projects during the academic year of 1996.
{"title":"Experiences teaching design automation in the introductory level course","authors":"Yong Y. Li","doi":"10.1109/MSE.1997.612549","DOIUrl":"https://doi.org/10.1109/MSE.1997.612549","url":null,"abstract":"\"Logic and Digital Design\" is an introductory level course for electrical engineering students at the Department of Electrical Engineering, University of Wisconsin-Platteville. This paper describes the development of using design automation tools in the course. Since Fall 1993, a realistic design environment has been created. Through laboratory work and a comprehensive final project, not only students have learned fundamental knowledge of the logic and digital design, but also they have used the extensive facilities in the laboratory to undertake the design and integration of state machine. In the course, several tools have been introduced gradually, which include schematic capture tools (OrCAD, MAX+PLUS II), simulation tool (SYNOPSYS, MAX+PLUS II) hardware design language and synthesis (AHDL, Programmer). At the end of the course, each student is required to design, test and implement and demonstrate his/her own state machine using CPLD devices (ALTERA). This paper also describes the accomplishments of the student projects during the academic year of 1996.","PeriodicalId":120048,"journal":{"name":"Proceedings of International Conference on Microelectronic Systems Education","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1997-07-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125571354","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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