Pub Date : 2022-06-08DOI: 10.1109/mocast54814.2022.9837752
E. Kavvousanos, Vassilis Paliouras
Recently, Machine Learning has been considered as an alternative design paradigm for various communications sub-systems. However, the works that have assessed the performance of these methods beyond the algorithmic level are limited. In this paper, we implement in hardware and evaluate the performance of the Syndrome-based Deep Learning Decoder for a BCH(63,45) code in terms of throughput rate and latency. The implemented Neural Network is compressed by applying pruning, clustering and quantization to an 8-bit fixed-point representation, with no significant loss in its BER performance, while achieving 90% weight sparsity in each layer. An FPGA architecture is designed for the decoder which exploits the compressed structure of the Neural Network in order to accelerate the underlying computations with moderate hardware requirements. Experimental results are provided which show that the decoder achieves latency less than a tenth of a millisecond and a throughput rate up to 5 Mbps, substantially outperforming previous implementations by 30×.
{"title":"A Low-Latency Syndrome-based Deep Learning Decoder Architecture and its FPGA Implementation","authors":"E. Kavvousanos, Vassilis Paliouras","doi":"10.1109/mocast54814.2022.9837752","DOIUrl":"https://doi.org/10.1109/mocast54814.2022.9837752","url":null,"abstract":"Recently, Machine Learning has been considered as an alternative design paradigm for various communications sub-systems. However, the works that have assessed the performance of these methods beyond the algorithmic level are limited. In this paper, we implement in hardware and evaluate the performance of the Syndrome-based Deep Learning Decoder for a BCH(63,45) code in terms of throughput rate and latency. The implemented Neural Network is compressed by applying pruning, clustering and quantization to an 8-bit fixed-point representation, with no significant loss in its BER performance, while achieving 90% weight sparsity in each layer. An FPGA architecture is designed for the decoder which exploits the compressed structure of the Neural Network in order to accelerate the underlying computations with moderate hardware requirements. Experimental results are provided which show that the decoder achieves latency less than a tenth of a millisecond and a throughput rate up to 5 Mbps, substantially outperforming previous implementations by 30×.","PeriodicalId":122414,"journal":{"name":"2022 11th International Conference on Modern Circuits and Systems Technologies (MOCAST)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121901535","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-08DOI: 10.1109/mocast54814.2022.9837615
D. Samaras, A. Hatzopoulos
This work presents a Charge Pump circuit using active current mismatch compensation, which exhibits low power, low noise and good linearity for integer or fractional -N PLL. The proposed charge pump has a Vctrl range of 0.3V to 0.75V, 1.135 × 10-24 A2/Hz output current noise and current mismatch below 0.01%. Additionally, it includes a smoothing capacitor to reduce the transient phenomena which generate non-linearity. The layout dimensions of the proposed charge pump is 88um x 80um. Finally, the charge pump is designed using 65nm TSMC process with a supply voltage of 1V and power consumption of 309uW at 150uA current output.
本文提出了一种采用有源电流失配补偿的电荷泵电路，该电路具有低功耗、低噪声和良好的线性性，适用于整数或分数n锁相环。所提出的电荷泵的电压控制范围为0.3V至0.75V，输出电流噪声为1.135 × 10-24 A2/Hz，电流失配低于0.01%。此外，它还包括一个平滑电容器，以减少产生非线性的瞬态现象。所建议的电荷泵的布局尺寸为88um x 80um。最后，采用65nm TSMC工艺设计了充电泵，电源电压为1V，输出150uA电流时功耗为309w。
{"title":"A low power low noise 65nm charge pump using mismatch compensation and smoothing capacitor","authors":"D. Samaras, A. Hatzopoulos","doi":"10.1109/mocast54814.2022.9837615","DOIUrl":"https://doi.org/10.1109/mocast54814.2022.9837615","url":null,"abstract":"This work presents a Charge Pump circuit using active current mismatch compensation, which exhibits low power, low noise and good linearity for integer or fractional -N PLL. The proposed charge pump has a Vctrl range of 0.3V to 0.75V, 1.135 × 10-24 A2/Hz output current noise and current mismatch below 0.01%. Additionally, it includes a smoothing capacitor to reduce the transient phenomena which generate non-linearity. The layout dimensions of the proposed charge pump is 88um x 80um. Finally, the charge pump is designed using 65nm TSMC process with a supply voltage of 1V and power consumption of 309uW at 150uA current output.","PeriodicalId":122414,"journal":{"name":"2022 11th International Conference on Modern Circuits and Systems Technologies (MOCAST)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133141325","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-26DOI: 10.48550/arXiv.2205.13559
Batel Oved, Orian Leitersdorf, R. Ronen, Shahar Kvatinsky
Recent research has sought to accelerate cryptographic hash functions as they are at the core of modern cryptography. Traditional designs, however, suffer from the von Neumann bottleneck that originates from the separation of processing and memory units. An emerging solution to overcome this bottleneck is processing-in-memory (PIM): performing logic within the same devices responsible for memory to eliminate data-transfer and simultaneously provide massive computational parallelism. In this paper, we seek to vastly accelerate the state-of-the-art SHA-3 cryptographic function using the memristive memory processing unit (mMPU), a general-purpose memristive PIM architecture. To that end, we propose a novel in-memory algorithm for variable rotation, and utilize an efficient mapping of the SHA-3 state vector for memristive crossbar arrays to efficiently exploit PIM parallelism. We demonstrate a massive energy efficiency of 1, 422 Gbps/W, improving a state-of-the-art memristive SHA-3 accelerator (SHINE-2) by 4.6 ×.
{"title":"HashPIM: High-Throughput SHA-3 via Memristive Digital Processing-in-Memory","authors":"Batel Oved, Orian Leitersdorf, R. Ronen, Shahar Kvatinsky","doi":"10.48550/arXiv.2205.13559","DOIUrl":"https://doi.org/10.48550/arXiv.2205.13559","url":null,"abstract":"Recent research has sought to accelerate cryptographic hash functions as they are at the core of modern cryptography. Traditional designs, however, suffer from the von Neumann bottleneck that originates from the separation of processing and memory units. An emerging solution to overcome this bottleneck is processing-in-memory (PIM): performing logic within the same devices responsible for memory to eliminate data-transfer and simultaneously provide massive computational parallelism. In this paper, we seek to vastly accelerate the state-of-the-art SHA-3 cryptographic function using the memristive memory processing unit (mMPU), a general-purpose memristive PIM architecture. To that end, we propose a novel in-memory algorithm for variable rotation, and utilize an efficient mapping of the SHA-3 state vector for memristive crossbar arrays to efficiently exploit PIM parallelism. We demonstrate a massive energy efficiency of 1, 422 Gbps/W, improving a state-of-the-art memristive SHA-3 accelerator (SHINE-2) by 4.6 ×.","PeriodicalId":122414,"journal":{"name":"2022 11th International Conference on Modern Circuits and Systems Technologies (MOCAST)","volume":"26 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132193337","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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