Pub Date : 2016-10-01DOI: 10.1109/ISPACS.2016.7824754
Thanat Nonthaputha, M. Kumngern, S. Lerkvaranyu
This paper presents a new CMOS sample-and-hold (S/H) circuit employing one second-generation current conveyor (CCII), one resistor and one capacitor. Unlike, conventional S/H circuits, the proposed S/H circuit is absent from MOS switches. The proposed S/H circuit uses CCII to work as analog switch (CCAS) which high speed on-off status of switch and without buffer circuit can be obtained. The status on-off of switch is controlled by bias current. This bias current is sampling pulse that used for sampling input signal. The proposed S/H circuit is suitable for low-power and high accuracy for signal processing applications. The simulation results are used to confirm the workability of the proposed circuit.
{"title":"CMOS sample-and-hold circuit using current conveyor analogue switch","authors":"Thanat Nonthaputha, M. Kumngern, S. Lerkvaranyu","doi":"10.1109/ISPACS.2016.7824754","DOIUrl":"https://doi.org/10.1109/ISPACS.2016.7824754","url":null,"abstract":"This paper presents a new CMOS sample-and-hold (S/H) circuit employing one second-generation current conveyor (CCII), one resistor and one capacitor. Unlike, conventional S/H circuits, the proposed S/H circuit is absent from MOS switches. The proposed S/H circuit uses CCII to work as analog switch (CCAS) which high speed on-off status of switch and without buffer circuit can be obtained. The status on-off of switch is controlled by bias current. This bias current is sampling pulse that used for sampling input signal. The proposed S/H circuit is suitable for low-power and high accuracy for signal processing applications. The simulation results are used to confirm the workability of the proposed circuit.","PeriodicalId":131543,"journal":{"name":"2016 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130865814","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/ISPACS.2016.7824732
Qian Li, Xin Jin, Zhanqi Liu, Qionghai Dai
In this paper, a dynamic offloading model together with a cloud-friendly depth estimation algorithm is proposed to minimize the energy consumption of mobile devices by exploiting cloud computational resources for 2D-to-3D conversion. The cloud-friendly depth estimation algorithm partitions an input image into several parts, classifies each part to a specific type, and applies a specific conversion algorithm to each type to generate depth maps, which facilitates allocating the partitions between the mobile device and the cloud dynamically. Then, a dynamic offloading model is proposed for mobile energy minimization by allocating the partitions to be processed dynamically between the cloud and the mobile. The complexity of depth estimation, the processing capability of the cloud, and the power consumption of the mobile are considered jointly into the model to provide an optimized solution. Several simulations based on parameters of real mobile devices demonstrate that our method can save an average of almost 21.17% of total energy on different mobile devices and an average of 17.09% of total energy under different transmitting rates than the existing algorithms for 2D-to-3D conversion.
{"title":"Dynamic cloud offloading for 2D-to-3D conversion","authors":"Qian Li, Xin Jin, Zhanqi Liu, Qionghai Dai","doi":"10.1109/ISPACS.2016.7824732","DOIUrl":"https://doi.org/10.1109/ISPACS.2016.7824732","url":null,"abstract":"In this paper, a dynamic offloading model together with a cloud-friendly depth estimation algorithm is proposed to minimize the energy consumption of mobile devices by exploiting cloud computational resources for 2D-to-3D conversion. The cloud-friendly depth estimation algorithm partitions an input image into several parts, classifies each part to a specific type, and applies a specific conversion algorithm to each type to generate depth maps, which facilitates allocating the partitions between the mobile device and the cloud dynamically. Then, a dynamic offloading model is proposed for mobile energy minimization by allocating the partitions to be processed dynamically between the cloud and the mobile. The complexity of depth estimation, the processing capability of the cloud, and the power consumption of the mobile are considered jointly into the model to provide an optimized solution. Several simulations based on parameters of real mobile devices demonstrate that our method can save an average of almost 21.17% of total energy on different mobile devices and an average of 17.09% of total energy under different transmitting rates than the existing algorithms for 2D-to-3D conversion.","PeriodicalId":131543,"journal":{"name":"2016 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129993621","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/ISPACS.2016.7824722
Koken Chin, H. San, Atsushi Kitajima, Y. Arai, Jun Yamashita, Hisashi Ito
This paper presents an input bias current reduction technique for CMOS operational amplifier (op-amp) with electrostatic discharge (ESD) protection circuit. In a high input impedance CMOS op-amp, the leakage current of electrostatic discharge protection circuit causes a non-ideality error of input bias current. Especially, the leakage current increases drastically at high operating temperature. Proposed input bias current cancellation technique uses an additional op-amp and the replicas of ESD protection diodes to compensate the leakage current of ESD to reduce the input current of op-amp. SPICE simulation results verify the leakage current reduction effectiveness of proposed technique, and the input current of amplifier decreased to less than 1pA at 150 degrees in 0.7um standard CMOS technology without any extra options.
{"title":"Leakage current compensation technique of ESD protection circuit for CMOS operational amplifier","authors":"Koken Chin, H. San, Atsushi Kitajima, Y. Arai, Jun Yamashita, Hisashi Ito","doi":"10.1109/ISPACS.2016.7824722","DOIUrl":"https://doi.org/10.1109/ISPACS.2016.7824722","url":null,"abstract":"This paper presents an input bias current reduction technique for CMOS operational amplifier (op-amp) with electrostatic discharge (ESD) protection circuit. In a high input impedance CMOS op-amp, the leakage current of electrostatic discharge protection circuit causes a non-ideality error of input bias current. Especially, the leakage current increases drastically at high operating temperature. Proposed input bias current cancellation technique uses an additional op-amp and the replicas of ESD protection diodes to compensate the leakage current of ESD to reduce the input current of op-amp. SPICE simulation results verify the leakage current reduction effectiveness of proposed technique, and the input current of amplifier decreased to less than 1pA at 150 degrees in 0.7um standard CMOS technology without any extra options.","PeriodicalId":131543,"journal":{"name":"2016 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124782304","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/ISPACS.2016.7824703
D. Kumar, M. Kumar
This paper reports a new design of low power two bit magnitude comparator with adiabatic logic in 0.18µm CMOS technology. The proposed design shows the improvement in power delay product (PDP) of 66.76% to 82.97% with varying power supply for 1.1V to 2.0V as compared to conventional design. PDP of proposed design shows an improvement of 73.98% to 81.15 % with temperature varying from 50°C to 10°C as compared to conventional design. Results show a significant improvement in terms of PDP for proposed design as compared to existing conventional designs.
{"title":"Design of low power two bit magnitude comparator using adiabatic logic","authors":"D. Kumar, M. Kumar","doi":"10.1109/ISPACS.2016.7824703","DOIUrl":"https://doi.org/10.1109/ISPACS.2016.7824703","url":null,"abstract":"This paper reports a new design of low power two bit magnitude comparator with adiabatic logic in 0.18µm CMOS technology. The proposed design shows the improvement in power delay product (PDP) of 66.76% to 82.97% with varying power supply for 1.1V to 2.0V as compared to conventional design. PDP of proposed design shows an improvement of 73.98% to 81.15 % with temperature varying from 50°C to 10°C as compared to conventional design. Results show a significant improvement in terms of PDP for proposed design as compared to existing conventional designs.","PeriodicalId":131543,"journal":{"name":"2016 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133417907","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/ISPACS.2016.7824675
T. Adiono, Radhian Ferel Armansyah, Fadhli Dzil Ikram, Swizya Satira Nolika, Rachmad Vidya Wicaksana Putra, A. H. Salman
In this paper, we present a VLSI design of human detection using Sum of Absolute Difference (SAD) based parallel morphological template matching method. Its research targets are to achieve small area consumption yet with fast computation. The architecture is designed to process original and its template images with resolution of 640×480 and 40×100 pixels respectively. Here, we propose two techniques, a rolling-index architecture for SAD computation and an optimized binary tree adder. For every calculation window, the difference between source and template is calculated in parallel processing. Hence, the SAD calculation computes 40×100 pixels per clock cycle. The proposed design is coded using Verilog HDL and implemented in Altera Cyclone II FPGA. The full processing time needs 307,200 clock cycles. Each image frame needs 6.144 ms and the frame speed reaches 162 frame-per-second (fps) for video application. This proposed design only consumes 16,689 logic elements, comprising 12,732 combinational functions and 4,460 dedicated logic registers.
在本文中，我们提出了一种基于绝对差和(SAD)并行形态学模板匹配方法的人体检测VLSI设计。它的研究目标是实现小面积消耗和快速计算。该架构设计用于处理原始图像和模板图像，分辨率分别为640×480和40×100像素。在这里，我们提出了两种技术，一种用于SAD计算的滚动索引架构和一种优化的二叉树加法器。对于每个计算窗口，在并行处理中计算源和模板的差值。因此，SAD计算每个时钟周期计算40×100像素。该设计采用Verilog HDL进行编码，并在Altera Cyclone II FPGA上实现。整个处理时间需要307,200个时钟周期。每帧图像需要6.144 ms，帧速度达到每秒162帧(fps)。该设计仅消耗16,689个逻辑元件，包括12,732个组合函数和4,460个专用逻辑寄存器。
{"title":"Parallel morphological template matching design for efficient human detection application","authors":"T. Adiono, Radhian Ferel Armansyah, Fadhli Dzil Ikram, Swizya Satira Nolika, Rachmad Vidya Wicaksana Putra, A. H. Salman","doi":"10.1109/ISPACS.2016.7824675","DOIUrl":"https://doi.org/10.1109/ISPACS.2016.7824675","url":null,"abstract":"In this paper, we present a VLSI design of human detection using Sum of Absolute Difference (SAD) based parallel morphological template matching method. Its research targets are to achieve small area consumption yet with fast computation. The architecture is designed to process original and its template images with resolution of 640×480 and 40×100 pixels respectively. Here, we propose two techniques, a rolling-index architecture for SAD computation and an optimized binary tree adder. For every calculation window, the difference between source and template is calculated in parallel processing. Hence, the SAD calculation computes 40×100 pixels per clock cycle. The proposed design is coded using Verilog HDL and implemented in Altera Cyclone II FPGA. The full processing time needs 307,200 clock cycles. Each image frame needs 6.144 ms and the frame speed reaches 162 frame-per-second (fps) for video application. This proposed design only consumes 16,689 logic elements, comprising 12,732 combinational functions and 4,460 dedicated logic registers.","PeriodicalId":131543,"journal":{"name":"2016 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124858045","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/ISPACS.2016.7824681
Tushar Supe, David V. Anderson
This paper proposes an optimized and generalized Co-ordinate Rotation Digital Computer (CORDIC) algorithm in the rotation mode of the circular co-ordinate system. It computes the values of trigonometric functions and can be configured to provide the result with a lower overall latency than existing systems. This is done by using redundant representations and approximations of the required direction and angle of each rotation. The algorithm has been designed to provide the result in a fixed number of iterations equal to a design parameter as chosen by the designer. In each iteration, the algorithm performs rotations between zero and a certain number, in parallel. A technique to handle the scaling factor compensation for such an algorithm is also proposed. The results of the functional verification for different values of the design parameter and an estimation of the overall latency are presented.
{"title":"Super-CORDIC: An approximation based parallel and redundant CORDIC algorithm","authors":"Tushar Supe, David V. Anderson","doi":"10.1109/ISPACS.2016.7824681","DOIUrl":"https://doi.org/10.1109/ISPACS.2016.7824681","url":null,"abstract":"This paper proposes an optimized and generalized Co-ordinate Rotation Digital Computer (CORDIC) algorithm in the rotation mode of the circular co-ordinate system. It computes the values of trigonometric functions and can be configured to provide the result with a lower overall latency than existing systems. This is done by using redundant representations and approximations of the required direction and angle of each rotation. The algorithm has been designed to provide the result in a fixed number of iterations equal to a design parameter as chosen by the designer. In each iteration, the algorithm performs rotations between zero and a certain number, in parallel. A technique to handle the scaling factor compensation for such an algorithm is also proposed. The results of the functional verification for different values of the design parameter and an estimation of the overall latency are presented.","PeriodicalId":131543,"journal":{"name":"2016 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS)","volume":"45 6","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120839685","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/ISPACS.2016.7824743
T. Harada, K. Kaiwa
In this paper, we design, fabricate, and evaluate octagonal nMOSFET multi operation device for normal MOSFET operation, detection of 8 stress direction, and variation of temperatures. In previous works, one sensor device can detect only one physical or chemical phenomenon. If we get some sensing data, such as temperature, stress, and etc., more than two sensor devices must be implemented. According to stress detection, stress sensors reattach along stress direction for measurement, because most of the previous stress sensors can sense only one dimension. However, octagonal MOSFET is not necessary to adjust because this device has radial eight direction output terminals and can accommodate various sensing using these terminals. Furthermore, this device can also measure the variation of threshold voltage using these output terminals. For example, proposed device can get variety of temperatures due to the temperature characteristics of threshold voltage. As the results, we can realize that it can sense 8 stress directions and a variety of temperature.
{"title":"Stress direction and temperature detectable octagonal nMOSFET multi operation device","authors":"T. Harada, K. Kaiwa","doi":"10.1109/ISPACS.2016.7824743","DOIUrl":"https://doi.org/10.1109/ISPACS.2016.7824743","url":null,"abstract":"In this paper, we design, fabricate, and evaluate octagonal nMOSFET multi operation device for normal MOSFET operation, detection of 8 stress direction, and variation of temperatures. In previous works, one sensor device can detect only one physical or chemical phenomenon. If we get some sensing data, such as temperature, stress, and etc., more than two sensor devices must be implemented. According to stress detection, stress sensors reattach along stress direction for measurement, because most of the previous stress sensors can sense only one dimension. However, octagonal MOSFET is not necessary to adjust because this device has radial eight direction output terminals and can accommodate various sensing using these terminals. Furthermore, this device can also measure the variation of threshold voltage using these output terminals. For example, proposed device can get variety of temperatures due to the temperature characteristics of threshold voltage. As the results, we can realize that it can sense 8 stress directions and a variety of temperature.","PeriodicalId":131543,"journal":{"name":"2016 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS)","volume":" 8","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120828330","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/ISPACS.2016.7824741
Thitinan Kliangsuwan, A. Heednacram
In this paper, a local cloud monitoring station equipped with a fisheye lens camera is proposed and installed at Prince of Songkla University (PSU), Phuket. The station retrieves cloud images in conjunction with several meteorological sensors. The methodology and cloud classifier algorithm is proposed. The performance test using images captured from our cloud monitoring station shows that the cloud classification accuracy in practice is as high as 98.58%. The installed cloud monitoring system can report live cloud conditions and display them on a mobile application. Our complete system is inexpensive and suitable for local use of weather monitoring and alerting.
{"title":"A low-cost local cloud monitoring system","authors":"Thitinan Kliangsuwan, A. Heednacram","doi":"10.1109/ISPACS.2016.7824741","DOIUrl":"https://doi.org/10.1109/ISPACS.2016.7824741","url":null,"abstract":"In this paper, a local cloud monitoring station equipped with a fisheye lens camera is proposed and installed at Prince of Songkla University (PSU), Phuket. The station retrieves cloud images in conjunction with several meteorological sensors. The methodology and cloud classifier algorithm is proposed. The performance test using images captured from our cloud monitoring station shows that the cloud classification accuracy in practice is as high as 98.58%. The installed cloud monitoring system can report live cloud conditions and display them on a mobile application. Our complete system is inexpensive and suitable for local use of weather monitoring and alerting.","PeriodicalId":131543,"journal":{"name":"2016 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122203060","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/ISPACS.2016.7824760
T. Nakachi, T. Fujii
This paper introduces a rate-adaptive FireFort-LDGM (FF-LDGM) code for MMT adaptive Application Layer FEC (AL-FEC). The FF-LDGM code is an ISO/IEC MPEG international standard issued in Feb. 2015. It can handle a wade range of block lengths from a small number of packets to several thousands of packets. Especially, it is useful for real-time UHD video transmission. In this paper, we focus on recent advances in the rate adaptive FF-LDGM code. It provides a rate adaptive function that allows the coding rate to be adaptively changed to suit the network characteristic. We improve the error recovery performance of the rate-adaptive scheme by using selective interleaving. Simulation results demonstrate its superior adaptive performance.
{"title":"Rate-adaptive FF-LDGM code with selective inter-leaving scheme","authors":"T. Nakachi, T. Fujii","doi":"10.1109/ISPACS.2016.7824760","DOIUrl":"https://doi.org/10.1109/ISPACS.2016.7824760","url":null,"abstract":"This paper introduces a rate-adaptive FireFort-LDGM (FF-LDGM) code for MMT adaptive Application Layer FEC (AL-FEC). The FF-LDGM code is an ISO/IEC MPEG international standard issued in Feb. 2015. It can handle a wade range of block lengths from a small number of packets to several thousands of packets. Especially, it is useful for real-time UHD video transmission. In this paper, we focus on recent advances in the rate adaptive FF-LDGM code. It provides a rate adaptive function that allows the coding rate to be adaptively changed to suit the network characteristic. We improve the error recovery performance of the rate-adaptive scheme by using selective interleaving. Simulation results demonstrate its superior adaptive performance.","PeriodicalId":131543,"journal":{"name":"2016 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS)","volume":"43 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128532937","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/ISPACS.2016.7824740
Tatsumi Uwai, Takuma Miyamoto, Y. Nagao, L. Lanante, M. Kurosaki, H. Ochi
Random access Orthogonal Frequency Division Multiple Access (OFDMA), a method for uplink multi-user transmission (UL-MU) for STAs with unknown transmit buffer has been adopted in the upcoming IEEE802.11ax next generation wireless LAN standard. In this paper, we propose a performance analysis model which use bidimensional Markov chain model of OFDMA random access. Via computer simulation, we show the usefulness of the proposed method even in the case of dense environment. In addition, we present a method in calculating the optimal number of resource units, which in 802.11ax refer to a subset of subcarriers to assign the user for OFDMA random access from numerical results.
{"title":"Performance evaluation of OFDMA random access in IEEE802.11ax","authors":"Tatsumi Uwai, Takuma Miyamoto, Y. Nagao, L. Lanante, M. Kurosaki, H. Ochi","doi":"10.1109/ISPACS.2016.7824740","DOIUrl":"https://doi.org/10.1109/ISPACS.2016.7824740","url":null,"abstract":"Random access Orthogonal Frequency Division Multiple Access (OFDMA), a method for uplink multi-user transmission (UL-MU) for STAs with unknown transmit buffer has been adopted in the upcoming IEEE802.11ax next generation wireless LAN standard. In this paper, we propose a performance analysis model which use bidimensional Markov chain model of OFDMA random access. Via computer simulation, we show the usefulness of the proposed method even in the case of dense environment. In addition, we present a method in calculating the optimal number of resource units, which in 802.11ax refer to a subset of subcarriers to assign the user for OFDMA random access from numerical results.","PeriodicalId":131543,"journal":{"name":"2016 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133350348","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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