This article proposes a system-aware, fully programmatic and automated, process agnostic design methodology, which utilizes system-level simulations with the layout parasitics of the circuit under optimization included. The methodology is demonstrated with a design procedure for a comparator from specification to layout implementation in three analog-to-digital converter design examples with different specifications and applications without designer interaction. The procedure is shown to effectively converge toward performance achieved with ideal comparator in post-layout across two different semiconductor processes. While the methodology was demonstrated for design of comparators, the proposed system-aware methodology is generally applicable to any analog circuit, drastically reducing design time while providing a silicon ready circuit implementation purpose designed to the higher level system without human-in-the-loop.
{"title":"Fully Programmatic Automated Design Procedure of Comparators for Analog-to-Digital Converters","authors":"Veeti Lahtinen;Santeri Porrasmaa;Altti Heikkinen;Miikka Tenhunen;Jussi Ryynänen;Marko Kosunen","doi":"10.1109/TCAD.2025.3560224","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3560224","url":null,"abstract":"This article proposes a system-aware, fully programmatic and automated, process agnostic design methodology, which utilizes system-level simulations with the layout parasitics of the circuit under optimization included. The methodology is demonstrated with a design procedure for a comparator from specification to layout implementation in three analog-to-digital converter design examples with different specifications and applications without designer interaction. The procedure is shown to effectively converge toward performance achieved with ideal comparator in post-layout across two different semiconductor processes. While the methodology was demonstrated for design of comparators, the proposed system-aware methodology is generally applicable to any analog circuit, drastically reducing design time while providing a silicon ready circuit implementation purpose designed to the higher level system without human-in-the-loop.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"44 10","pages":"4043-4047"},"PeriodicalIF":2.9,"publicationDate":"2025-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10963892","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145100510","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-04DOI: 10.1109/TCAD.2025.3558145
Haoyang Xu;Xing Huang;Zhen Zhuang;Zhiwen Yu;Bin Guo;Kai-Yuan Chao;Bei Yu;Tsung-Yi Ho;Martin D. F. Wong
In modern advanced fan-out wafer-level packaging (FOWLP), redistribution layers (RDLs) are used to implement efficient interconnections among chips, where both flexible vias and irregular pad structures can be deployed to realize highly integrated heterogeneous systems. With the sharp increase in chip densities, however, it becomes challenging to fully utilize the routing resources in RDLs. The routing graph without optimized resource planning can lead to significant deterioration in the solution quality of RDL design. Furthermore, prior work determines via locations in the RDLs before identifying wire routes, thus offsetting the advantages of flexible vias and irregular pads. To systematically solve the RDL routing problem in FOWLP, in this article, we propose a hierarchical partitioning-based interchip routing method considering both flexible vias and irregular pads, so that optimized RDL solutions can be generated automatically and efficiently. The proposed method includes the following key techniques: 1) a channel planning method for optimized routing region partition and a dynamic routing graph-based pathfinding method for efficient global routing; 2) a binary-search-based hierarchical tile segmentation method for conflict removal and wirelength reduction; 3) a novel monotonicity-analysis-based access point optimization method and a staggered via planning strategy for both wirelength and detour reduction; and 4) a geometry-based detailed routing algorithm for innertile wire routing. The experimental results demonstrate that the proposed algorithm leads to 100% routablility and 4.8% wirelength reduction on average compared to the state-of-the-art work, with a maximum reduction rate of 10.3% across all the benchmarks.
{"title":"Hierarchical Partitioning-Based Interchip Redistribution Layer Routing for Fan-Out Wafer-Level Packaging","authors":"Haoyang Xu;Xing Huang;Zhen Zhuang;Zhiwen Yu;Bin Guo;Kai-Yuan Chao;Bei Yu;Tsung-Yi Ho;Martin D. F. Wong","doi":"10.1109/TCAD.2025.3558145","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3558145","url":null,"abstract":"In modern advanced fan-out wafer-level packaging (FOWLP), redistribution layers (RDLs) are used to implement efficient interconnections among chips, where both flexible vias and irregular pad structures can be deployed to realize highly integrated heterogeneous systems. With the sharp increase in chip densities, however, it becomes challenging to fully utilize the routing resources in RDLs. The routing graph without optimized resource planning can lead to significant deterioration in the solution quality of RDL design. Furthermore, prior work determines via locations in the RDLs before identifying wire routes, thus offsetting the advantages of flexible vias and irregular pads. To systematically solve the RDL routing problem in FOWLP, in this article, we propose a hierarchical partitioning-based interchip routing method considering both flexible vias and irregular pads, so that optimized RDL solutions can be generated automatically and efficiently. The proposed method includes the following key techniques: 1) a channel planning method for optimized routing region partition and a dynamic routing graph-based pathfinding method for efficient global routing; 2) a binary-search-based hierarchical tile segmentation method for conflict removal and wirelength reduction; 3) a novel monotonicity-analysis-based access point optimization method and a staggered via planning strategy for both wirelength and detour reduction; and 4) a geometry-based detailed routing algorithm for innertile wire routing. The experimental results demonstrate that the proposed algorithm leads to 100% routablility and 4.8% wirelength reduction on average compared to the state-of-the-art work, with a maximum reduction rate of 10.3% across all the benchmarks.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"44 11","pages":"4367-4380"},"PeriodicalIF":2.9,"publicationDate":"2025-04-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145405340","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Placement is a critical task with high computation complexity in VLSI physical design. Modern analytical placers formulate the placement objective as a nonlinear optimization task, which suffers a long iteration time. To accelerate and enhance the placement process, recent studies have turned to deep learning-based approaches, particularly leveraging graph convolution networks (GCNs). However, learning-based placers require time- and data-consuming model training due to the complexity of circuit placement that involves large-scale cells and design-specific graph statistics. This article proposes GiFt, a parameter-free initialization technique for accelerating placement, rooted in graph signal processing. GiFt excels at capturing multiresolution smooth signals of circuit graphs to generate optimized initial placement solutions without the need for time-consuming model training, and meanwhile significantly reduces the number of iterations required by analytical placers. Moreover, we present GiFtPlus, an enhanced version of GiFt, which is more efficient in handling large-scale circuit placement and can accommodate location constraints. Experimental results on public benchmarks show that GiFt and GiFtPlus significantly improve placement efficiency, while achieving competitive or superior performance compared to state-of-the-art placers. In particular, the recently proposed GPU-accelerated analytical placer DREAMPlace uses up to 50% more total runtime than GiFtPlus-DREAMPlace.
{"title":"An Efficient Placement Speedup Technique Based on Graph Signal Processing","authors":"Yiting Liu;Hai Zhou;Jia Wang;Fan Yang;Xuan Zeng;Li Shang","doi":"10.1109/TCAD.2025.3556968","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3556968","url":null,"abstract":"Placement is a critical task with high computation complexity in VLSI physical design. Modern analytical placers formulate the placement objective as a nonlinear optimization task, which suffers a long iteration time. To accelerate and enhance the placement process, recent studies have turned to deep learning-based approaches, particularly leveraging graph convolution networks (GCNs). However, learning-based placers require time- and data-consuming model training due to the complexity of circuit placement that involves large-scale cells and design-specific graph statistics. This article proposes GiFt, a parameter-free initialization technique for accelerating placement, rooted in graph signal processing. GiFt excels at capturing multiresolution smooth signals of circuit graphs to generate optimized initial placement solutions without the need for time-consuming model training, and meanwhile significantly reduces the number of iterations required by analytical placers. Moreover, we present GiFtPlus, an enhanced version of GiFt, which is more efficient in handling large-scale circuit placement and can accommodate location constraints. Experimental results on public benchmarks show that GiFt and GiFtPlus significantly improve placement efficiency, while achieving competitive or superior performance compared to state-of-the-art placers. In particular, the recently proposed GPU-accelerated analytical placer DREAMPlace uses up to 50% more total runtime than GiFtPlus-DREAMPlace.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"44 10","pages":"3924-3937"},"PeriodicalIF":2.9,"publicationDate":"2025-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145090051","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-01DOI: 10.1109/TCAD.2025.3556969
Qianxi Chen;Yujiao Deng;Qiang Wu;Zhixiong Di
As chip manufacturing approaches physical limits, the probability of defects due to specific chip layout structures has significantly increased. These defect-prone structures are known as lithographic hotspots. Pattern matching method is widely used in hotspot detection algorithms due to its efficiency and accuracy. However, traditional pattern matching algorithms face major challenges in both solution efficiency and flexibility for fuzzy matching. To overcome these limitations, an integer range-based deterministic finite automaton (r-DFA)-based layout pattern matching method supporting parallelization and fuzzy matching is proposed. Manhattan polygons in the layout are represented as multiple path strings, thereby transforming the pattern matching problem into a string regular expression search problem. To simplifies the construction of large integer range elements in fuzzy matching, the r-DFA is employed, enhancing construction efficiency and enabling the algorithm to achieve linear time complexity. Moreover, this approach focuses most of the matching process within each individual layout polygon, enabling parallelized matching across diverse layout polygons. Compared to the state-of-the-art, our approach supports fuzzy matching, and shows an average efficiency improvement of 1.23 times.
{"title":"An r-DFA-Based Layout Pattern Match Method Supporting Fuzzy Matching","authors":"Qianxi Chen;Yujiao Deng;Qiang Wu;Zhixiong Di","doi":"10.1109/TCAD.2025.3556969","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3556969","url":null,"abstract":"As chip manufacturing approaches physical limits, the probability of defects due to specific chip layout structures has significantly increased. These defect-prone structures are known as lithographic hotspots. Pattern matching method is widely used in hotspot detection algorithms due to its efficiency and accuracy. However, traditional pattern matching algorithms face major challenges in both solution efficiency and flexibility for fuzzy matching. To overcome these limitations, an integer range-based deterministic finite automaton (r-DFA)-based layout pattern matching method supporting parallelization and fuzzy matching is proposed. Manhattan polygons in the layout are represented as multiple path strings, thereby transforming the pattern matching problem into a string regular expression search problem. To simplifies the construction of large integer range elements in fuzzy matching, the r-DFA is employed, enhancing construction efficiency and enabling the algorithm to achieve linear time complexity. Moreover, this approach focuses most of the matching process within each individual layout polygon, enabling parallelized matching across diverse layout polygons. Compared to the state-of-the-art, our approach supports fuzzy matching, and shows an average efficiency improvement of 1.23 times.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"44 10","pages":"3938-3947"},"PeriodicalIF":2.9,"publicationDate":"2025-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145090053","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-01DOI: 10.1109/TCAD.2025.3556967
Mohamed Amine Hamdi;Francesco Daghero;Giuseppe Maria Sarda;Josse Van Delm;Arne Symons;Luca Benini;Marian Verhelst;Daniele Jahier Pagliari;Alessio Burrello
Streamlining the deployment of Deep Neural Networks (DNNs) on heterogeneous edge platforms, coupling within the same micro-controller unit (MCU) instruction processors and hardware accelerators for tensor computations, is becoming one of the crucial challenges of the TinyML field. The best-performing DNN compilation toolchains are usually deeply customized for a single MCU family, and porting them to a different one implies labor-intensive redevelopment of almost the entire compiler. On the opposite side, retargetable toolchains, such as TVM, fail to exploit the capabilities of custom accelerators, producing general but unoptimized code. To overcome this duality, we introduce MATCH, a novel TVM-based DNN deployment framework designed for easy agile retargeting across different MCU processors and accelerators, thanks to a customizable model-based hardware abstraction. We show that a general and retargetable mapping framework can compete with, and even outperform custom toolchains on diverse targets while only needing the definition of an abstract hardware cost model and a SoC-specific API. We tested MATCH on two state-of-the-art heterogeneous MCUs, GAP9 and DIANA. On the four DNN models of the MLPerf Tiny suite MATCH reduces inference latency on average by $60.87times $ on DIANA, compared to using the plain TVM, thanks to the exploitation of the on-board HW accelerator. Compared to HTVM, a fully customized toolchain for DIANA, we still reduce the latency by 16.94%. On GAP9, using the same benchmarks, we improve the latency by $2.15times $ compared to the dedicated DORY compiler, thanks to our heterogeneous DNN mapping approach that synergically exploits the DNN accelerator and the eight-cores cluster available on board.
{"title":"MATCH: Model-Aware TVM-Based Compilation for Heterogeneous Edge Devices","authors":"Mohamed Amine Hamdi;Francesco Daghero;Giuseppe Maria Sarda;Josse Van Delm;Arne Symons;Luca Benini;Marian Verhelst;Daniele Jahier Pagliari;Alessio Burrello","doi":"10.1109/TCAD.2025.3556967","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3556967","url":null,"abstract":"Streamlining the deployment of Deep Neural Networks (DNNs) on heterogeneous edge platforms, coupling within the same micro-controller unit (MCU) instruction processors and hardware accelerators for tensor computations, is becoming one of the crucial challenges of the TinyML field. The best-performing DNN compilation toolchains are usually deeply customized for a single MCU family, and porting them to a different one implies labor-intensive redevelopment of almost the entire compiler. On the opposite side, retargetable toolchains, such as TVM, fail to exploit the capabilities of custom accelerators, producing general but unoptimized code. To overcome this duality, we introduce MATCH, a novel TVM-based DNN deployment framework designed for easy agile retargeting across different MCU processors and accelerators, thanks to a customizable model-based hardware abstraction. We show that a general and retargetable mapping framework can compete with, and even outperform custom toolchains on diverse targets while only needing the definition of an abstract hardware cost model and a SoC-specific API. We tested MATCH on two state-of-the-art heterogeneous MCUs, GAP9 and DIANA. On the four DNN models of the MLPerf Tiny suite MATCH reduces inference latency on average by <inline-formula> <tex-math>$60.87times $ </tex-math></inline-formula> on DIANA, compared to using the plain TVM, thanks to the exploitation of the on-board HW accelerator. Compared to HTVM, a fully customized toolchain for DIANA, we still reduce the latency by 16.94%. On GAP9, using the same benchmarks, we improve the latency by <inline-formula> <tex-math>$2.15times $ </tex-math></inline-formula> compared to the dedicated DORY compiler, thanks to our heterogeneous DNN mapping approach that synergically exploits the DNN accelerator and the eight-cores cluster available on board.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"44 10","pages":"3844-3857"},"PeriodicalIF":2.9,"publicationDate":"2025-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145090257","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The security closure of integrated circuits (ICs) is an emerging area of research within the very large scale integration (VLSI) community. Malicious third parties, referred to as “attackers,” can employ various techniques to leak, alter, or manipulate the logic of a circuit. When targeting a completed layout, their primary goal is often the insertion of hardware trojans. In this work, we present algorithms that strengthen placement solutions against hardware trojan attacks. While state-of-the-art methods rely on exhaustive placement algorithms, we propose a clustering-based placement approach that reduces the number of moved cells by up to 17%. Additionally, we introduce a cell movement heuristic aimed at preventing increases in wirelength. Our methods reduce vulnerable placement sites by up to 78% while maintaining minimal impact on design performance. Compared to other approaches, our solution decreases the amount of moved cells to an average of 8%, mitigating the impact on wirelength to an average of 0.5%.
{"title":"Placement Refinement Strategies for Security Closure","authors":"Marcelo Danigno;Mateus Fogaça;Rafael Schvittz;Paulo Butzen","doi":"10.1109/TCAD.2025.3555964","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3555964","url":null,"abstract":"The security closure of integrated circuits (ICs) is an emerging area of research within the very large scale integration (VLSI) community. Malicious third parties, referred to as “attackers,” can employ various techniques to leak, alter, or manipulate the logic of a circuit. When targeting a completed layout, their primary goal is often the insertion of hardware trojans. In this work, we present algorithms that strengthen placement solutions against hardware trojan attacks. While state-of-the-art methods rely on exhaustive placement algorithms, we propose a clustering-based placement approach that reduces the number of moved cells by up to 17%. Additionally, we introduce a cell movement heuristic aimed at preventing increases in wirelength. Our methods reduce vulnerable placement sites by up to 78% while maintaining minimal impact on design performance. Compared to other approaches, our solution decreases the amount of moved cells to an average of 8%, mitigating the impact on wirelength to an average of 0.5%.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"44 10","pages":"4053-4058"},"PeriodicalIF":2.9,"publicationDate":"2025-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145100402","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-03-28DOI: 10.1109/TCAD.2025.3555507
Wentian Wu;Qianhui Li;Tong Qu;Qi Wang;Zongliang Huo;Tianchun Ye
With the development of flash technology, the increasing throughput gap between nand flash memory (NFM) arrays and the I/O interface has become a performance bottleneck for NFM-based solid-state drives (SSDs). Multilevel parallelism techniques have been employed on modern SSDs to meet the challenge of increasing demands for bandwidth in I/O-intensive workloads. However, conventional parallel methods only monitor the status of ways, resulting in the “idle bubble”—idle time of the dies cannot execute subsequent operations until all the dies in the way complete command execution. This issue limits the resource utilization and performance of SSDs. To minimize the idle bubble, we propose priority-based out-of-order scheduling and fine-grain status polling (POFGSP). The priority-based out-of-order scheduling relaxes constraints on command execution order and schedules commands with the same execution time to be executed in parallel. Therefore, the scheduler reduces these idle bubbles caused by differences in command execution times. Moreover, the fine-grain status polling approach polls the die-level status during the interface’s idle time, reducing idle bubbles with accurate status. Compared to state-of-the-art schedulers, our POFGSP approach can reduce request response time by 35.6% under real-world cloud block storage workloads and improve the SSD system’s maximum bandwidth by 8.7%–74.9%.
{"title":"POFGSP: Priority-Based Out-of-Order Scheduling and Fine-Grain Status Polling for SSD Performance Improvement","authors":"Wentian Wu;Qianhui Li;Tong Qu;Qi Wang;Zongliang Huo;Tianchun Ye","doi":"10.1109/TCAD.2025.3555507","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3555507","url":null,"abstract":"With the development of flash technology, the increasing throughput gap between <sc>nand</small> flash memory (NFM) arrays and the I/O interface has become a performance bottleneck for NFM-based solid-state drives (SSDs). Multilevel parallelism techniques have been employed on modern SSDs to meet the challenge of increasing demands for bandwidth in I/O-intensive workloads. However, conventional parallel methods only monitor the status of ways, resulting in the “idle bubble”—idle time of the dies cannot execute subsequent operations until all the dies in the way complete command execution. This issue limits the resource utilization and performance of SSDs. To minimize the idle bubble, we propose priority-based out-of-order scheduling and fine-grain status polling (POFGSP). The priority-based out-of-order scheduling relaxes constraints on command execution order and schedules commands with the same execution time to be executed in parallel. Therefore, the scheduler reduces these idle bubbles caused by differences in command execution times. Moreover, the fine-grain status polling approach polls the die-level status during the interface’s idle time, reducing idle bubbles with accurate status. Compared to state-of-the-art schedulers, our POFGSP approach can reduce request response time by 35.6% under real-world cloud block storage workloads and improve the SSD system’s maximum bandwidth by 8.7%–74.9%.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"44 10","pages":"3724-3737"},"PeriodicalIF":2.9,"publicationDate":"2025-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145090259","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The fusion of tiny energy harvesting devices with deep neural networks (DNN) optimized for intermittent execution is vital for sustainable intelligent applications at the edge. However, current intermittent-aware neural architecture search (NAS) frameworks overlook the inherent intermittency management overhead (IMO) of DNNs, leading to under-performance upon deployment. Moreover, we observe that straightforward IMO minimization within NAS may degrade solution accuracy. This work explores the relationship between DNN architectural characteristics, IMO, and accuracy, uncovering the varying sensitivity toward IMO across different DNN characteristics. Inspired by our insights, we present two guidelines for leveraging IMO sensitivity in NAS. First, the overall architecture search space can be reduced to exclude parameters with low IMO sensitivity, and second, network blocks with high IMO sensitivity can be primarily focused during the search, facilitating the discovery of highly accurate networks with low IMO. We incorporate these guidelines into TiNAS, which integrates cutting-edge tiny NAS and intermittent-aware NAS frameworks. Evaluations are conducted across various datasets and latency requirements, as well as deployment experiments on a Texas Instruments device under different intermittent power profiles. Compared to two variants, one minimizing IMO and the other disregarding IMO, TiNAS, respectively, achieves up to 38% higher accuracy and 33% lower IMO, with greater improvements for larger datasets. Its deployed solutions also achieve up to a 1.33 times inference speedup, especially under fluctuating power conditions.
{"title":"Intermittent-Friendly Neural Architecture Search: Demystifying Accuracy and Overhead Tradeoffs","authors":"Hashan Roshantha Mendis;Chih-Hsuan Yen;Chih-Kai Kang;Pi-Cheng Hsiu","doi":"10.1109/TCAD.2025.3555963","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3555963","url":null,"abstract":"The fusion of tiny energy harvesting devices with deep neural networks (DNN) optimized for intermittent execution is vital for sustainable intelligent applications at the edge. However, current intermittent-aware neural architecture search (NAS) frameworks overlook the inherent intermittency management overhead (IMO) of DNNs, leading to under-performance upon deployment. Moreover, we observe that straightforward IMO minimization within NAS may degrade solution accuracy. This work explores the relationship between DNN architectural characteristics, IMO, and accuracy, uncovering the varying sensitivity toward IMO across different DNN characteristics. Inspired by our insights, we present two guidelines for leveraging IMO sensitivity in NAS. First, the overall architecture search space can be reduced to exclude parameters with low IMO sensitivity, and second, network blocks with high IMO sensitivity can be primarily focused during the search, facilitating the discovery of highly accurate networks with low IMO. We incorporate these guidelines into TiNAS, which integrates cutting-edge tiny NAS and intermittent-aware NAS frameworks. Evaluations are conducted across various datasets and latency requirements, as well as deployment experiments on a Texas Instruments device under different intermittent power profiles. Compared to two variants, one minimizing IMO and the other disregarding IMO, TiNAS, respectively, achieves up to 38% higher accuracy and 33% lower IMO, with greater improvements for larger datasets. Its deployed solutions also achieve up to a 1.33 times inference speedup, especially under fluctuating power conditions.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"44 10","pages":"3990-4003"},"PeriodicalIF":2.9,"publicationDate":"2025-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145100355","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This article introduces OpenLS-DGF, an adaptive logic synthesis dataset generation framework, to enhance machine-learning (ML) applications within the logic synthesis process. Previous dataset generation flows were tailored for specific tasks or lacked integrated ML capabilities. While OpenLS-DGF supports various ML tasks by encapsulating the three fundamental steps of logic synthesis: 1) Boolean representation; 2) logic optimization; and 3) technology mapping. It preserves the original information in both Verilog and ML-friendly GraphML formats. The Verilog files offer semi-customizable capabilities, enabling researchers to insert additional steps and incrementally refine the generated dataset. Furthermore, OpenLS-DGF includes an adaptive circuit engine that facilitates the final dataset management and downstream tasks. The generated OpenLS-D-v1 dataset comprises 46 combinational designs from established benchmarks, totaling over 966 000 Boolean circuits. OpenLS-D-v1 supports integrating new data features, making it more versatile for new tasks. This article demonstrates the versatility of OpenLS-D-v1 through four distinct downstream tasks: circuit classification, circuit ranking, quality of results (QoR) prediction, and probability prediction. Each task is chosen to represent essential steps of logic synthesis, and the experimental results show the generated dataset from OpenLS-DGF achieves prominent diversity and applicability. The source code and datasets are available at https://github.com/Logic-Factory/ACE/blob/master/OpenLS-DGF.
{"title":"OpenLS-DGF: An Adaptive Open-Source Dataset Generation Framework for Machine-Learning Tasks in Logic Synthesis","authors":"Liwei Ni;Rui Wang;Miao Liu;Xingyu Meng;Xiaoze Lin;Junfeng Liu;Guojie Luo;Zhufei Chu;Weikang Qian;Xiaoyan Yang;Biwei Xie;Xingquan Li;Huawei Li","doi":"10.1109/TCAD.2025.3555506","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3555506","url":null,"abstract":"This article introduces OpenLS-DGF, an adaptive logic synthesis dataset generation framework, to enhance machine-learning (ML) applications within the logic synthesis process. Previous dataset generation flows were tailored for specific tasks or lacked integrated ML capabilities. While OpenLS-DGF supports various ML tasks by encapsulating the three fundamental steps of logic synthesis: 1) Boolean representation; 2) logic optimization; and 3) technology mapping. It preserves the original information in both Verilog and ML-friendly GraphML formats. The Verilog files offer semi-customizable capabilities, enabling researchers to insert additional steps and incrementally refine the generated dataset. Furthermore, OpenLS-DGF includes an adaptive circuit engine that facilitates the final dataset management and downstream tasks. The generated OpenLS-D-v1 dataset comprises 46 combinational designs from established benchmarks, totaling over 966 000 Boolean circuits. OpenLS-D-v1 supports integrating new data features, making it more versatile for new tasks. This article demonstrates the versatility of OpenLS-D-v1 through four distinct downstream tasks: circuit classification, circuit ranking, quality of results (QoR) prediction, and probability prediction. Each task is chosen to represent essential steps of logic synthesis, and the experimental results show the generated dataset from OpenLS-DGF achieves prominent diversity and applicability. The source code and datasets are available at <uri>https://github.com/Logic-Factory/ACE/blob/master/OpenLS-DGF</uri>.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"44 10","pages":"3830-3843"},"PeriodicalIF":2.9,"publicationDate":"2025-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145090249","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-03-27DOI: 10.1109/TCAD.2025.3555513
Yang Wang;Hanlong Chen;Wang Lin;Zuohua Ding
Barrier certificate generation is an ingenious and powerful approach for safety verification of cyber-physical systems. This article suggests a new learning and verification framework that helps to achieve the balance between the representation ability and the verification efficiency for neural barrier certificates. In the learning phase, it learns candidate barrier certificates represented as convex difference neural networks (CDiNNs). Since CDiNNs can be rewritten as difference of convex (DC) functions that can express any twice differentiable function, thus have outstanding representation ability and flexibility. In the verification phase, it employs an efficient approach for formally verifying the validity of the neural candidates via DC programming. Due to the convexity-based structure, CDiNNs can significantly facilitate the verification process. We conduct an experimental evaluation over a set of benchmarks, which validates that our method is much more efficient and effective than the state-of-the-art approaches.
{"title":"Formal Synthesis of Neural Barrier Certificates for Dynamical Systems via DC Programming","authors":"Yang Wang;Hanlong Chen;Wang Lin;Zuohua Ding","doi":"10.1109/TCAD.2025.3555513","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3555513","url":null,"abstract":"Barrier certificate generation is an ingenious and powerful approach for safety verification of cyber-physical systems. This article suggests a new learning and verification framework that helps to achieve the balance between the representation ability and the verification efficiency for neural barrier certificates. In the learning phase, it learns candidate barrier certificates represented as convex difference neural networks (CDiNNs). Since CDiNNs can be rewritten as difference of convex (DC) functions that can express any twice differentiable function, thus have outstanding representation ability and flexibility. In the verification phase, it employs an efficient approach for formally verifying the validity of the neural candidates via DC programming. Due to the convexity-based structure, CDiNNs can significantly facilitate the verification process. We conduct an experimental evaluation over a set of benchmarks, which validates that our method is much more efficient and effective than the state-of-the-art approaches.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"44 10","pages":"4038-4042"},"PeriodicalIF":2.9,"publicationDate":"2025-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145100356","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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