Modern cyber-physical systems (CPSs) employ an increasingly large number of software control loops to enhance their autonomous capabilities. Such large task sets and their dependencies may lead to deadline misses caused by platform-level timing uncertainties, resource contention, etc. To ensure the schedulability of the task set in the embedded platform in the presence of these uncertainties, there exist co-design techniques that assign task periodicities such that control costs are minimized. Another line of work exists that addresses the same platform schedulability issue by skipping a bounded number of control executions within a fixed number of control instances. Considering that control tasks are designed to perform robustly against delayed actuation (due to deadline misses, network packet drops etc.) a bounded number of control skips can be applied while ensuring certain performance margin. Our work combines these two control scheduling co-design disciplines and develops a strategy to adaptively employ control skips or update periodicities of the control tasks depending on their current performance requirements. For this we leverage a novel theory of automata-based control skip sequence generation while ensuring periodicity, safety and stability constraints. We demonstrate the effectiveness of this dynamic resource sharing approach in an automotive Hardware-in-loop setup with realistic control task set implementations.
{"title":"Revisiting Dynamic Scheduling of Control Tasks: A Performance-Aware Fine-Grained Approach","authors":"Sunandan Adhikary;Ipsita Koley;Saurav Kumar Ghosh;Sumana Ghosh;Soumyajit Dey","doi":"10.1109/TCAD.2024.3443007","DOIUrl":"https://doi.org/10.1109/TCAD.2024.3443007","url":null,"abstract":"Modern cyber-physical systems (CPSs) employ an increasingly large number of software control loops to enhance their autonomous capabilities. Such large task sets and their dependencies may lead to deadline misses caused by platform-level timing uncertainties, resource contention, etc. To ensure the schedulability of the task set in the embedded platform in the presence of these uncertainties, there exist co-design techniques that assign task periodicities such that control costs are minimized. Another line of work exists that addresses the same platform schedulability issue by skipping a bounded number of control executions within a fixed number of control instances. Considering that control tasks are designed to perform robustly against delayed actuation (due to deadline misses, network packet drops etc.) a bounded number of control skips can be applied while ensuring certain performance margin. Our work combines these two control scheduling co-design disciplines and develops a strategy to adaptively employ control skips or update periodicities of the control tasks depending on their current performance requirements. For this we leverage a novel theory of automata-based control skip sequence generation while ensuring periodicity, safety and stability constraints. We demonstrate the effectiveness of this dynamic resource sharing approach in an automotive Hardware-in-loop setup with realistic control task set implementations.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"43 11","pages":"3662-3673"},"PeriodicalIF":2.7,"publicationDate":"2024-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142595818","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-06DOI: 10.1109/TCAD.2024.3438113
Fabian Seiler;Nima TaheriNejad
Image processing algorithms continue to demand higher performance from computers. However, computer performance is not improving at the same rate as before. In response to the current challenges in enhancing computing performance, a wave of new technologies and computing paradigms is surfacing. Among these, memristors stand out as one of the most promising components due to their technological prospects and low power consumption. With efficient data storage capabilities and their ability to directly perform logical operations within the memory, they are well-suited for in-memory computation (IMC). Approximate computing emerges as another promising paradigm, offering improved performance metrics, notably speed. The tradeoff for this gain is the reduction of accuracy. In this article, we are using the stateful logic material implication (IMPLY) in the semi-serial topology and combine both the paradigms to further enhance the computational performance. We present three novel approximated adders that drastically improve speed and energy consumption with an normalized mean error distance (NMED) lower than 0.02 for most scenarios. We evaluated partially approximated Ripple carry adder (RCA) at the circuit-level and compared them to the State-of-the-Art (SoA). The proposed adders are applied in different image processing applications and the quality metrics are calculated. While maintaining acceptable quality, our approach achieves significant energy savings of 6%–38% and reduces the delay (number of computation cycles) by 5%–35%, demonstrating notable efficiency compared to exact calculations.
{"title":"Efficient Image Processing via Memristive-Based Approximate In-Memory Computing","authors":"Fabian Seiler;Nima TaheriNejad","doi":"10.1109/TCAD.2024.3438113","DOIUrl":"https://doi.org/10.1109/TCAD.2024.3438113","url":null,"abstract":"Image processing algorithms continue to demand higher performance from computers. However, computer performance is not improving at the same rate as before. In response to the current challenges in enhancing computing performance, a wave of new technologies and computing paradigms is surfacing. Among these, memristors stand out as one of the most promising components due to their technological prospects and low power consumption. With efficient data storage capabilities and their ability to directly perform logical operations within the memory, they are well-suited for in-memory computation (IMC). Approximate computing emerges as another promising paradigm, offering improved performance metrics, notably speed. The tradeoff for this gain is the reduction of accuracy. In this article, we are using the stateful logic material implication (IMPLY) in the semi-serial topology and combine both the paradigms to further enhance the computational performance. We present three novel approximated adders that drastically improve speed and energy consumption with an normalized mean error distance (NMED) lower than 0.02 for most scenarios. We evaluated partially approximated Ripple carry adder (RCA) at the circuit-level and compared them to the State-of-the-Art (SoA). The proposed adders are applied in different image processing applications and the quality metrics are calculated. While maintaining acceptable quality, our approach achieves significant energy savings of 6%–38% and reduces the delay (number of computation cycles) by 5%–35%, demonstrating notable efficiency compared to exact calculations.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"43 11","pages":"3312-3323"},"PeriodicalIF":2.7,"publicationDate":"2024-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10745792","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142595845","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-26DOI: 10.1109/TCAD.2024.3432632
Kun Wu;Yuncheng Liu;Hui Gao;Jun Tao;Wei Xiong;Xin Li
Since diffractive deep neural network (D2NN) provides a full optical solution to implement deep neural networks (DNNs), it offers ultrafast operation speed and virtually unlimited bandwidth, yielding an alternative-yet-competitive approach for computer-based neural networks. A D2NN is composed of several 3D-printed phase masks as hidden layers and a number of optical detectors at the output. To enable automatic and efficient design of D2NNs, we propose an iterative optimization method to determine the optimal design parameters of D2NNs. During each iteration step, we first optimize the physical parameters for masks (e.g., thicknesses) while fixing the detector parameters (e.g., locations). Next, we exhaustively search the detector parameters with fixed masks. These two steps are repeated until convergence is reached. Our numerical experiments demonstrate that the proposed optimization algorithm can produce a high-performance D2NN achieving 97% accuracy for recognizing handwritten digits.
{"title":"Efficient Design Optimization for Diffractive Deep Neural Networks","authors":"Kun Wu;Yuncheng Liu;Hui Gao;Jun Tao;Wei Xiong;Xin Li","doi":"10.1109/TCAD.2024.3432632","DOIUrl":"https://doi.org/10.1109/TCAD.2024.3432632","url":null,"abstract":"Since diffractive deep neural network (D2NN) provides a full optical solution to implement deep neural networks (DNNs), it offers ultrafast operation speed and virtually unlimited bandwidth, yielding an alternative-yet-competitive approach for computer-based neural networks. A D2NN is composed of several 3D-printed phase masks as hidden layers and a number of optical detectors at the output. To enable automatic and efficient design of D2NNs, we propose an iterative optimization method to determine the optimal design parameters of D2NNs. During each iteration step, we first optimize the physical parameters for masks (e.g., thicknesses) while fixing the detector parameters (e.g., locations). Next, we exhaustively search the detector parameters with fixed masks. These two steps are repeated until convergence is reached. Our numerical experiments demonstrate that the proposed optimization algorithm can produce a high-performance D2NN achieving 97% accuracy for recognizing handwritten digits.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"44 3","pages":"1199-1203"},"PeriodicalIF":2.7,"publicationDate":"2024-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143465682","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Multiple patterning lithography (MPL) has been introduced in the integrated circuits manufacturing industry to enhance feature density as the technology node advances. A crucial step of MPL is assigning layout features to different masks, namely layout decomposition. Exact algorithms like integer linear programming (ILP) can solve layout decomposition to optimality but lack scalability for dense patterns. Relaxation algorithms (e.g., linear programming and semi-definite programming) and heuristics (e.g., exact cover) are capable of handling large cases at the cost of inferior solution quality. These methods rely on different mathematical solvers and expert-designed heuristics to offer a balance between solution quality and computational efficiency. In this article, we propose a unified layout decomposition framework comprising three algorithms: 1) satisfiability (SAT)-exact; 2) SAT-bilevel; and 3) SAT-fast, all leveraging the capabilities of Boolean SAT solvers. The SAT-exact ensures optimality, but with faster convergence than ILP, SAT-bilevel addresses the decomposition as a bilevel optimization problem for rapid near-optimal solutions, and SAT-fast handles very large layouts in an incremental manner. Experimental results demonstrate our framework’s superiority over existing state-of-the-art methods in terms of solution quality and runtime.
随着技术节点的发展，集成电路制造业引入了多重图案光刻技术（MPL），以提高特征密度。MPL 的一个关键步骤是将版图特征分配给不同的掩膜，即版图分解。整数线性规划（ILP）等精确算法可以最优地解决布局分解问题，但对密集图案缺乏可扩展性。放松算法（如线性规划和半有限规划）和启发式算法（如精确覆盖）能够处理大型案例，但代价是解决方案质量较差。这些方法依赖于不同的数学求解器和专家设计的启发式算法，在求解质量和计算效率之间取得平衡。在本文中，我们提出了一个统一的布局分解框架，包括三种算法：1）精确可满足性（SAT）；2）SAT-bilevel；3）SAT-fast，所有算法都利用了布尔 SAT 求解器的功能。SAT-exact 确保最优性，但收敛速度比 ILP 更快；SAT-bilevel 将分解作为一个双层优化问题来处理，以快速获得接近最优的解决方案；SAT-fast 以增量方式处理超大布局。实验结果表明，就解决方案质量和运行时间而言，我们的框架优于现有的最先进方法。
{"title":"Layout Decomposition via Boolean Satisfiability","authors":"Hongduo Liu;Peiyu Liao;Mengchuan Zou;Bowen Pang;Xijun Li;Mingxuan Yuan;Tsung-Yi Ho;Bei Yu","doi":"10.1109/TCAD.2024.3467220","DOIUrl":"https://doi.org/10.1109/TCAD.2024.3467220","url":null,"abstract":"Multiple patterning lithography (MPL) has been introduced in the integrated circuits manufacturing industry to enhance feature density as the technology node advances. A crucial step of MPL is assigning layout features to different masks, namely layout decomposition. Exact algorithms like integer linear programming (ILP) can solve layout decomposition to optimality but lack scalability for dense patterns. Relaxation algorithms (e.g., linear programming and semi-definite programming) and heuristics (e.g., exact cover) are capable of handling large cases at the cost of inferior solution quality. These methods rely on different mathematical solvers and expert-designed heuristics to offer a balance between solution quality and computational efficiency. In this article, we propose a unified layout decomposition framework comprising three algorithms: 1) satisfiability (SAT)-exact; 2) SAT-bilevel; and 3) SAT-fast, all leveraging the capabilities of Boolean SAT solvers. The SAT-exact ensures optimality, but with faster convergence than ILP, SAT-bilevel addresses the decomposition as a bilevel optimization problem for rapid near-optimal solutions, and SAT-fast handles very large layouts in an incremental manner. Experimental results demonstrate our framework’s superiority over existing state-of-the-art methods in terms of solution quality and runtime.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"44 3","pages":"1112-1125"},"PeriodicalIF":2.7,"publicationDate":"2024-09-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143465681","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Insulated gate bipolar transistors (IGBTs) are the key component in power electronics, and the intricate relationship between their performance and structural parameters poses a formidable challenge in the design process. This article proposes an automatic optimal design method for IGBT structural parameters to leverage the pretrained machine learning (ML) model to efficiently predict the initial IGBT device’s performance, followed by utilizing the differential evolution (DE) algorithm to automatically adjust structural parameters based on the disparity between predicted and expected device performance until the expected performance is achieved. The method is validated in the design of punch-through IGBTs (PT-IGBTs) and trench gate field-stop IGBTs (FS-IGBTs), and the performance of technology computer-aided design (TCAD) simulation of the designed device is similar to the target performance. In particular, the simulation results of the designed FS-IGBT are highly fitted to the datasheet of the commercial device, which verifies the generalizability and effectiveness of the method. In addition, comparative analyses with various algorithms show DE provides the fastest optimization and extraordinary robustness under the exact specifications. Crucially, the proposed design scheme aligns with semiconductor physics. The method simplifies IGBT design without the need for manual tuning and TCAD tool simulation.
{"title":"Efficient Automatic Design of IGBT Structural Parameters Using Differential Evolution and Machine Learning Model","authors":"Qing Yao;Jing Chen;Kemeng Yang;Jiafei Yao;Jun Zhang;Yuxuan Dai;Weihua Tang;Bo Zhang;Yufeng Guo","doi":"10.1109/TCAD.2024.3468011","DOIUrl":"https://doi.org/10.1109/TCAD.2024.3468011","url":null,"abstract":"Insulated gate bipolar transistors (IGBTs) are the key component in power electronics, and the intricate relationship between their performance and structural parameters poses a formidable challenge in the design process. This article proposes an automatic optimal design method for IGBT structural parameters to leverage the pretrained machine learning (ML) model to efficiently predict the initial IGBT device’s performance, followed by utilizing the differential evolution (DE) algorithm to automatically adjust structural parameters based on the disparity between predicted and expected device performance until the expected performance is achieved. The method is validated in the design of punch-through IGBTs (PT-IGBTs) and trench gate field-stop IGBTs (FS-IGBTs), and the performance of technology computer-aided design (TCAD) simulation of the designed device is similar to the target performance. In particular, the simulation results of the designed FS-IGBT are highly fitted to the datasheet of the commercial device, which verifies the generalizability and effectiveness of the method. In addition, comparative analyses with various algorithms show DE provides the fastest optimization and extraordinary robustness under the exact specifications. Crucially, the proposed design scheme aligns with semiconductor physics. The method simplifies IGBT design without the need for manual tuning and TCAD tool simulation.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"44 3","pages":"1059-1069"},"PeriodicalIF":2.7,"publicationDate":"2024-09-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143455326","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-25DOI: 10.1109/TCAD.2024.3468016
Haoyang Sun;Cong Jiang;Xun Ye;Dan Feng;Benjamin Tan;Yuzhe Ma;Kang Liu
As the technology node develops toward its physical limit, lithographic hotspot detection has become increasingly important and ever-challenging in the computer-aided design (CAD) flow. In recent years, convolutional neural networks (CNNs) have achieved great success in hotspot detection. However, the interpretability of their hotspot prediction has yet to be considered. Compared with conventional lithography simulation and pattern matching-based methods, the black-box nature of CNNs wavers their practical applications with confidence. In this article, we propose the first interpretable CNN-based hotspot detector capable of providing high-detection accuracy and reliable explanations for hotspot identification. Specifically, we augment the training dataset with expanded error markers obtained and preprocessed from lithography simulation, which are then learned by an encoder-decoder architecture as intermediate features. We additionally introduce coordinate attention in the encoder to facilitate better-feature extraction. By learning these error markers and part of their surrounding metals as root cause hotspot features, our architecture achieves the highest-hotspot accuracy of 99.78% and the lowest-false positive rate of 5.29% compared to all prior work. Moreover, our method demonstrates the best visual and quantitative interpretability results when applying CNN interpretation methods.
{"title":"Interpretable CNN-Based Lithographic Hotspot Detection Through Error Marker Learning","authors":"Haoyang Sun;Cong Jiang;Xun Ye;Dan Feng;Benjamin Tan;Yuzhe Ma;Kang Liu","doi":"10.1109/TCAD.2024.3468016","DOIUrl":"https://doi.org/10.1109/TCAD.2024.3468016","url":null,"abstract":"As the technology node develops toward its physical limit, lithographic hotspot detection has become increasingly important and ever-challenging in the computer-aided design (CAD) flow. In recent years, convolutional neural networks (CNNs) have achieved great success in hotspot detection. However, the interpretability of their hotspot prediction has yet to be considered. Compared with conventional lithography simulation and pattern matching-based methods, the black-box nature of CNNs wavers their practical applications with confidence. In this article, we propose the first interpretable CNN-based hotspot detector capable of providing high-detection accuracy and reliable explanations for hotspot identification. Specifically, we augment the training dataset with expanded error markers obtained and preprocessed from lithography simulation, which are then learned by an encoder-decoder architecture as intermediate features. We additionally introduce coordinate attention in the encoder to facilitate better-feature extraction. By learning these error markers and part of their surrounding metals as root cause hotspot features, our architecture achieves the highest-hotspot accuracy of 99.78% and the lowest-false positive rate of 5.29% compared to all prior work. Moreover, our method demonstrates the best visual and quantitative interpretability results when applying CNN interpretation methods.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"44 3","pages":"1031-1044"},"PeriodicalIF":2.7,"publicationDate":"2024-09-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143455325","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-23DOI: 10.1109/TCAD.2024.3466809
Po-Yao Chuang;Francesco Lorenzelli;Cheng-Wen Wu;Erik Jan Marinissen
Chiplet-based (2.5-D and 3-D) multidie packages typically feature numerous die-to-die interconnects using micro-bump connections and possibly through-silicon vias or interposer wires, which are prone to manufacturing defects, such as shorts and opens, in both hard and weak (resistive) variants. Traditional I-ATPG methods only cover hard defects and scale with the logarithm of the number of interconnects. Despite being considered efficient, they cover shorts between all interconnects, including those for which shorts are unrealistic given their relative layout positions. This article proposes E2I-TEST, which covers all hard and weak variants of open defects and of only the shorts and coupling defects between physically adjacent interconnects for both 3-D and 2.5-D chips, while preventing aliasing during fault diagnosis. This article further improves E2I-TEST to prevent ground bounce, avoiding undesired voltage fluctuations during test mode. While the number of interconnects is expected to rise significantly, E2I-TEST offers a high-quality interconnect test, while maintaining a constant number of test patterns.
{"title":"Generating Test Patterns for Chiplet Interconnects With Optimized Effectiveness and Efficiency","authors":"Po-Yao Chuang;Francesco Lorenzelli;Cheng-Wen Wu;Erik Jan Marinissen","doi":"10.1109/TCAD.2024.3466809","DOIUrl":"https://doi.org/10.1109/TCAD.2024.3466809","url":null,"abstract":"Chiplet-based (2.5-D and 3-D) multidie packages typically feature numerous die-to-die interconnects using micro-bump connections and possibly through-silicon vias or interposer wires, which are prone to manufacturing defects, such as shorts and opens, in both hard and weak (resistive) variants. Traditional I-ATPG methods only cover hard defects and scale with the logarithm of the number of interconnects. Despite being considered efficient, they cover shorts between all interconnects, including those for which shorts are unrealistic given their relative layout positions. This article proposes E2I-TEST, which covers all hard and weak variants of open defects and of only the shorts and coupling defects between physically adjacent interconnects for both 3-D and 2.5-D chips, while preventing aliasing during fault diagnosis. This article further improves E2I-TEST to prevent ground bounce, avoiding undesired voltage fluctuations during test mode. While the number of interconnects is expected to rise significantly, E2I-TEST offers a high-quality interconnect test, while maintaining a constant number of test patterns.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"44 3","pages":"1155-1168"},"PeriodicalIF":2.7,"publicationDate":"2024-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143465617","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
With advances in technology scaling and globalization of the semiconductor industry, the vulnerability of analog integrated circuits (ICs) to reverse-engineering-based attacks, intellectual property theft, and unauthorized access has increased. Prior state-of-the-art analog deobfuscation techniques, such as those using genetic algorithms (GAs) and the satisfiability modulo theory, require an Oracle (i.e., unlocked IC) to recover the correct key. However, in some scenarios, an attacker present in an untrusted foundry might not have access to the Oracle. We demonstrate an Oracle-less attack using Bayesian optimization (BO) to retrieve the key of locked analog designs. To thwart both Oracle-guided and Oracle-less attacks, we present an automated obfuscation circuit generation framework for securing analog ICs. By employing randomness in obfuscation circuit generation, the proposed analog key-based methodology safeguards the integrity and reliability of analog ICs. Experimental results and security analysis for several analog designs demonstrate the robustness of the proposed technique to optimization attacks based on a GA and BO. We further show that the probability of guessing the correct key through brute force attack for an obfuscated analog circuit is negligibly small $(4.83times 10^{-18})$ . The proposed obfuscation scheme incurs an area overhead of less than 1.3% and power overhead of less than 2.64% for a mixed-signal IC.
{"title":"Enhancing Analog IC Security Using Randomized Obfuscation Circuits","authors":"Jayeeta Chaudhuri;Mayukh Bhattacharya;Krishnendu Chakrabarty","doi":"10.1109/TCAD.2024.3466810","DOIUrl":"https://doi.org/10.1109/TCAD.2024.3466810","url":null,"abstract":"With advances in technology scaling and globalization of the semiconductor industry, the vulnerability of analog integrated circuits (ICs) to reverse-engineering-based attacks, intellectual property theft, and unauthorized access has increased. Prior state-of-the-art analog deobfuscation techniques, such as those using genetic algorithms (GAs) and the satisfiability modulo theory, require an Oracle (i.e., unlocked IC) to recover the correct key. However, in some scenarios, an attacker present in an untrusted foundry might not have access to the Oracle. We demonstrate an Oracle-less attack using Bayesian optimization (BO) to retrieve the key of locked analog designs. To thwart both Oracle-guided and Oracle-less attacks, we present an automated obfuscation circuit generation framework for securing analog ICs. By employing randomness in obfuscation circuit generation, the proposed analog key-based methodology safeguards the integrity and reliability of analog ICs. Experimental results and security analysis for several analog designs demonstrate the robustness of the proposed technique to optimization attacks based on a GA and BO. We further show that the probability of guessing the correct key through brute force attack for an obfuscated analog circuit is negligibly small <inline-formula> <tex-math>$(4.83times 10^{-18})$ </tex-math></inline-formula>. The proposed obfuscation scheme incurs an area overhead of less than 1.3% and power overhead of less than 2.64% for a mixed-signal IC.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"44 3","pages":"867-881"},"PeriodicalIF":2.7,"publicationDate":"2024-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143455358","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-19DOI: 10.1109/TCAD.2024.3454934
{"title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information","authors":"","doi":"10.1109/TCAD.2024.3454934","DOIUrl":"https://doi.org/10.1109/TCAD.2024.3454934","url":null,"abstract":"","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"43 10","pages":"C2-C2"},"PeriodicalIF":2.7,"publicationDate":"2024-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10684353","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142246472","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-19DOI: 10.1109/TCAD.2024.3449609
{"title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information","authors":"","doi":"10.1109/TCAD.2024.3449609","DOIUrl":"https://doi.org/10.1109/TCAD.2024.3449609","url":null,"abstract":"","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"43 10","pages":"C3-C3"},"PeriodicalIF":2.7,"publicationDate":"2024-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10684352","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142276469","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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