Pub Date : 2025-06-04DOI: 10.1109/TCAD.2025.3576319
Irith Pomeranz
State-of-the-art technologies exhibit a variety of defects requiring test sets that detect a variety of fault models. Such a test set is large, and tests at the end of the test set detect small numbers of additional faults. Procedures that steepen the fault coverage curve help address constraints on test application time and test data volume of large test sets. Existing steepening procedures move tests detecting more faults to earlier positions of the test set. Such procedures are referred to as forward steepening procedures. This article takes a complementary view that results in a reverse steepening procedure. The procedure moves tests detecting fewer additional faults to later positions. Indirectly, it causes tests detecting more faults to appear in earlier positions. Experimental results for benchmark circuits in an academic simulation environment demonstrate the effectiveness of the reverse steepening procedure as a standalone procedure, and as part of a procedure that reduces the test data volume without reducing the fault coverage.
{"title":"Reverse Steepening of a Fault Coverage Curve","authors":"Irith Pomeranz","doi":"10.1109/TCAD.2025.3576319","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3576319","url":null,"abstract":"State-of-the-art technologies exhibit a variety of defects requiring test sets that detect a variety of fault models. Such a test set is large, and tests at the end of the test set detect small numbers of additional faults. Procedures that steepen the fault coverage curve help address constraints on test application time and test data volume of large test sets. Existing steepening procedures move tests detecting more faults to earlier positions of the test set. Such procedures are referred to as forward steepening procedures. This article takes a complementary view that results in a reverse steepening procedure. The procedure moves tests detecting fewer additional faults to later positions. Indirectly, it causes tests detecting more faults to appear in earlier positions. Experimental results for benchmark circuits in an academic simulation environment demonstrate the effectiveness of the reverse steepening procedure as a standalone procedure, and as part of a procedure that reduces the test data volume without reducing the fault coverage.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 1","pages":"557-561"},"PeriodicalIF":2.9,"publicationDate":"2025-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145904312","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Field programmable gate array (FPGA) logic synthesis compilers (e.g., Vivado, Iverilog, Yosys, and Quartus) are widely applied in electronic design automation (EDA), such as the development of FPGA programs. However, defects (e.g., incorrect synthesis) in logic synthesis compilers may lead to unexpected behaviors in target applications, posing security risks. Therefore, it is crucial to thoroughly test logic synthesis compilers to eliminate such defects. Despite several hardware design language (HDL) code generators (e.g., Verismith) having been proposed to find defects in logic synthesis compilers, the effectiveness of these generators is still limited by the simple code generation strategy and the monogeneity of the generated HDL code. This article proposes EvoHDL, a novel method to generate syntax-valid HDL code for comprehensively testing FPGA logic synthesis compilers. EvoHDL can generate more complex and diverse defect-triggering HDL code (e.g., Verilog, VHDL, and SystemVerilog) by leveraging the guidance of abstract syntax tree and the extensive function block libraries of cyber-physical systems. Extensive experiments show that the diversity and defect-triggering capability of HDL code generated by EvoHDL are significantly better than the state-of-the-art method (i.e., Verismith). In three months, EvoHDL has reported 20 new defects-many of which are deep and important; 16 of them have been confirmed.
{"title":"A Novel HDL Code Generator for Effectively Testing FPGA Logic Synthesis Compilers","authors":"Zhihao Xu;Shikai Guo;Guilin Zhao;Peiyu Zou;Xiaochen Li;He Jiang","doi":"10.1109/TCAD.2025.3565488","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3565488","url":null,"abstract":"Field programmable gate array (FPGA) logic synthesis compilers (e.g., Vivado, Iverilog, Yosys, and Quartus) are widely applied in electronic design automation (EDA), such as the development of FPGA programs. However, defects (e.g., incorrect synthesis) in logic synthesis compilers may lead to unexpected behaviors in target applications, posing security risks. Therefore, it is crucial to thoroughly test logic synthesis compilers to eliminate such defects. Despite several hardware design language (HDL) code generators (e.g., Verismith) having been proposed to find defects in logic synthesis compilers, the effectiveness of these generators is still limited by the simple code generation strategy and the monogeneity of the generated HDL code. This article proposes EvoHDL, a novel method to generate syntax-valid HDL code for comprehensively testing FPGA logic synthesis compilers. EvoHDL can generate more complex and diverse defect-triggering HDL code (e.g., Verilog, VHDL, and SystemVerilog) by leveraging the guidance of abstract syntax tree and the extensive function block libraries of cyber-physical systems. Extensive experiments show that the diversity and defect-triggering capability of HDL code generated by EvoHDL are significantly better than the state-of-the-art method (i.e., Verismith). In three months, EvoHDL has reported 20 new defects-many of which are deep and important; 16 of them have been confirmed.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"44 11","pages":"4405-4418"},"PeriodicalIF":2.9,"publicationDate":"2025-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145335316","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-29DOI: 10.1109/TCAD.2025.3565473
Sungju Kim;Hyungcheol Shin
This study proposes new physics-based terminal capacitance models derived from the select gate (SG) channel potential in the gate-induced drain leakage (GIDL)-assisted 3-D NAND Flash string. These models accurately predict the transient behavior of the string across various SG voltage (VSG) ramps, showing good agreement with computer-aided design (TCAD) simulation results. Their closed-form solutions eliminate iterative calculations, ensuring simulation program with integrated circuit emphasis (SPICE) compatibility and enabling monte-carlo (MC) simulations that account for various process variations and voltage ramp conditions. This approach provides critical insights into optimizing GIDL-assisted erase performance, advancing both the reliability and efficiency of next-generation 3-D NAND Flash memory.
{"title":"Closed-Form Capacitance Network Compact Model and Monte Carlo Analysis of the GIDL-Assisted Potential Growth in 3-D NAND Flash String","authors":"Sungju Kim;Hyungcheol Shin","doi":"10.1109/TCAD.2025.3565473","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3565473","url":null,"abstract":"This study proposes new physics-based terminal capacitance models derived from the select gate (SG) channel potential in the gate-induced drain leakage (GIDL)-assisted 3-D NAND Flash string. These models accurately predict the transient behavior of the string across various SG voltage (VSG) ramps, showing good agreement with computer-aided design (TCAD) simulation results. Their closed-form solutions eliminate iterative calculations, ensuring simulation program with integrated circuit emphasis (SPICE) compatibility and enabling monte-carlo (MC) simulations that account for various process variations and voltage ramp conditions. This approach provides critical insights into optimizing GIDL-assisted erase performance, advancing both the reliability and efficiency of next-generation 3-D NAND Flash memory.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"44 11","pages":"4438-4442"},"PeriodicalIF":2.9,"publicationDate":"2025-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145335323","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-29DOI: 10.1109/TCAD.2025.3565466
Ahmed Mamdouh;Haoran Geng;Michael Niemier;Xiaobo Sharon Hu;Dayane Reis
Processing-in-memory (PIM) enhances memory with computational capabilities, potentially solving energy and latency issues associated with data transfer between memory and processors. However, managing concurrent computation and data flow within the PIM architecture incurs significant latency and energy penalty for applications. This article introduces Shared-PIM, an architecture for in-dynamic random-access memory (DRAM) PIM that strategically allocates rows in memory banks, bolstered by memory peripherals, for concurrent processing and data movement. Shared-PIM enables simultaneous computation and data transfer within a memory bank. When compared to LISA, a state-of-the-art (SOTA) architecture that facilitates data transfers for in-DRAM PIM, Shared-PIM reduces data movement latency and energy by $5times $ and $1.2times $ , respectively. Furthermore, when integrated to a SOTA in-DRAM PIM architecture (pLUTo), Shared-PIM achieves $1.4times $ faster addition and multiplication, and thereby improves the performance of matrix multiplication (MM) tasks by 40%, polynomial multiplication (PMM) by 44%, and numeric number transfer (NTT) tasks by 31%. Moreover, for graph processing tasks like breadth-first search (BFS) and depth-first search (DFS), Shared-PIM achieves a 29% improvement in speed, all with an area overhead of just 7.16% compared to the baseline pLUTo.
{"title":"Shared-PIM: Enabling Concurrent Computation and Data Flow for Faster Processing-in-DRAM","authors":"Ahmed Mamdouh;Haoran Geng;Michael Niemier;Xiaobo Sharon Hu;Dayane Reis","doi":"10.1109/TCAD.2025.3565466","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3565466","url":null,"abstract":"Processing-in-memory (PIM) enhances memory with computational capabilities, potentially solving energy and latency issues associated with data transfer between memory and processors. However, managing concurrent computation and data flow within the PIM architecture incurs significant latency and energy penalty for applications. This article introduces Shared-PIM, an architecture for in-dynamic random-access memory (DRAM) PIM that strategically allocates rows in memory banks, bolstered by memory peripherals, for concurrent processing and data movement. Shared-PIM enables simultaneous computation and data transfer within a memory bank. When compared to LISA, a state-of-the-art (SOTA) architecture that facilitates data transfers for in-DRAM PIM, Shared-PIM reduces data movement latency and energy by <inline-formula> <tex-math>$5times $ </tex-math></inline-formula> and <inline-formula> <tex-math>$1.2times $ </tex-math></inline-formula>, respectively. Furthermore, when integrated to a SOTA in-DRAM PIM architecture (pLUTo), Shared-PIM achieves <inline-formula> <tex-math>$1.4times $ </tex-math></inline-formula> faster addition and multiplication, and thereby improves the performance of matrix multiplication (MM) tasks by 40%, polynomial multiplication (PMM) by 44%, and numeric number transfer (NTT) tasks by 31%. Moreover, for graph processing tasks like breadth-first search (BFS) and depth-first search (DFS), Shared-PIM achieves a 29% improvement in speed, all with an area overhead of just 7.16% compared to the baseline pLUTo.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"44 11","pages":"4395-4404"},"PeriodicalIF":2.9,"publicationDate":"2025-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145335324","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-22DOI: 10.1109/TCAD.2025.3558209
{"title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information","authors":"","doi":"10.1109/TCAD.2025.3558209","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3558209","url":null,"abstract":"","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"44 5","pages":"C3-C3"},"PeriodicalIF":2.7,"publicationDate":"2025-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10973770","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143860884","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-22DOI: 10.1109/TCAD.2025.3558207
{"title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information","authors":"","doi":"10.1109/TCAD.2025.3558207","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3558207","url":null,"abstract":"","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"44 5","pages":"C2-C2"},"PeriodicalIF":2.7,"publicationDate":"2025-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10974374","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143871022","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Corrections to “A Bidirectional Deep Learning Approach for Designing MEMS Sensors”","authors":"Xiong Cheng;Pengfei Zhang;Yiqi Zhou;Daying Sun;Wenhua Gu;Yutao Yue;Xiaodong Huang","doi":"10.1109/TCAD.2025.3528617","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3528617","url":null,"abstract":"","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"44 5","pages":"2026-2027"},"PeriodicalIF":2.7,"publicationDate":"2025-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10973771","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143860817","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Monolithic 3-D (M3D) integration for integrated circuits (ICs) offers the promise of higher performance and lower power consumption over stacked-3D ICs. However, M3D suffers from large power supply noise (PSN) in the power distribution network due to high current demand and long conduction paths from voltage sources to local receivers. Excessive switching activities during the capture cycles in at-speed delay testing exacerbate the PSN-induced voltage droop problem. Therefore, PSN reduction is necessary for M3D ICs during testing to prevent the failure of good chips on the tester (i.e., yield loss). In this article, we first develop an analysis flow for M3D designs to compute the PSN-induced voltage droop. Based on the analysis results, we extract the test patterns that are likely to cause yield loss. Next, we propose a reinforcement learning (RL)-based framework to insert test points and generate low-switching patterns that help in mitigating PSN without degrading the test coverage. Simulation results for benchmark M3D designs demonstrate the effectiveness of the proposed power-safe testing approach, compared to baseline cases that utilize commercial tools.
{"title":"Reinforcement-Learning-Based Test Point Insertion for Power-Safe Testing in Monolithic 3-D ICs","authors":"Shao-Chun Hung;Arjun Chaudhuri;Krishnendu Chakrabarty","doi":"10.1109/TCAD.2025.3562950","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3562950","url":null,"abstract":"Monolithic 3-D (M3D) integration for integrated circuits (ICs) offers the promise of higher performance and lower power consumption over stacked-3D ICs. However, M3D suffers from large power supply noise (PSN) in the power distribution network due to high current demand and long conduction paths from voltage sources to local receivers. Excessive switching activities during the capture cycles in at-speed delay testing exacerbate the PSN-induced voltage droop problem. Therefore, PSN reduction is necessary for M3D ICs during testing to prevent the failure of good chips on the tester (i.e., yield loss). In this article, we first develop an analysis flow for M3D designs to compute the PSN-induced voltage droop. Based on the analysis results, we extract the test patterns that are likely to cause yield loss. Next, we propose a reinforcement learning (RL)-based framework to insert test points and generate low-switching patterns that help in mitigating PSN without degrading the test coverage. Simulation results for benchmark M3D designs demonstrate the effectiveness of the proposed power-safe testing approach, compared to baseline cases that utilize commercial tools.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"44 11","pages":"4419-4432"},"PeriodicalIF":2.9,"publicationDate":"2025-04-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145335289","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Field-programmable gate array (FPGA) macro placement holds a crucial role within the FPGA physical design flow since it substantially influences the subsequent stages of cell placement and routing. With the increasing number of macros and the complex cascade shape and region constraints imposed by modern FPGAs, the routability and macro placement have become much more challenging. In this article, we propose an effective and efficient routability-driven macro placement algorithm for modern FPGAs with cascade shape and region constraints. To reserve adequate space for cell placement and guarantee routability, we first develop a routability-driven mixed-size analytical global placement that evenly distributes both macros and cells while considering cascade shape and region constraints. Particularly, the proposed global placement engine integrates a well-trained congestion prediction model, targeting benchmarks with high routing congestion to enhance overall routability. Then, we propose an integer linear programming (ILP)-based cascade shape legalization followed by matching-based macro legalization to remove macro overlaps while satisfying the region constraints. Finally, a routability-driven detailed macro placement is proposed to refine the solution. Compared with the winners of the MLCAD 2023 FPGA macro placement contest and state-of-the-art works, experimental results show that our algorithm achieves the best overall score and routability.
{"title":"Routability-Driven Macro Placement Engine for Modern FPGAs With Complex Cascade Shape and Region Constraints","authors":"Hao Gu;Jian Gu;Keyu Peng;Jianli Chen;Jun Yang;Ziran Zhu","doi":"10.1109/TCAD.2025.3562952","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3562952","url":null,"abstract":"Field-programmable gate array (FPGA) macro placement holds a crucial role within the FPGA physical design flow since it substantially influences the subsequent stages of cell placement and routing. With the increasing number of macros and the complex cascade shape and region constraints imposed by modern FPGAs, the routability and macro placement have become much more challenging. In this article, we propose an effective and efficient routability-driven macro placement algorithm for modern FPGAs with cascade shape and region constraints. To reserve adequate space for cell placement and guarantee routability, we first develop a routability-driven mixed-size analytical global placement that evenly distributes both macros and cells while considering cascade shape and region constraints. Particularly, the proposed global placement engine integrates a well-trained congestion prediction model, targeting benchmarks with high routing congestion to enhance overall routability. Then, we propose an integer linear programming (ILP)-based cascade shape legalization followed by matching-based macro legalization to remove macro overlaps while satisfying the region constraints. Finally, a routability-driven detailed macro placement is proposed to refine the solution. Compared with the winners of the MLCAD 2023 FPGA macro placement contest and state-of-the-art works, experimental results show that our algorithm achieves the best overall score and routability.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"44 11","pages":"4381-4394"},"PeriodicalIF":2.9,"publicationDate":"2025-04-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145335332","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this work, we propose a novel post-layout netlist simplification, modeling, and agile electromigration (EM) analysis framework. First, we implement a hierarchical parasitic extraction strategy to partition the top-level post-layout netlist into functional modules, followed by a worst-case circuit analysis to quickly identify wires with potential for EM violations within each module. Next, the feedforward neural networks (FFNs) and long short-term memory (LSTM) models are employed to construct circuit behavioral models encompassing the input-output behavior and current responses of specified internal nodes. These models are subsequently converted into Verilog-A format for transistor-level simulation. Finally, we substitute the modules with generated Verilog-A models to reduce the circuit complexity. Our framework can significantly accelerate the simulation and EM analysis under different excitation signals. The experiments show that our framework yields up to $38.02times $ speedup in simulation time required for transistor-level EM analysis over the commercial tool, together with excellent accuracy.
{"title":"Hierarchical Behavioral Learning-Based Dynamic Electromigration Analysis for Signal Networks","authors":"Yupeng Hu;Yapeng Li;Jindong Tu;Tinghuan Chen;Qi Sun;Cheng Zhuo","doi":"10.1109/TCAD.2025.3560586","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3560586","url":null,"abstract":"In this work, we propose a novel post-layout netlist simplification, modeling, and agile electromigration (EM) analysis framework. First, we implement a hierarchical parasitic extraction strategy to partition the top-level post-layout netlist into functional modules, followed by a worst-case circuit analysis to quickly identify wires with potential for EM violations within each module. Next, the feedforward neural networks (FFNs) and long short-term memory (LSTM) models are employed to construct circuit behavioral models encompassing the input-output behavior and current responses of specified internal nodes. These models are subsequently converted into Verilog-A format for transistor-level simulation. Finally, we substitute the modules with generated Verilog-A models to reduce the circuit complexity. Our framework can significantly accelerate the simulation and EM analysis under different excitation signals. The experiments show that our framework yields up to <inline-formula> <tex-math>$38.02times $ </tex-math></inline-formula> speedup in simulation time required for transistor-level EM analysis over the commercial tool, together with excellent accuracy.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"44 11","pages":"4433-4437"},"PeriodicalIF":2.9,"publicationDate":"2025-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145335288","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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