Advancements in emerging technologies have recently increased the traction of non-von Neumann design styles. One of the most popular design styles in this domain involves using memristors to perform logic operations in memory, known as logic-in-memory (LiM). memristor aided logic (MAGIC) is one of such LiM based design style that is widely used given its benefits in latency and energy. Several prior works have focused on the generation of logic operations, also called micro-operations, for LiM based on the MAGIC design style. Recently, the generation of SPICE netlists for MAGIC design style has been achieved by the MemSPICE tool. While this represents a significant step forward, verifying the correctness of the generated netlists still depends on SPICE-level simulations. These simulations become particularly impractical for medium-to-large designs presenting a bottleneck in the validation process. To address this limitation, in this article, we introduce veriSiM, an automated formal verification methodology for MAGIC-based LiM. More concretely, it ensures the correctness of the generated LiM SPICE netlists against the golden reference Verilog design. Our methodology involves generating clauses from the SPICE netlists and verifying them against clauses generated from the golden reference Verilog design, using the high-performance Z3 solver to perform the equivalence checking. The clause generation process from the SPICE netlists needs to be based on several conditions, which have been identified and discussed in detail. We have used several benchmarks from ISCAS’85, ISCAS’89, and ITC’99 to demonstrate the efficacy of the veriSiM methodology in formally verifying the LiM SPICE netlists.
{"title":"veriSiM: Formal Verification of SPICE Netlists for MAGIC-Based Logic-in-Memory","authors":"Chandan Kumar Jha;Simranjeet Singh;Khushboo Qayyum;Ankit Bende;Muhammad Hassan;Vikas Rana;Farhad Merchant;Rolf Drechsler","doi":"10.1109/TCAD.2025.3583199","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3583199","url":null,"abstract":"Advancements in emerging technologies have recently increased the traction of non-von Neumann design styles. One of the most popular design styles in this domain involves using memristors to perform logic operations in memory, known as logic-in-memory (LiM). memristor aided logic (MAGIC) is one of such LiM based design style that is widely used given its benefits in latency and energy. Several prior works have focused on the generation of logic operations, also called micro-operations, for LiM based on the MAGIC design style. Recently, the generation of SPICE netlists for MAGIC design style has been achieved by the MemSPICE tool. While this represents a significant step forward, verifying the correctness of the generated netlists still depends on SPICE-level simulations. These simulations become particularly impractical for medium-to-large designs presenting a bottleneck in the validation process. To address this limitation, in this article, we introduce veriSiM, an automated formal verification methodology for MAGIC-based LiM. More concretely, it ensures the correctness of the generated LiM SPICE netlists against the golden reference Verilog design. Our methodology involves generating clauses from the SPICE netlists and verifying them against clauses generated from the golden reference Verilog design, using the high-performance Z3 solver to perform the equivalence checking. The clause generation process from the SPICE netlists needs to be based on several conditions, which have been identified and discussed in detail. We have used several benchmarks from ISCAS’85, ISCAS’89, and ITC’99 to demonstrate the efficacy of the veriSiM methodology in formally verifying the LiM SPICE netlists.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 2","pages":"845-854"},"PeriodicalIF":2.9,"publicationDate":"2025-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146006865","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-06-23DOI: 10.1109/TCAD.2025.3582196
Kanghyun Choi;Deokki Hong;Hyeyoon Lee;Joonsang Yu;Noseong Park;Youngsok Kim;Jinho Lee
Co-exploration of neural architectures and hardware accelerators has emerged as a promising approach to address computational cost problems, especially in low-profile systems. However, existing co-exploration methods based on reinforcement learning or evolutionary search suffer from substantial search costs. To address this, this work presents DANCE++, a differentiable approach toward the co-exploration of hardware and network architecture design. At the heart of DANCE++ is a differentiable evaluator network that models hardware metrics with a neural network, enabling accelerator design through backpropagation. DANCE++ significantly reduces search time and enhances accuracy and hardware cost metrics compared to traditional approaches. To further address real-world scenarios, this work embodies two important practical topics: 1) hard constraints and 2) data dependency. To meet the constraints, such as frame rates, this work proposes a gradient manipulation algorithm that guides differentiable optimization to find hard-constrained solutions. Also to consider cases where training dataset is inaccessible, this work proposes to use data-free training methods in both co-exploration and training phases. To the best of our knowledge, DANCE++ is the first co-exploration method that targets these real-world challenges, supported by extensive experiments demonstrating its effectiveness.
{"title":"DANCE++: Differentiable Accelerator/Network Co-Exploration With Hard Constraints and Data-Free Training for Real-World Scenarios","authors":"Kanghyun Choi;Deokki Hong;Hyeyoon Lee;Joonsang Yu;Noseong Park;Youngsok Kim;Jinho Lee","doi":"10.1109/TCAD.2025.3582196","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3582196","url":null,"abstract":"Co-exploration of neural architectures and hardware accelerators has emerged as a promising approach to address computational cost problems, especially in low-profile systems. However, existing co-exploration methods based on reinforcement learning or evolutionary search suffer from substantial search costs. To address this, this work presents DANCE++, a differentiable approach toward the co-exploration of hardware and network architecture design. At the heart of DANCE++ is a differentiable evaluator network that models hardware metrics with a neural network, enabling accelerator design through backpropagation. DANCE++ significantly reduces search time and enhances accuracy and hardware cost metrics compared to traditional approaches. To further address real-world scenarios, this work embodies two important practical topics: 1) hard constraints and 2) data dependency. To meet the constraints, such as frame rates, this work proposes a gradient manipulation algorithm that guides differentiable optimization to find hard-constrained solutions. Also to consider cases where training dataset is inaccessible, this work proposes to use data-free training methods in both co-exploration and training phases. To the best of our knowledge, DANCE++ is the first co-exploration method that targets these real-world challenges, supported by extensive experiments demonstrating its effectiveness.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 2","pages":"915-928"},"PeriodicalIF":2.9,"publicationDate":"2025-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146006923","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-06-20DOI: 10.1109/TCAD.2025.3581866
Pooja Joshi;Anindita Chakraborty;Hafizur Rahaman
Partitioning memristive crossbar is emerging as a new technique for improving computational throughput, and overcoming tradeoffs in memristive processing-in-memory (PIM) architecture. This article presents a complete framework for realizing logic functions inside a partitioned memristive crossbar. This work utilizes a heuristic-based clustering algorithm on and-inverter graphs (AIGs) to minimize the number of lookup tables (LUTs) necessary for mapping Boolean logic functions. In our proposed mapping technique, LUTs are evaluated using single-row memristor aided logic (MAGIC)-based norgates, and mapped inside the partitioned memristive crossbar. The peripheral design for partitioned crossbar utilizes a shared CMOS decoder, and generates Opcodes to control logic computation across all partitions. The experimental results show an average throughput improvement of $12.58{times }$ , $68.47{times }$ , $156.10{times }$ , $107.76{times }$ , and $506.22{times }$ over SIMPLER, ReVAMP-ArC, ReVAMP-DeC, m-AIG-based mapping technique, and CoMIC-3D mapping, respectively. In addition, on average, a 47.4% reduction in computation area is observed.
{"title":"LUT-Based Mapping of Logic Functions to Partitioned Memristive Crossbar Using MAGIC for High-Throughput Computing","authors":"Pooja Joshi;Anindita Chakraborty;Hafizur Rahaman","doi":"10.1109/TCAD.2025.3581866","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3581866","url":null,"abstract":"Partitioning memristive crossbar is emerging as a new technique for improving computational throughput, and overcoming tradeoffs in memristive processing-in-memory (PIM) architecture. This article presents a complete framework for realizing logic functions inside a partitioned memristive crossbar. This work utilizes a heuristic-based clustering algorithm on and-inverter graphs (AIGs) to minimize the number of lookup tables (LUTs) necessary for mapping Boolean logic functions. In our proposed mapping technique, LUTs are evaluated using single-row memristor aided logic (MAGIC)-based <sc>nor</small>gates, and mapped inside the partitioned memristive crossbar. The peripheral design for partitioned crossbar utilizes a shared CMOS decoder, and generates Opcodes to control logic computation across all partitions. The experimental results show an average throughput improvement of <inline-formula> <tex-math>$12.58{times }$ </tex-math></inline-formula>, <inline-formula> <tex-math>$68.47{times }$ </tex-math></inline-formula>, <inline-formula> <tex-math>$156.10{times }$ </tex-math></inline-formula>, <inline-formula> <tex-math>$107.76{times }$ </tex-math></inline-formula>, and <inline-formula> <tex-math>$506.22{times }$ </tex-math></inline-formula> over SIMPLER, ReVAMP-ArC, ReVAMP-DeC, m-AIG-based mapping technique, and CoMIC-3D mapping, respectively. In addition, on average, a 47.4% reduction in computation area is observed.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 1","pages":"359-372"},"PeriodicalIF":2.9,"publicationDate":"2025-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145904261","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-06-19DOI: 10.1109/TCAD.2025.3575827
{"title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information","authors":"","doi":"10.1109/TCAD.2025.3575827","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3575827","url":null,"abstract":"","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"44 7","pages":"C2-C2"},"PeriodicalIF":2.7,"publicationDate":"2025-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11044996","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144323110","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-06-19DOI: 10.1109/TCAD.2025.3581475
Yang Dai;Yukun Li;Leiyu Gao;Pengzhan Wang;Weiwei Li;Jing Zuo;Cheng Chen;Wu Zhao
The effect caused by asymmetric structures on the performance of the AlGaN/GaN bilateral impact-ionization-avalanche-transit-time (BIMPATT) device is studied in this article. The asymmetric structures include the asymmetry of the bilateral channel lengths by changing the anode position and the asymmetry of the 2-D electron gas (2-DEG) concentrations by changing the AlGaN thickness. The asymmetry affects the direct current (DC), radio frequency (RF), and noise characteristics of the BIMPATT. Large-signal analysis shows that the asymmetric structures improve the operating frequency but reduce the maximum power and efficiency of the BIMPATT. The asymmetric structures show better RF characteristics than the symmetric structure in the high-frequency band. At last, the asymmetric structures increase the noise performance of the BIMPATT. The reason for these phenomena is the asymmetry of avalanche ionization region and intensity caused by the asymmetry of device structure. This article provides more references for the design and performance optimization of the lateral IMPATT devices.
{"title":"Effect of Asymmetric Structures On the Performance of AlGaN/GaN Bilateral IMPATT Device","authors":"Yang Dai;Yukun Li;Leiyu Gao;Pengzhan Wang;Weiwei Li;Jing Zuo;Cheng Chen;Wu Zhao","doi":"10.1109/TCAD.2025.3581475","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3581475","url":null,"abstract":"The effect caused by asymmetric structures on the performance of the AlGaN/GaN bilateral impact-ionization-avalanche-transit-time (BIMPATT) device is studied in this article. The asymmetric structures include the asymmetry of the bilateral channel lengths by changing the anode position and the asymmetry of the 2-D electron gas (2-DEG) concentrations by changing the AlGaN thickness. The asymmetry affects the direct current (DC), radio frequency (RF), and noise characteristics of the BIMPATT. Large-signal analysis shows that the asymmetric structures improve the operating frequency but reduce the maximum power and efficiency of the BIMPATT. The asymmetric structures show better RF characteristics than the symmetric structure in the high-frequency band. At last, the asymmetric structures increase the noise performance of the BIMPATT. The reason for these phenomena is the asymmetry of avalanche ionization region and intensity caused by the asymmetry of device structure. This article provides more references for the design and performance optimization of the lateral IMPATT devices.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 1","pages":"335-344"},"PeriodicalIF":2.9,"publicationDate":"2025-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145904301","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-06-19DOI: 10.1109/TCAD.2025.3581474
Longze Wang;Wei W. Xing;Zhelong Wang;Christos Sotiriou;Nikolaos Sketopoulos;Ning Xu;Yuanqing Cheng
With the advancement of modern nanoscale technology nodes, static timing analysis (STA) has become an indispensable technique for ensuring circuit reliability and performance across diverse process conditions. However, traditional STA methods scale poorly to the explosion of process corners in the nanoscale fabrication technology. Despite some seminal works in using AI to accelerate such processes, they either lack reliability or stability. To this end, we introduce active self-attention neural process (ASAP), a novel approach addressing this challenge by combining both the latest deep learning methods and the classical Bayesian models to deliver scalable and accurate predictions with a self-calibration strategy to ensure reliability. Technically, the ASAP novelly integrates self-attention to help identify and prioritize crucial features under various input conditions and employs neural process to make confidence-based predictions for the final timing results. Furthermore, ASAP is equipped with Active Learning for self-refinement and self-correction. Experimental evaluations on benchmark circuits demonstrate that our method surpasses state-of-the-art work in STA accuracy by 18% in terms of prediction accuracy.
{"title":"ASAP: Accelerating Corner-Based Timing Analysis With Bayesian Active Self-Attention Neural Process","authors":"Longze Wang;Wei W. Xing;Zhelong Wang;Christos Sotiriou;Nikolaos Sketopoulos;Ning Xu;Yuanqing Cheng","doi":"10.1109/TCAD.2025.3581474","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3581474","url":null,"abstract":"With the advancement of modern nanoscale technology nodes, static timing analysis (STA) has become an indispensable technique for ensuring circuit reliability and performance across diverse process conditions. However, traditional STA methods scale poorly to the explosion of process corners in the nanoscale fabrication technology. Despite some seminal works in using AI to accelerate such processes, they either lack reliability or stability. To this end, we introduce active self-attention neural process (ASAP), a novel approach addressing this challenge by combining both the latest deep learning methods and the classical Bayesian models to deliver scalable and accurate predictions with a self-calibration strategy to ensure reliability. Technically, the ASAP novelly integrates self-attention to help identify and prioritize crucial features under various input conditions and employs neural process to make confidence-based predictions for the final timing results. Furthermore, ASAP is equipped with Active Learning for self-refinement and self-correction. Experimental evaluations on benchmark circuits demonstrate that our method surpasses state-of-the-art work in STA accuracy by 18% in terms of prediction accuracy.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 1","pages":"480-493"},"PeriodicalIF":2.9,"publicationDate":"2025-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145904294","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-06-19DOI: 10.1109/TCAD.2025.3572228
{"title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information","authors":"","doi":"10.1109/TCAD.2025.3572228","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3572228","url":null,"abstract":"","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"44 7","pages":"C3-C3"},"PeriodicalIF":2.7,"publicationDate":"2025-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11044979","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144322968","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-06-17DOI: 10.1109/TCAD.2025.3580511
Shanyi Li;Zhen Zhuang;Mingyu Liu;Weihua Sheng;Bei Yu;Tsung-Yi Ho
Due to the rapid expansion of printed circuit board (PCB) designs, accompanied by diverse design rules and specific constraints, there has been a substantial increase in manual design engineering efforts. To address this challenge, industries are seeking productivity improvements through automated placement techniques. However, existing placers primarily target VLSI placement and do not align well with PCBs’ unique characteristics. This mismatch arises from both the customization of PCBs and the complexity of the problem, which involves considering various constraints such as priorities, irregularities, and alignment. This article introduces HiePlace, an efficient mathematical-programming (MP)-based placement framework designed explicitly for PCBs. It aims to address the diverse constraints and achieve better performance. To address the issue of time-consuming computation in the direct MP-based algorithm, we present two innovative acceleration techniques: 1) in the initial stage, we introduce a dynamic programming approach to prioritize the placement of core components. This technique effectively reduces the solution space and enhances the overall placement quality and 2) in addition, we propose a relaxation algorithm to minimize the number of boolean variables and further narrow down the solution space. This approach enables more efficient placement results by considering the problem’s specific constraints. Experimental results show that the proposed framework produces $7.7times $ speed up and 66% cost reduction.
{"title":"HiePlace: Efficient Hierarchical PCB Placement","authors":"Shanyi Li;Zhen Zhuang;Mingyu Liu;Weihua Sheng;Bei Yu;Tsung-Yi Ho","doi":"10.1109/TCAD.2025.3580511","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3580511","url":null,"abstract":"Due to the rapid expansion of printed circuit board (PCB) designs, accompanied by diverse design rules and specific constraints, there has been a substantial increase in manual design engineering efforts. To address this challenge, industries are seeking productivity improvements through automated placement techniques. However, existing placers primarily target VLSI placement and do not align well with PCBs’ unique characteristics. This mismatch arises from both the customization of PCBs and the complexity of the problem, which involves considering various constraints such as priorities, irregularities, and alignment. This article introduces HiePlace, an efficient mathematical-programming (MP)-based placement framework designed explicitly for PCBs. It aims to address the diverse constraints and achieve better performance. To address the issue of time-consuming computation in the direct MP-based algorithm, we present two innovative acceleration techniques: 1) in the initial stage, we introduce a dynamic programming approach to prioritize the placement of core components. This technique effectively reduces the solution space and enhances the overall placement quality and 2) in addition, we propose a relaxation algorithm to minimize the number of boolean variables and further narrow down the solution space. This approach enables more efficient placement results by considering the problem’s specific constraints. Experimental results show that the proposed framework produces <inline-formula> <tex-math>$7.7times $ </tex-math></inline-formula> speed up and 66% cost reduction.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 1","pages":"428-440"},"PeriodicalIF":2.9,"publicationDate":"2025-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11039086","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145904266","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-06-16DOI: 10.1109/TCAD.2025.3580310
Xianrui Dou;Huaguo Liang;Zhengfeng Huang;Yingchun Lu;Tian Chen;Jun Liu
The immaturity of manufacturing processes often leads to a high incidence of defects in through-silicon vias (TSVs). Prebond TSV testing is essential for optimizing the yield of chip-based integrated circuits. However, current testing methods are limited by their incomprehensive fault coverage and difficulty detecting subtle defects. Furthermore, these methods exhibit significant performance variability due to changes in process angle, power supply voltage, and temperature (PVT). To overcome these limitations, this article introduces an innovative ring oscillator (RO)-based prebond test method specifically designed for TSVs, with a robust system for defect classification and grading. By sampling each node of the RO oscillating ring, the proposed method enhances the resolution of the Time-to-Digital Converter, thereby improving the defect detection capability. Additionally, a weak current source, constructed utilizing the unique properties of MOS transistors, enables the precise detection of open faults, resistive open defects with $R_{text {open}} geq 1.5~{mathrm {K}} {mathrm {Omega }}$ , and leakage defects with $R_{text {leak}} leq 10~{mathrm {G}} {mathrm {Omega }}$ . To further mitigate the impact of PVT variations on test results, this article integrates advanced machine learning techniques for defect classification and grading, providing valuable insights for fault bin classification and fault diagnosis. This innovative approach contributes significantly to the advancement of 3-D IC reliability assessment.
{"title":"Ring Oscillator-Based PreBond TSV Testing Method With Classification and Grading of Defects","authors":"Xianrui Dou;Huaguo Liang;Zhengfeng Huang;Yingchun Lu;Tian Chen;Jun Liu","doi":"10.1109/TCAD.2025.3580310","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3580310","url":null,"abstract":"The immaturity of manufacturing processes often leads to a high incidence of defects in through-silicon vias (TSVs). Prebond TSV testing is essential for optimizing the yield of chip-based integrated circuits. However, current testing methods are limited by their incomprehensive fault coverage and difficulty detecting subtle defects. Furthermore, these methods exhibit significant performance variability due to changes in process angle, power supply voltage, and temperature (PVT). To overcome these limitations, this article introduces an innovative ring oscillator (RO)-based prebond test method specifically designed for TSVs, with a robust system for defect classification and grading. By sampling each node of the RO oscillating ring, the proposed method enhances the resolution of the Time-to-Digital Converter, thereby improving the defect detection capability. Additionally, a weak current source, constructed utilizing the unique properties of MOS transistors, enables the precise detection of open faults, resistive open defects with <inline-formula> <tex-math>$R_{text {open}} geq 1.5~{mathrm {K}} {mathrm {Omega }}$ </tex-math></inline-formula>, and leakage defects with <inline-formula> <tex-math>$R_{text {leak}} leq 10~{mathrm {G}} {mathrm {Omega }}$ </tex-math></inline-formula>. To further mitigate the impact of PVT variations on test results, this article integrates advanced machine learning techniques for defect classification and grading, providing valuable insights for fault bin classification and fault diagnosis. This innovative approach contributes significantly to the advancement of 3-D IC reliability assessment.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 1","pages":"387-395"},"PeriodicalIF":2.9,"publicationDate":"2025-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145904284","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The application of machine learning techniques in side-channel analysis (SCA) has recently received increased attention. Finding the best hyperparameters to achieve optimal performance for machine learning models in SCA is still a challenging endeavor. In order to solve the problem, we present an efficient ensemble framework designed to support profiled SCA for attacking cryptographic devices with countermeasures. Our proposed framework can partially mitigate the impact of traditional countermeasures employed in cryptographic devices. Additionally, we introduce a novel voting method called elite voting, which leverages candidate keys with higher probabilities to recover the secret key and adjusts the voting weights for better candidate keys. Experimental results illustrate that our proposed framework can effectively recover the right key from cryptographic devices with countermeasures through multiple experiments. It enhances the signal-to-noise ratio of traces and successfully recovers the right key across various datasets. Furthermore, when compared to traditional methods, our elite voting method further enhances the performance of ensemble learning by reducing the number of traces needed to recover the secret key. It exhibits superior performance compared to other ensemble methods, as it can reduce the minimum required number of traces significantly.
{"title":"An Efficient Ensemble Framework to Assist Profiled Side-Channel Analysis by Machine Learning","authors":"Yaoling Ding;Yuwei Zhang;An Wang;Shaofei Sun;Congming Wei;Liehuang Zhu","doi":"10.1109/TCAD.2025.3580344","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3580344","url":null,"abstract":"The application of machine learning techniques in side-channel analysis (SCA) has recently received increased attention. Finding the best hyperparameters to achieve optimal performance for machine learning models in SCA is still a challenging endeavor. In order to solve the problem, we present an efficient ensemble framework designed to support profiled SCA for attacking cryptographic devices with countermeasures. Our proposed framework can partially mitigate the impact of traditional countermeasures employed in cryptographic devices. Additionally, we introduce a novel voting method called elite voting, which leverages candidate keys with higher probabilities to recover the secret key and adjusts the voting weights for better candidate keys. Experimental results illustrate that our proposed framework can effectively recover the right key from cryptographic devices with countermeasures through multiple experiments. It enhances the signal-to-noise ratio of traces and successfully recovers the right key across various datasets. Furthermore, when compared to traditional methods, our elite voting method further enhances the performance of ensemble learning by reducing the number of traces needed to recover the secret key. It exhibits superior performance compared to other ensemble methods, as it can reduce the minimum required number of traces significantly.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 1","pages":"494-505"},"PeriodicalIF":2.9,"publicationDate":"2025-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145904336","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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