Pub Date : 2023-01-01DOI: 10.1587/transele.2022cdp0005
Shota Nakabeppu, N. Yamasaki
SUMMARY It is very important to design an embedded real-time sys- tem as a fault-tolerant system to ensure dependability. In particular, when a power failure occurs, restart processing after power restoration is required in a real-time system using a conventional processor. Even if power is restored quickly, the restart process takes a long time and causes deadline misses. In order to design a fault-tolerant real-time system, it is necessary to have a processor that can resume operation in a short time immediately after power is restored, even if a power failure occurs at any time. Since current embedded real-time systems are required to execute many tasks, high schedulability for high throughput is also important. This paper proposes a non-stop microprocessor architecture to achieve a fault-tolerant real-time system. The non-stop microprocessor is designed so as to resume normal operation even if a power failure occurs at any time, to achieve little per- formance degradation for high schedulability even if checkpoint creations and restorations are performed many times, to control flexibly non-volatile devices through software configuration, and to ensure data consistency no matter when a checkpoint restoration is performed. The evaluation shows that the non-stop microprocessor can restore a checkpoint within 5 µ sec and almost hide the overhead of checkpoint creations. The non-stop mi- croprocessor with such capabilities will be an essential component of a fault-tolerant real-time system with high schedulability.
{"title":"Non-Stop Microprocessor for Fault-Tolerant Real-Time Systems","authors":"Shota Nakabeppu, N. Yamasaki","doi":"10.1587/transele.2022cdp0005","DOIUrl":"https://doi.org/10.1587/transele.2022cdp0005","url":null,"abstract":"SUMMARY It is very important to design an embedded real-time sys- tem as a fault-tolerant system to ensure dependability. In particular, when a power failure occurs, restart processing after power restoration is required in a real-time system using a conventional processor. Even if power is restored quickly, the restart process takes a long time and causes deadline misses. In order to design a fault-tolerant real-time system, it is necessary to have a processor that can resume operation in a short time immediately after power is restored, even if a power failure occurs at any time. Since current embedded real-time systems are required to execute many tasks, high schedulability for high throughput is also important. This paper proposes a non-stop microprocessor architecture to achieve a fault-tolerant real-time system. The non-stop microprocessor is designed so as to resume normal operation even if a power failure occurs at any time, to achieve little per- formance degradation for high schedulability even if checkpoint creations and restorations are performed many times, to control flexibly non-volatile devices through software configuration, and to ensure data consistency no matter when a checkpoint restoration is performed. The evaluation shows that the non-stop microprocessor can restore a checkpoint within 5 µ sec and almost hide the overhead of checkpoint creations. The non-stop mi- croprocessor with such capabilities will be an essential component of a fault-tolerant real-time system with high schedulability.","PeriodicalId":13259,"journal":{"name":"IEICE Trans. Electron.","volume":"5 1","pages":"365-381"},"PeriodicalIF":0.0,"publicationDate":"2023-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84665948","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-01-01DOI: 10.1587/transele.2022oms0002
R. Tanaka, S. Imai
{"title":"Biofuel Cell Fueled by Decomposing Cellulose Nanofiber to Glucose by Using Cellulase Enzyme","authors":"R. Tanaka, S. Imai","doi":"10.1587/transele.2022oms0002","DOIUrl":"https://doi.org/10.1587/transele.2022oms0002","url":null,"abstract":"","PeriodicalId":13259,"journal":{"name":"IEICE Trans. Electron.","volume":"1 1","pages":"262-265"},"PeriodicalIF":0.0,"publicationDate":"2023-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83346122","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-01-01DOI: 10.1587/transele.2022ecp5030
K. Hirayama, Yoshiyuki Yanagimoto, J. Sugisaka, T. Yasui
{"title":"Permittivity Estimation Based on Transmission Coefficient for Gaussian Beam in Free-Space Method","authors":"K. Hirayama, Yoshiyuki Yanagimoto, J. Sugisaka, T. Yasui","doi":"10.1587/transele.2022ecp5030","DOIUrl":"https://doi.org/10.1587/transele.2022ecp5030","url":null,"abstract":"","PeriodicalId":13259,"journal":{"name":"IEICE Trans. Electron.","volume":"21 1","pages":"335-343"},"PeriodicalIF":0.0,"publicationDate":"2023-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90188769","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-01-01DOI: 10.1587/transele.2021ecp5064
K. Kawai, N. Shinohara, T. Mitani
{"title":"Novel Structure of Single-Shunt Rectifier Circuit with Impedance Matching at Output Filter","authors":"K. Kawai, N. Shinohara, T. Mitani","doi":"10.1587/transele.2021ecp5064","DOIUrl":"https://doi.org/10.1587/transele.2021ecp5064","url":null,"abstract":"","PeriodicalId":13259,"journal":{"name":"IEICE Trans. Electron.","volume":"11 1","pages":"50-58"},"PeriodicalIF":0.0,"publicationDate":"2023-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78287463","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-01-01DOI: 10.1587/transele.2022ecs6009
D. Kim, Il-Tak Han, Tae-Wan Kim, Ho-Sang Kwon, Kyung-Tae Kim
{"title":"Optimization of Planar Subarray Structure Based on Random Search Method for Large Active Electronically Scanned Array Antenna","authors":"D. Kim, Il-Tak Han, Tae-Wan Kim, Ho-Sang Kwon, Kyung-Tae Kim","doi":"10.1587/transele.2022ecs6009","DOIUrl":"https://doi.org/10.1587/transele.2022ecs6009","url":null,"abstract":"","PeriodicalId":13259,"journal":{"name":"IEICE Trans. Electron.","volume":"11 1","pages":"184-187"},"PeriodicalIF":0.0,"publicationDate":"2023-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88522699","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-01-01DOI: 10.1587/transele.2022cdi0001
M. Nagata
SUMMARY Hardware oriented security and trust of semiconductor integrated circuit (IC) chips have been highly demanded. This paper outlines the requirements and recent developments in circuits and packaging systems of IC chips for security applications, with the particular emphasis on protections against physical implementation attacks. Power side channels are of undesired presence to crypto circuits once a crypto algorithm is implemented in Silicon, over power delivery networks (PDNs) on the frontside of a chip or even through the backside of a Si substrate, in the form of power voltage variation and electromagnetic wave emanation. Pre-ventive measures have been exploited with circuit design and packaging technologies
{"title":"Design of Circuits and Packaging Systems for Security Chips","authors":"M. Nagata","doi":"10.1587/transele.2022cdi0001","DOIUrl":"https://doi.org/10.1587/transele.2022cdi0001","url":null,"abstract":"SUMMARY Hardware oriented security and trust of semiconductor integrated circuit (IC) chips have been highly demanded. This paper outlines the requirements and recent developments in circuits and packaging systems of IC chips for security applications, with the particular emphasis on protections against physical implementation attacks. Power side channels are of undesired presence to crypto circuits once a crypto algorithm is implemented in Silicon, over power delivery networks (PDNs) on the frontside of a chip or even through the backside of a Si substrate, in the form of power voltage variation and electromagnetic wave emanation. Pre-ventive measures have been exploited with circuit design and packaging technologies","PeriodicalId":13259,"journal":{"name":"IEICE Trans. Electron.","volume":"9 1","pages":"345-351"},"PeriodicalIF":0.0,"publicationDate":"2023-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88107721","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-01-01DOI: 10.1587/transele.2022res0001
Tatsuya Ikeuchi, R. Sato, Y. Yamaguchi, H. Yamada
{"title":"Fundamental Study on Grasping Growth State of Paddy Rice Using Quad-Polarimetric SAR Data","authors":"Tatsuya Ikeuchi, R. Sato, Y. Yamaguchi, H. Yamada","doi":"10.1587/transele.2022res0001","DOIUrl":"https://doi.org/10.1587/transele.2022res0001","url":null,"abstract":"","PeriodicalId":13259,"journal":{"name":"IEICE Trans. Electron.","volume":"5 1","pages":"144-148"},"PeriodicalIF":0.0,"publicationDate":"2023-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73161063","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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