Modern hospitals are beginning to adopt E-HEALTH as efficient complements to the traditional healthcare services. To support the E-HEALTH services, a locatable, radiation-free and high-capacity communication system is urgently needed in hospitals. Power line communication (PLC) system can use the ubiquitous power line network to power the light-emitting diode (LED) lights while serving as the backbone network for the indoor visible light communication (VLC) systems naturally. In this paper, an integrated broadband power line and visible light communication systems with OFDM modulation is proposed for the indoor hospital applications. This gives a brand-new solution to replace the conventional wireless communication systems in hospitals.
{"title":"Indoor hospital communication systems: An integrated solution based on power line and visible light communication","authors":"Jian Song, Wenbo Ding, Fang Yang, Hui Yang, Jintao Wang, Xiaofei Wang, Xun Zhang","doi":"10.1109/FTFC.2014.6828620","DOIUrl":"https://doi.org/10.1109/FTFC.2014.6828620","url":null,"abstract":"Modern hospitals are beginning to adopt E-HEALTH as efficient complements to the traditional healthcare services. To support the E-HEALTH services, a locatable, radiation-free and high-capacity communication system is urgently needed in hospitals. Power line communication (PLC) system can use the ubiquitous power line network to power the light-emitting diode (LED) lights while serving as the backbone network for the indoor visible light communication (VLC) systems naturally. In this paper, an integrated broadband power line and visible light communication systems with OFDM modulation is proposed for the indoor hospital applications. This gives a brand-new solution to replace the conventional wireless communication systems in hospitals.","PeriodicalId":138166,"journal":{"name":"2014 IEEE Faible Tension Faible Consommation","volume":"386 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131418364","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-04DOI: 10.1109/FTFC.2014.6828597
G. de Streel, J. De Vos, D. Flandre, D. Bol
A linear regulator for point of load power delivery with 280nA quiescent current and 0.008mm2 area is presented in this paper. Strong specifications on Power Supply Rejection Ratio (PSRR) and power consumption were included in the design at 0.5V output voltage to supply both low power analog and Ultra-Low-Voltage (ULV) digital circuits with a maximum load current of 0.5mA. Current mode pole splitting and NMOS source follower power stage allows us to optimize PSRR and guarantee stability whilst keeping low silicon footprint for the 6pf on-chip capacitor. We demonstrate its use for supplying a ULV CMOS imager that was manufactured in 65nm LP/GP CMOS process.
{"title":"A 65nm 1V to 0.5V linear regulator with ultra low quiescent current for mixed-signal ULV SoCs","authors":"G. de Streel, J. De Vos, D. Flandre, D. Bol","doi":"10.1109/FTFC.2014.6828597","DOIUrl":"https://doi.org/10.1109/FTFC.2014.6828597","url":null,"abstract":"A linear regulator for point of load power delivery with 280nA quiescent current and 0.008mm2 area is presented in this paper. Strong specifications on Power Supply Rejection Ratio (PSRR) and power consumption were included in the design at 0.5V output voltage to supply both low power analog and Ultra-Low-Voltage (ULV) digital circuits with a maximum load current of 0.5mA. Current mode pole splitting and NMOS source follower power stage allows us to optimize PSRR and guarantee stability whilst keeping low silicon footprint for the 6pf on-chip capacitor. We demonstrate its use for supplying a ULV CMOS imager that was manufactured in 65nm LP/GP CMOS process.","PeriodicalId":138166,"journal":{"name":"2014 IEEE Faible Tension Faible Consommation","volume":"304 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133566110","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-04DOI: 10.1109/FTFC.2014.6828614
Thomas Haine, François Stas, D. Bol
Ultra-low-power (ULP) diodes are special 2-T structures featuring a unique negative-differential resistance characteristic that can be used to build a 4-T ULP latch for flip-flop or SRAM applications. In this paper, we explore the area/mismatch tradeoff in such a ULP latch for ultra-low-voltage (ULV) SoCs in 28 nm FDSOI CMOS. We analyze the impact of transistor sizing, supply voltage and back-gate biasing to reach 6¿ robustness of the latch against mismatch while maintaining a leakage power below 10 pW. Under these constraints, the use of a genetic algorithm allows us to obtain the Pareto curve of optimal solutions between area and speed for both flip-flop and SRAM applications.
{"title":"Optimization of the area/robustness/speed trade-off in a 28 nm FDSOI latch based on ULP diodes","authors":"Thomas Haine, François Stas, D. Bol","doi":"10.1109/FTFC.2014.6828614","DOIUrl":"https://doi.org/10.1109/FTFC.2014.6828614","url":null,"abstract":"Ultra-low-power (ULP) diodes are special 2-T structures featuring a unique negative-differential resistance characteristic that can be used to build a 4-T ULP latch for flip-flop or SRAM applications. In this paper, we explore the area/mismatch tradeoff in such a ULP latch for ultra-low-voltage (ULV) SoCs in 28 nm FDSOI CMOS. We analyze the impact of transistor sizing, supply voltage and back-gate biasing to reach 6¿ robustness of the latch against mismatch while maintaining a leakage power below 10 pW. Under these constraints, the use of a genetic algorithm allows us to obtain the Pareto curve of optimal solutions between area and speed for both flip-flop and SRAM applications.","PeriodicalId":138166,"journal":{"name":"2014 IEEE Faible Tension Faible Consommation","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122194685","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-04DOI: 10.1109/FTFC.2014.6828621
G. Terrasson, A. Llaria, R. Briand
Recent advances in miniaturized sensors, low-power electronics and wireless communications have enabled the development of Body Sensor Networks (BSNs). These networks composed of intelligent communicating nodes are mainly dedicated to healthcare monitoring in order to study different pathologies or to detect and correct health problems. The objective of this article is to demonstrate the need of a system level dimensioning in order to design performing biomedical BSNs. Using the simulation tool OSCCAR developed by authors, this paper analyses the impact on the system performance of technology and strategy choice in early stages of BSN design flow, highlighting at the same time the need of a tradeoff between specifications such as Quality of Service and node autonomy.
{"title":"System level dimensioning of low power biomedical Body Sensor Networks","authors":"G. Terrasson, A. Llaria, R. Briand","doi":"10.1109/FTFC.2014.6828621","DOIUrl":"https://doi.org/10.1109/FTFC.2014.6828621","url":null,"abstract":"Recent advances in miniaturized sensors, low-power electronics and wireless communications have enabled the development of Body Sensor Networks (BSNs). These networks composed of intelligent communicating nodes are mainly dedicated to healthcare monitoring in order to study different pathologies or to detect and correct health problems. The objective of this article is to demonstrate the need of a system level dimensioning in order to design performing biomedical BSNs. Using the simulation tool OSCCAR developed by authors, this paper analyses the impact on the system performance of technology and strategy choice in early stages of BSN design flow, highlighting at the same time the need of a tradeoff between specifications such as Quality of Service and node autonomy.","PeriodicalId":138166,"journal":{"name":"2014 IEEE Faible Tension Faible Consommation","volume":"237 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121118897","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-04DOI: 10.1109/FTFC.2014.6828606
M. Azadmehr, Belal K. Khajeh, Y. Berg
In this paper we have demonstrated a novel approach for actuation and read-out of resonating sensors. In this approach, instead of reading the amplitude of the resonating beam in resonance, we use the frequency of the beam as a measure of the sensors response. By using a bidirectional amplifier a pulse is sent to a resonating sensor in one direction and the frequency response of the sensor is measured using the opposite direction of the amplifier. This approach results in more compact and more power conservative systems. This approach mimics the way radars operate where a pulse is sent out and the reflection is measured. The circuit is very compact with low component spread and consumes an average power of 22μW and a maximum power of 100μW when actuating the sensor.
{"title":"A bidirectional circuit for actuation and read-out of resonating sensors","authors":"M. Azadmehr, Belal K. Khajeh, Y. Berg","doi":"10.1109/FTFC.2014.6828606","DOIUrl":"https://doi.org/10.1109/FTFC.2014.6828606","url":null,"abstract":"In this paper we have demonstrated a novel approach for actuation and read-out of resonating sensors. In this approach, instead of reading the amplitude of the resonating beam in resonance, we use the frequency of the beam as a measure of the sensors response. By using a bidirectional amplifier a pulse is sent to a resonating sensor in one direction and the frequency response of the sensor is measured using the opposite direction of the amplifier. This approach results in more compact and more power conservative systems. This approach mimics the way radars operate where a pulse is sent out and the reflection is measured. The circuit is very compact with low component spread and consumes an average power of 22μW and a maximum power of 100μW when actuating the sensor.","PeriodicalId":138166,"journal":{"name":"2014 IEEE Faible Tension Faible Consommation","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131128666","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-04DOI: 10.1109/FTFC.2014.6828615
J. De Vos, D. Flandre, D. Bol
The development of wireless sensor nodes (WSNs) as well as the rise of the Internet-of-Things (IoT) push ahead the research effort in ultra-low-power integrated circuits. Jointly with the recent development of micro-energy harvesters, it extends the battery lifetime of IoT nodes. Nevertheless, the power extracted by such energy harvesters does not provide a large power budget so that circuits in IoT nodes are highly duty cycled. In this paper we study switched-capacitor DC/DC converters as a solution for empowering such IoT nodes in a SoC integration. We specifically give insights about their sizing and show that a systematic sizing methodology is a strong tool enabling fast exploration of the design trade-offs. We also study how multi-mode converters can meet the power needs of IoT SoCs.
{"title":"Switched-capacitor DC/DC converters for empowering Internet-of-Things SoCs","authors":"J. De Vos, D. Flandre, D. Bol","doi":"10.1109/FTFC.2014.6828615","DOIUrl":"https://doi.org/10.1109/FTFC.2014.6828615","url":null,"abstract":"The development of wireless sensor nodes (WSNs) as well as the rise of the Internet-of-Things (IoT) push ahead the research effort in ultra-low-power integrated circuits. Jointly with the recent development of micro-energy harvesters, it extends the battery lifetime of IoT nodes. Nevertheless, the power extracted by such energy harvesters does not provide a large power budget so that circuits in IoT nodes are highly duty cycled. In this paper we study switched-capacitor DC/DC converters as a solution for empowering such IoT nodes in a SoC integration. We specifically give insights about their sizing and show that a systematic sizing methodology is a strong tool enabling fast exploration of the design trade-offs. We also study how multi-mode converters can meet the power needs of IoT SoCs.","PeriodicalId":138166,"journal":{"name":"2014 IEEE Faible Tension Faible Consommation","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127001212","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-04DOI: 10.1109/FTFC.2014.6828617
A. Teman
SRAM stability is one of the primary bottlenecks of current VLSI system design, and the unequivocal supply voltage scaling limiter. Static noise margin metrics have long been the de-facto standard for measuring this stability and estimating the yield of SRAM arrays. However, in modern process technologies, under scaled supply voltages and increased process variations, these traditional metrics are no longer sufficient. Recent research has analyzed the dynamic behavior and stability of SRAM circuits, leading to dynamic stability metrics and dynamic noise margin definition. This paper provides a brief overview of the limitations of static noise margin metrics and the resulting dynamic stability and noise margin concepts that have been proposed to overcome them.
{"title":"Dynamic stability and noise margins of SRAM arrays in nanoscaled technologies","authors":"A. Teman","doi":"10.1109/FTFC.2014.6828617","DOIUrl":"https://doi.org/10.1109/FTFC.2014.6828617","url":null,"abstract":"SRAM stability is one of the primary bottlenecks of current VLSI system design, and the unequivocal supply voltage scaling limiter. Static noise margin metrics have long been the de-facto standard for measuring this stability and estimating the yield of SRAM arrays. However, in modern process technologies, under scaled supply voltages and increased process variations, these traditional metrics are no longer sufficient. Recent research has analyzed the dynamic behavior and stability of SRAM circuits, leading to dynamic stability metrics and dynamic noise margin definition. This paper provides a brief overview of the limitations of static noise margin metrics and the resulting dynamic stability and noise margin concepts that have been proposed to overcome them.","PeriodicalId":138166,"journal":{"name":"2014 IEEE Faible Tension Faible Consommation","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127119678","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-04DOI: 10.1109/FTFC.2014.6828607
T. K. Hong Nguyen, C. Belleudy, T. V. Pham
Power consumption in programmable devices has become a primary factor in design flow. Among the main concerns of power consumption, application performance, battery life, thermal challenges, or reliability, power consumption is crucial in FPGA designs for powered battery equipment. In this paper, we study the FPGA-based design for Sobel Edge Detection algorithm for low cost fall detector and we present an accurate evaluation of dynamic power estimation and real-time measurement. Our work uses Root Mean Square Error index to evaluate the accuracy rate between estimated and measured power consumption... This application is implemented on low-power Zynq-7000 AP SoC family.
可编程器件的功耗已成为设计流程中的主要因素。在功耗、应用性能、电池寿命、热挑战或可靠性等主要问题中，功耗在动力电池设备的FPGA设计中至关重要。本文研究了基于fpga的低成本跌落检测器的Sobel边缘检测算法设计，并给出了准确的动态功率估计和实时测量评估。我们的工作使用均方根误差指数来评估估计和测量功耗之间的准确率。本应用在低功耗Zynq-7000 AP SoC系列上实现。
{"title":"Power evaluation of Sobel filter on Xilinx platform","authors":"T. K. Hong Nguyen, C. Belleudy, T. V. Pham","doi":"10.1109/FTFC.2014.6828607","DOIUrl":"https://doi.org/10.1109/FTFC.2014.6828607","url":null,"abstract":"Power consumption in programmable devices has become a primary factor in design flow. Among the main concerns of power consumption, application performance, battery life, thermal challenges, or reliability, power consumption is crucial in FPGA designs for powered battery equipment. In this paper, we study the FPGA-based design for Sobel Edge Detection algorithm for low cost fall detector and we present an accurate evaluation of dynamic power estimation and real-time measurement. Our work uses Root Mean Square Error index to evaluate the accuracy rate between estimated and measured power consumption... This application is implemented on low-power Zynq-7000 AP SoC family.","PeriodicalId":138166,"journal":{"name":"2014 IEEE Faible Tension Faible Consommation","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129093154","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-04DOI: 10.1109/FTFC.2014.6828603
Yu Yung-Hui, Po-Hao Wang, Tien-Fu Chen, Tay-Jyi Lin, Jinn-Shyan Wang
Scaling down the supply voltage for embedded SoC becomes a necessary technique to lower power requirements in mobile devices. However, caches become susceptible or even fail in low voltages, and distribution of access latencies is significantly increased in new technology nodes. Past researches suggested several solutions to deal with the memory reliability at low voltages, where a timing table records cache lines with latency faults. This paper proposes cache management strategies for variable-latency caches at low voltages. We analyze the locality effect and propose two methods to dynamically adapt latency faults at run time and give the advantages of those methods compared to traditional LRU for low-voltage caches.
{"title":"Adaptive variable-latency cache management for low-voltage caches","authors":"Yu Yung-Hui, Po-Hao Wang, Tien-Fu Chen, Tay-Jyi Lin, Jinn-Shyan Wang","doi":"10.1109/FTFC.2014.6828603","DOIUrl":"https://doi.org/10.1109/FTFC.2014.6828603","url":null,"abstract":"Scaling down the supply voltage for embedded SoC becomes a necessary technique to lower power requirements in mobile devices. However, caches become susceptible or even fail in low voltages, and distribution of access latencies is significantly increased in new technology nodes. Past researches suggested several solutions to deal with the memory reliability at low voltages, where a timing table records cache lines with latency faults. This paper proposes cache management strategies for variable-latency caches at low voltages. We analyze the locality effect and propose two methods to dynamically adapt latency faults at run time and give the advantages of those methods compared to traditional LRU for low-voltage caches.","PeriodicalId":138166,"journal":{"name":"2014 IEEE Faible Tension Faible Consommation","volume":"111 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132543240","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-04DOI: 10.1109/FTFC.2014.6828595
Florian Barrau, Bruno Paille, E. Kussener, D. Goguenheim
This paper presents a new approach to resolve an ambiguity zone of carrier phase measurements of low power devices. It is based on a Time Difference Of Arrival method. It reliably resolves the ambiguities between two reference points and a transceiver. Simulation are based on a low-power state-of-the-art ZigBee radio architecture. The results show that with a ZigBee channel and 12 MHz sampling frequency it is possible to reliably measure distances from 25cm to 25m without phase ambiguities and with a standard deviation lower than 20cm.
{"title":"New technique to resolve carrier-phase cycle ambiguity for narrowband low-power systems","authors":"Florian Barrau, Bruno Paille, E. Kussener, D. Goguenheim","doi":"10.1109/FTFC.2014.6828595","DOIUrl":"https://doi.org/10.1109/FTFC.2014.6828595","url":null,"abstract":"This paper presents a new approach to resolve an ambiguity zone of carrier phase measurements of low power devices. It is based on a Time Difference Of Arrival method. It reliably resolves the ambiguities between two reference points and a transceiver. Simulation are based on a low-power state-of-the-art ZigBee radio architecture. The results show that with a ZigBee channel and 12 MHz sampling frequency it is possible to reliably measure distances from 25cm to 25m without phase ambiguities and with a standard deviation lower than 20cm.","PeriodicalId":138166,"journal":{"name":"2014 IEEE Faible Tension Faible Consommation","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131070201","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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