Pub Date : 2014-05-04DOI: 10.1109/FTFC.2014.6828613
S. Sen, K. Shaik, J. Mukherjee, P. Dhalvaniya
A distortion improvement technique for bootstrapped-gate Sample-and-Hold (S/H) circuits, is proposed. The gate overdrive voltage and conductance of the MOS sampling switch are made constant by cancelling the body-effect induced variations in the threshold-voltage. An amplifier is used to provide appropriate gain in the bootstrapped-gate path. The technique allows the minimized second-harmonic distortion (HD2) by adjusting the gain to Ag =1+kγ1, where kγ1 is the sensitivity of threshold voltage to the source voltage. Furthermore, the S/H distortion remains insensitive to the amplifier op-amp characteristics. Chip prototype measurement results of a single-ended S/H amplifier using 0.18 μm CMOS technology show HD2 improvement of 11 dB over conventional bootstrapped-gate S/H.
{"title":"A distortion reduction technique for bootstrapped-gate MOS Sample-and-Hold circuits using body-effect compensation","authors":"S. Sen, K. Shaik, J. Mukherjee, P. Dhalvaniya","doi":"10.1109/FTFC.2014.6828613","DOIUrl":"https://doi.org/10.1109/FTFC.2014.6828613","url":null,"abstract":"A distortion improvement technique for bootstrapped-gate Sample-and-Hold (S/H) circuits, is proposed. The gate overdrive voltage and conductance of the MOS sampling switch are made constant by cancelling the body-effect induced variations in the threshold-voltage. An amplifier is used to provide appropriate gain in the bootstrapped-gate path. The technique allows the minimized second-harmonic distortion (HD2) by adjusting the gain to Ag =1+kγ1, where kγ1 is the sensitivity of threshold voltage to the source voltage. Furthermore, the S/H distortion remains insensitive to the amplifier op-amp characteristics. Chip prototype measurement results of a single-ended S/H amplifier using 0.18 μm CMOS technology show HD2 improvement of 11 dB over conventional bootstrapped-gate S/H.","PeriodicalId":138166,"journal":{"name":"2014 IEEE Faible Tension Faible Consommation","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116428260","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-04DOI: 10.1109/FTFC.2014.6828598
A. Mordakhay, A. Fish
An analog readout circuit for use in conjunction with the Planar-Hall-Effect Magnetic-Random-Access-Memory is presented. The non-volatile nature of this type of memory allows zero leakage during memory retention, allowing significant power saving. The circuit employs a novel technique for readout operation of memory bit-cells. The circuit uses chopping and switched-capacitor techniques for amplification of the low input signal as well as elimination of DC-offset and low-frequency noise. The binary nature of the data allows an area efficient implementation at the cost of linearity, which is less significant for memory readout applications. The proposed circuit was implemented in the TowerJazz 180nm CMOS process at a supply voltage of 1.8V, and can reliably sense input signals with amplitude of as low as 1mV.
{"title":"Analog readout circuit for zero leakage Planar-Hall-Effect-Magnetic-Random-Access-Memory","authors":"A. Mordakhay, A. Fish","doi":"10.1109/FTFC.2014.6828598","DOIUrl":"https://doi.org/10.1109/FTFC.2014.6828598","url":null,"abstract":"An analog readout circuit for use in conjunction with the Planar-Hall-Effect Magnetic-Random-Access-Memory is presented. The non-volatile nature of this type of memory allows zero leakage during memory retention, allowing significant power saving. The circuit employs a novel technique for readout operation of memory bit-cells. The circuit uses chopping and switched-capacitor techniques for amplification of the low input signal as well as elimination of DC-offset and low-frequency noise. The binary nature of the data allows an area efficient implementation at the cost of linearity, which is less significant for memory readout applications. The proposed circuit was implemented in the TowerJazz 180nm CMOS process at a supply voltage of 1.8V, and can reliably sense input signals with amplitude of as low as 1mV.","PeriodicalId":138166,"journal":{"name":"2014 IEEE Faible Tension Faible Consommation","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121806609","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-04DOI: 10.1109/FTFC.2014.6828602
K. Sarfraz, M. Chan
A low-noise local bitline technique is presented for dual-Vt register files. The proposed read port topology produces an equal magnitude of local bitline (LBL) leakage currents during standby and read `0¿ modes of operation. This feature allows a standard keeper to operate more effectively at reduced supply voltages due to suppressed LBL noise and permits robust memory operation down to data retention voltage (DRV). The LBL noise at DRV is reduced to 34.7% of the permitted noise level. Furthermore, LBL leakage currents are suppressed by 39.4% and 93.5% in standby and read `0¿ modes of operation with the proposed technique as compared to the conventional LBL technique under an equal LBL delay and robustness constraint. These benefits are achieved at the expense of 35.3% increase in bitcell area, 5.3% increase in energy consumption in a read operation and 14.5% degradation in the overall read delay.
{"title":"A low-noise local bitline technique for dual-Vt register files","authors":"K. Sarfraz, M. Chan","doi":"10.1109/FTFC.2014.6828602","DOIUrl":"https://doi.org/10.1109/FTFC.2014.6828602","url":null,"abstract":"A low-noise local bitline technique is presented for dual-Vt register files. The proposed read port topology produces an equal magnitude of local bitline (LBL) leakage currents during standby and read `0¿ modes of operation. This feature allows a standard keeper to operate more effectively at reduced supply voltages due to suppressed LBL noise and permits robust memory operation down to data retention voltage (DRV). The LBL noise at DRV is reduced to 34.7% of the permitted noise level. Furthermore, LBL leakage currents are suppressed by 39.4% and 93.5% in standby and read `0¿ modes of operation with the proposed technique as compared to the conventional LBL technique under an equal LBL delay and robustness constraint. These benefits are achieved at the expense of 35.3% increase in bitcell area, 5.3% increase in energy consumption in a read operation and 14.5% degradation in the overall read delay.","PeriodicalId":138166,"journal":{"name":"2014 IEEE Faible Tension Faible Consommation","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123461751","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-04DOI: 10.1109/FTFC.2014.6828599
A. Essawy, A. Ismail
In this work an inverted-based low-voltage implementation for continuous-time sigma delta analog-to-digital converters is proposed. The proposed implementation is applied to a third-order single loop modulator. The loop filter is implemented using active RC integrators. A 50 dB SNDR is achieved for a signal bandwidth of 2 MHz and sampling frequency of 100 MHz, while consuming 1 mA from 0.75 V, supply in 65 nm CMOS technology.
在这项工作中，提出了一种基于逆变的低压实现连续时间σ δ模数转换器。提出的实现应用于三阶单环路调制器。环路滤波器采用有源RC积分器实现。在65纳米CMOS技术中，信号带宽为2 MHz，采样频率为100 MHz，同时从0.75 V电源消耗1 mA，实现了50 dB SNDR。
{"title":"A low voltage inverter-based continuous-time sigma delta analog-to-digital converter in 65nm CMOS technology","authors":"A. Essawy, A. Ismail","doi":"10.1109/FTFC.2014.6828599","DOIUrl":"https://doi.org/10.1109/FTFC.2014.6828599","url":null,"abstract":"In this work an inverted-based low-voltage implementation for continuous-time sigma delta analog-to-digital converters is proposed. The proposed implementation is applied to a third-order single loop modulator. The loop filter is implemented using active RC integrators. A 50 dB SNDR is achieved for a signal bandwidth of 2 MHz and sampling frequency of 100 MHz, while consuming 1 mA from 0.75 V, supply in 65 nm CMOS technology.","PeriodicalId":138166,"journal":{"name":"2014 IEEE Faible Tension Faible Consommation","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125657671","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-04DOI: 10.1109/FTFC.2014.6828593
Roman Buzilo, B. Likhterov, R. Giterman, I. Levi, A. Fish, A. Belenky
This paper presents a new system approach to an on-chip voltage source based on integrated thermoelectric generator (TEG) elements. The proposed architecture employs a novel active TEG array (ATA) system. The ATA system is able to control the TEG's harvested electrical energy, without using a DC/DC integrated converter. This makes it possible to cut power losses due to the non-ideality of the converter efficiency and to reduce the chip area. Commonly, the reduced efficiency of DC/DC converters was compensated for by adding TEG elements, thus enlarging the chip area. The proposed novel approach to designing an energy harvesting integrated voltage source was implemented to support ultra-low power systems for biomedical applications such as wearable wireless body sensors. The voltage source was simulated in a 0.18 μm standard CMOS process, supplying 1.8V±0.18V. The simulation results are presented.
{"title":"Approach to integrated energy harvesting voltage source based on novel active TEG array system","authors":"Roman Buzilo, B. Likhterov, R. Giterman, I. Levi, A. Fish, A. Belenky","doi":"10.1109/FTFC.2014.6828593","DOIUrl":"https://doi.org/10.1109/FTFC.2014.6828593","url":null,"abstract":"This paper presents a new system approach to an on-chip voltage source based on integrated thermoelectric generator (TEG) elements. The proposed architecture employs a novel active TEG array (ATA) system. The ATA system is able to control the TEG's harvested electrical energy, without using a DC/DC integrated converter. This makes it possible to cut power losses due to the non-ideality of the converter efficiency and to reduce the chip area. Commonly, the reduced efficiency of DC/DC converters was compensated for by adding TEG elements, thus enlarging the chip area. The proposed novel approach to designing an energy harvesting integrated voltage source was implemented to support ultra-low power systems for biomedical applications such as wearable wireless body sensors. The voltage source was simulated in a 0.18 μm standard CMOS process, supplying 1.8V±0.18V. The simulation results are presented.","PeriodicalId":138166,"journal":{"name":"2014 IEEE Faible Tension Faible Consommation","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115548680","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-04DOI: 10.1109/FTFC.2014.6828610
J. A. A. Angulo, E. Kussener, H. Barthélemy, Benjamin Duval
This paper presents a low power True Random Number Generator (TRNG), based on the discrete time-chaos, intended for a RFID security applications, to be developped on CMOS 350nm standard technology. The circuit relies on a discrete time chaotic oscillator to generate patterns to be sampled to get a raw random signal to be debiased by a digital corrector.
{"title":"Discrete chaos - based Random Number Generator","authors":"J. A. A. Angulo, E. Kussener, H. Barthélemy, Benjamin Duval","doi":"10.1109/FTFC.2014.6828610","DOIUrl":"https://doi.org/10.1109/FTFC.2014.6828610","url":null,"abstract":"This paper presents a low power True Random Number Generator (TRNG), based on the discrete time-chaos, intended for a RFID security applications, to be developped on CMOS 350nm standard technology. The circuit relies on a discrete time chaotic oscillator to generate patterns to be sampled to get a raw random signal to be debiased by a digital corrector.","PeriodicalId":138166,"journal":{"name":"2014 IEEE Faible Tension Faible Consommation","volume":"138 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128767307","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-04DOI: 10.1109/FTFC.2014.6828616
N. Reynders, B. Rooseleer, W. Dehaene
This paper discusses energy-efficient design, both for logic and for memories. For datapaths which are controlled by dynamic energy, high energy-efficiency can be obtained by significantly reducing the supply voltage. However, simply lowering VDD does not automatically imply more energy-efficient operation for SRAM memories, as they are dominated by static leakage. This paper identifies which design methodologies can be employed to achieve high energy-efficiency. In particular, a JPEG encoder fabricated in a 40nm CMOS technology is used as a case study to determine the trade-offs, challenges and benefits of energy-efficient design.
{"title":"Energy-efficient logic and SRAM design: A case study","authors":"N. Reynders, B. Rooseleer, W. Dehaene","doi":"10.1109/FTFC.2014.6828616","DOIUrl":"https://doi.org/10.1109/FTFC.2014.6828616","url":null,"abstract":"This paper discusses energy-efficient design, both for logic and for memories. For datapaths which are controlled by dynamic energy, high energy-efficiency can be obtained by significantly reducing the supply voltage. However, simply lowering VDD does not automatically imply more energy-efficient operation for SRAM memories, as they are dominated by static leakage. This paper identifies which design methodologies can be employed to achieve high energy-efficiency. In particular, a JPEG encoder fabricated in a 40nm CMOS technology is used as a case study to determine the trade-offs, challenges and benefits of energy-efficient design.","PeriodicalId":138166,"journal":{"name":"2014 IEEE Faible Tension Faible Consommation","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128784233","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-04DOI: 10.1109/FTFC.2014.6828622
S. Z. Ahmed, Yuhui Bai, Imen Dhif, Laurent Lambert, Imen Mhedhbi, P. Garda, B. Granado, K. Hachicha, A. Pinna, Fakhreddine Ghaffari, A. Histace, O. Romain
In this paper we present an hardware realisation for an image coder used in the SmartEEG project. This collaborative project has the aim of the conception of a multimodal tool for EEG signal to allow transmission of a complete examination of a patient. We show that we can expect good performance on a FPGA board for the time consuming part of this tool that is the image coder.
{"title":"SmartEEG: A multimodal tool for EEG signals","authors":"S. Z. Ahmed, Yuhui Bai, Imen Dhif, Laurent Lambert, Imen Mhedhbi, P. Garda, B. Granado, K. Hachicha, A. Pinna, Fakhreddine Ghaffari, A. Histace, O. Romain","doi":"10.1109/FTFC.2014.6828622","DOIUrl":"https://doi.org/10.1109/FTFC.2014.6828622","url":null,"abstract":"In this paper we present an hardware realisation for an image coder used in the SmartEEG project. This collaborative project has the aim of the conception of a multimodal tool for EEG signal to allow transmission of a complete examination of a patient. We show that we can expect good performance on a FPGA board for the time consuming part of this tool that is the image coder.","PeriodicalId":138166,"journal":{"name":"2014 IEEE Faible Tension Faible Consommation","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123715118","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-04DOI: 10.1109/FTFC.2014.6828604
A. Mabrouki, M. Latrach, Vincent Lorrain
In this paper we present the design of high efficiency low power rectifier for microwave energy harvesting. The proposed circuit is based on a voltage booster formed by a voltage doubler type Latour structure. The circuit topology including parasitic elements and microstrip lines has been studied and optimized for high efficiency energy conversion dedicated to low input power operations (below -10 dBm). Measurement results show 21% and 38% RF-DC conversion efficiencies for, respectively, -20 dBm and -10 dBm input power for 10 KΩ resistor load at 850 MHz. Experimental performances of the rectifier are in good agreement with the simulated ones.
{"title":"High efficiency low power rectifier design using zero bias schottky diodes","authors":"A. Mabrouki, M. Latrach, Vincent Lorrain","doi":"10.1109/FTFC.2014.6828604","DOIUrl":"https://doi.org/10.1109/FTFC.2014.6828604","url":null,"abstract":"In this paper we present the design of high efficiency low power rectifier for microwave energy harvesting. The proposed circuit is based on a voltage booster formed by a voltage doubler type Latour structure. The circuit topology including parasitic elements and microstrip lines has been studied and optimized for high efficiency energy conversion dedicated to low input power operations (below -10 dBm). Measurement results show 21% and 38% RF-DC conversion efficiencies for, respectively, -20 dBm and -10 dBm input power for 10 KΩ resistor load at 850 MHz. Experimental performances of the rectifier are in good agreement with the simulated ones.","PeriodicalId":138166,"journal":{"name":"2014 IEEE Faible Tension Faible Consommation","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125502737","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-01DOI: 10.1109/FTFC.2014.6828609
A. Baz, D. Shang, Fei Xia, Xuan Gu, A. Yakovlev
The contradictions among high performance, low power and unpredictable energy supply motivate a large part of current mobile and embedded system design research especially on systems that can work under a wide range of voltages. Concurrency has been used to improve performance and/or efficiency, but has not been properly studied with widely variable supply voltages. In this paper, a self-timed micropipeline is designed to investigate system behaviour under a wide range of voltages, focusing on asynchrony and the relationship between the degree of concurrency and all important performance metrics including the amount of computation. Results suggest that above threshold, the amount of computation per given amount of energy is practically insensitive to the degree of concurrency, but below threshold the dependency on the degree of concurrency goes up significantly. This indicates that probably the best architectures for energy efficiency are asynchronous data-flow ones and those operating in sub-threshold.
{"title":"Energy efficiency of micropipelines under wide dynamic supply voltages","authors":"A. Baz, D. Shang, Fei Xia, Xuan Gu, A. Yakovlev","doi":"10.1109/FTFC.2014.6828609","DOIUrl":"https://doi.org/10.1109/FTFC.2014.6828609","url":null,"abstract":"The contradictions among high performance, low power and unpredictable energy supply motivate a large part of current mobile and embedded system design research especially on systems that can work under a wide range of voltages. Concurrency has been used to improve performance and/or efficiency, but has not been properly studied with widely variable supply voltages. In this paper, a self-timed micropipeline is designed to investigate system behaviour under a wide range of voltages, focusing on asynchrony and the relationship between the degree of concurrency and all important performance metrics including the amount of computation. Results suggest that above threshold, the amount of computation per given amount of energy is practically insensitive to the degree of concurrency, but below threshold the dependency on the degree of concurrency goes up significantly. This indicates that probably the best architectures for energy efficiency are asynchronous data-flow ones and those operating in sub-threshold.","PeriodicalId":138166,"journal":{"name":"2014 IEEE Faible Tension Faible Consommation","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130414019","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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