Pub Date : 2017-09-01DOI: 10.1109/ISPCC.2017.8269733
Gaurav, R. Anand, Vinod Kumar
Psychological stress is a vital parameter related to individual's health and cognitive performance which may affect emotions and professional efficiency. Regula stress profile generated can be used as neurofeedback for the clinical as personal assessment. This paper describes a method to detect mental stress level based on physiological parameters. In this method an electroencephalogram (EEG) parameter based binary stress classifier is developed which is validated through probabilistic stress profiler of differential stress inventory questionnaire. A non-invasive 9 channel EEG is used to extract physiological signal and an EEG-metric based cognitive state and workload outputs is generated for 41 healthy volunteers (37 males and 4 females, age; 24±5 years). All subjects were performed three simple tasks of closed eye, focusing vision on a red dot on center of dark screen and focusing on a white screen. Central tendencies (mean, median and mode) are extracted from of EEG-metric (sleep onset, distraction, low engagement, high engagement and cognitive states) as features. Either of the two classes as low stress or high stress are evaluated from probabilistic stress profiler of differential stress inventory and used as training output classes. A supervisory training of multiple layer perceptron based binary support vector machine classifier was used to detect stress class one by one. 40 subject's samples were used for training and interchanging one-by one 41th subject's stress class is determined from the designed classifier. Out of 41 subjects, stress level of 30 subjects is correctly identified.
{"title":"Non-invasive EEG-metric based stress detection","authors":"Gaurav, R. Anand, Vinod Kumar","doi":"10.1109/ISPCC.2017.8269733","DOIUrl":"https://doi.org/10.1109/ISPCC.2017.8269733","url":null,"abstract":"Psychological stress is a vital parameter related to individual's health and cognitive performance which may affect emotions and professional efficiency. Regula stress profile generated can be used as neurofeedback for the clinical as personal assessment. This paper describes a method to detect mental stress level based on physiological parameters. In this method an electroencephalogram (EEG) parameter based binary stress classifier is developed which is validated through probabilistic stress profiler of differential stress inventory questionnaire. A non-invasive 9 channel EEG is used to extract physiological signal and an EEG-metric based cognitive state and workload outputs is generated for 41 healthy volunteers (37 males and 4 females, age; 24±5 years). All subjects were performed three simple tasks of closed eye, focusing vision on a red dot on center of dark screen and focusing on a white screen. Central tendencies (mean, median and mode) are extracted from of EEG-metric (sleep onset, distraction, low engagement, high engagement and cognitive states) as features. Either of the two classes as low stress or high stress are evaluated from probabilistic stress profiler of differential stress inventory and used as training output classes. A supervisory training of multiple layer perceptron based binary support vector machine classifier was used to detect stress class one by one. 40 subject's samples were used for training and interchanging one-by one 41th subject's stress class is determined from the designed classifier. Out of 41 subjects, stress level of 30 subjects is correctly identified.","PeriodicalId":142166,"journal":{"name":"2017 4th International Conference on Signal Processing, Computing and Control (ISPCC)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126011866","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-09-01DOI: 10.1109/ISPCC.2017.8269685
K. Ramkumar, Amanpreet Kaur
The Mobile Adhoc NETworks (MANETs) are vulnerable to routing attacks [4] and hackers scythe the wireless networks easily. The MANETs need a distinctive attention of confidentiality [5] and authentication since these networks have unstable topologies and uncertainty in routing. Generally, the hackers try to snoop the wireless medium and get information about the wireless networks, the nodes which are in a particular propagation range can do this easily. So, it is a best practice to encrypt all routing and payloads in MANETs to avoid all men in the middle attacks. The symmetric encryptions are the standards for encrypting long messages with the limited computational efforts but they need a common key to start the encryption and decryption process. There are two basic questions, How to exchange the key between the source and destination, moreover who will take care of issuing and revoking keys to the new entrants. The key management is an important aspect of security algorithms and the proposed work implements a standard key management system by using the curve fitting-least square method of polynomial interpolation.
{"title":"A distributed method of key issue and revocation of mobile ad hoc networks using curve fitting","authors":"K. Ramkumar, Amanpreet Kaur","doi":"10.1109/ISPCC.2017.8269685","DOIUrl":"https://doi.org/10.1109/ISPCC.2017.8269685","url":null,"abstract":"The Mobile Adhoc NETworks (MANETs) are vulnerable to routing attacks [4] and hackers scythe the wireless networks easily. The MANETs need a distinctive attention of confidentiality [5] and authentication since these networks have unstable topologies and uncertainty in routing. Generally, the hackers try to snoop the wireless medium and get information about the wireless networks, the nodes which are in a particular propagation range can do this easily. So, it is a best practice to encrypt all routing and payloads in MANETs to avoid all men in the middle attacks. The symmetric encryptions are the standards for encrypting long messages with the limited computational efforts but they need a common key to start the encryption and decryption process. There are two basic questions, How to exchange the key between the source and destination, moreover who will take care of issuing and revoking keys to the new entrants. The key management is an important aspect of security algorithms and the proposed work implements a standard key management system by using the curve fitting-least square method of polynomial interpolation.","PeriodicalId":142166,"journal":{"name":"2017 4th International Conference on Signal Processing, Computing and Control (ISPCC)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114222400","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-09-01DOI: 10.1109/ISPCC.2017.8269718
M. Gupta, Akshay Walia, S. Gupta, A. Sikander
In a large scale interconnected power system, the frequency and tie line power fluctuates when the sudden changes in load occurs. Therefore, in order to regulate this fluctuation in a desired manner a suitable control scheme namely load frequency control is required. But the model of this interconnected single area power system is very complex therefore it is difficult to develop a required control strategy. Thus, in this paper, modelling and identification of single area power system has been presented via model order reduction. In order to maintain the stability in reduced system a stability preservation method namely stability equation methods has been employed. The obtained results are compared when higher and reduced systems are subjected to unit step and impulse inputs. Furthermore, the performance of the proposed reduced model has also been evaluated in frequency domain.
{"title":"Modelling and identification of single area power system for load frequency control","authors":"M. Gupta, Akshay Walia, S. Gupta, A. Sikander","doi":"10.1109/ISPCC.2017.8269718","DOIUrl":"https://doi.org/10.1109/ISPCC.2017.8269718","url":null,"abstract":"In a large scale interconnected power system, the frequency and tie line power fluctuates when the sudden changes in load occurs. Therefore, in order to regulate this fluctuation in a desired manner a suitable control scheme namely load frequency control is required. But the model of this interconnected single area power system is very complex therefore it is difficult to develop a required control strategy. Thus, in this paper, modelling and identification of single area power system has been presented via model order reduction. In order to maintain the stability in reduced system a stability preservation method namely stability equation methods has been employed. The obtained results are compared when higher and reduced systems are subjected to unit step and impulse inputs. Furthermore, the performance of the proposed reduced model has also been evaluated in frequency domain.","PeriodicalId":142166,"journal":{"name":"2017 4th International Conference on Signal Processing, Computing and Control (ISPCC)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124719109","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-09-01DOI: 10.1109/ISPCC.2017.8269672
Diksha Hooda, Rinkle Rani
Software Delivery accounts a considerable premium to an organization. It provides a definition to the fundamental expertise and the core competitiveness. An efficient approach towards software delivery paves the way to overpower competitive risks. The major challenges faced during the process of software delivery include bandwidth limitation, poor performance, delivery time, and economics of distribution and handling uncertainties at various levels of delivery. The problem is aggravated with increase in the size of the package delivery that is to be delivered. This paper provides a novel approach for efficient software delivery to the requesters which cuts in the chances of poor performance due to bandwidth issues. The approach provides an algorithm that simplifies the delivery for software products that are heavier in terms of size. It is a local tooling process which has an upper hand over the traditional centralized portal where all the software delivery requests are directed. The localized tooling methodology ensures safety of the product by encryption techniques. As a result of the request made by the end user, the tool packages the encrypted form of the product with an installing agent and prepares it to be transferred over the network. At the receiver's end, the package is downloaded and extracted with the help of the environment setup of the launching agent installed at the user's end.
{"title":"A novel localized approach for efficient delivery of software products","authors":"Diksha Hooda, Rinkle Rani","doi":"10.1109/ISPCC.2017.8269672","DOIUrl":"https://doi.org/10.1109/ISPCC.2017.8269672","url":null,"abstract":"Software Delivery accounts a considerable premium to an organization. It provides a definition to the fundamental expertise and the core competitiveness. An efficient approach towards software delivery paves the way to overpower competitive risks. The major challenges faced during the process of software delivery include bandwidth limitation, poor performance, delivery time, and economics of distribution and handling uncertainties at various levels of delivery. The problem is aggravated with increase in the size of the package delivery that is to be delivered. This paper provides a novel approach for efficient software delivery to the requesters which cuts in the chances of poor performance due to bandwidth issues. The approach provides an algorithm that simplifies the delivery for software products that are heavier in terms of size. It is a local tooling process which has an upper hand over the traditional centralized portal where all the software delivery requests are directed. The localized tooling methodology ensures safety of the product by encryption techniques. As a result of the request made by the end user, the tool packages the encrypted form of the product with an installing agent and prepares it to be transferred over the network. At the receiver's end, the package is downloaded and extracted with the help of the environment setup of the launching agent installed at the user's end.","PeriodicalId":142166,"journal":{"name":"2017 4th International Conference on Signal Processing, Computing and Control (ISPCC)","volume":"384 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124769159","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-09-01DOI: 10.1109/ISPCC.2017.8269722
Jaspinder Kaur, B. Sidhu
Cloud Computing is in demand now a days as it provides reliable, scalable and economical IT operations. As the scale of the cloud computing is increasing the need of an efficient scheduling algorithm for an effecting management of resources is also becoming crucial. Scheduling problem in cloud is NP-hard problem. Meta-heuristic approaches have been very useful in providing near optimal solution to the scheduling problem. In this paper a new approach for Task Scheduling using Flower Pollination Algorithm (TSFPA) has been introduced to allocate resources to task. The objective of this proposed algorithm is to minimize the makespan. The performance of the proposed algorithm has been compared with genetic algorithm (GA), first come first serve (FCFS) and round robin (RR) approach of scheduling using Cloudsim toolkit. Simulation results showed that performance of TSFPA is better than GA, RR and FCFS in terms of makespan.
{"title":"A new flower pollination based task scheduling algorithm in cloud environment","authors":"Jaspinder Kaur, B. Sidhu","doi":"10.1109/ISPCC.2017.8269722","DOIUrl":"https://doi.org/10.1109/ISPCC.2017.8269722","url":null,"abstract":"Cloud Computing is in demand now a days as it provides reliable, scalable and economical IT operations. As the scale of the cloud computing is increasing the need of an efficient scheduling algorithm for an effecting management of resources is also becoming crucial. Scheduling problem in cloud is NP-hard problem. Meta-heuristic approaches have been very useful in providing near optimal solution to the scheduling problem. In this paper a new approach for Task Scheduling using Flower Pollination Algorithm (TSFPA) has been introduced to allocate resources to task. The objective of this proposed algorithm is to minimize the makespan. The performance of the proposed algorithm has been compared with genetic algorithm (GA), first come first serve (FCFS) and round robin (RR) approach of scheduling using Cloudsim toolkit. Simulation results showed that performance of TSFPA is better than GA, RR and FCFS in terms of makespan.","PeriodicalId":142166,"journal":{"name":"2017 4th International Conference on Signal Processing, Computing and Control (ISPCC)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116805412","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-09-01DOI: 10.1109/ISPCC.2017.8269738
Jaskaranbeer Kaur, Ajay Kumar, M. Bansal
Smart cards are secure and multifunctional devices that have become the important part of our daily life applications i.e. from finance, transportation, telecommunication to education, entertainment, health care. Increased use of these devices leads to much advancement in the field of smart cards, yet there are some security threats related to smart cards that needed to be explored. In this paper, smart cards applications and its security threats are discussed. The smart cards authentication and data encryption schemes have been surveyed which lead to comparative survey of various works proposed in this area. This survey results in some research issues; and future directions to resolve these issues are defined.
{"title":"Lightweight cipher algorithms for smart cards security: A survey and open challenges","authors":"Jaskaranbeer Kaur, Ajay Kumar, M. Bansal","doi":"10.1109/ISPCC.2017.8269738","DOIUrl":"https://doi.org/10.1109/ISPCC.2017.8269738","url":null,"abstract":"Smart cards are secure and multifunctional devices that have become the important part of our daily life applications i.e. from finance, transportation, telecommunication to education, entertainment, health care. Increased use of these devices leads to much advancement in the field of smart cards, yet there are some security threats related to smart cards that needed to be explored. In this paper, smart cards applications and its security threats are discussed. The smart cards authentication and data encryption schemes have been surveyed which lead to comparative survey of various works proposed in this area. This survey results in some research issues; and future directions to resolve these issues are defined.","PeriodicalId":142166,"journal":{"name":"2017 4th International Conference on Signal Processing, Computing and Control (ISPCC)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130544390","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-09-01DOI: 10.1109/ISPCC.2017.8269746
P. Waraich, N. Batra
Secure routing over VANET is a major issue due to its high mobility environment. Due to dynamic topology, routes are frequently updated and also suffers from link breaks due to the obstacles i.e. buildings, tunnels and bridges etc. Frequent link breaks can cause packet drop and thus result in degradation of network performance. In case of VANETs, it becomes very difficult to identify the reason of the packet drop as it can also occur due to the presence of a security threat. VANET is a type of wireless adhoc network and suffer from common attacks which exist for mobile adhoc network (MANET) i.e. Denial of Services (DoS), Black hole, Gray hole and Sybil attack etc. Researchers have already developed various security mechanisms for secure routing over MANET but these solutions are not fully compatible with unique attributes of VANET i.e. vehicles can communicate with each other (V2V) as well as communication can be initiated with infrastructure based network (V2I). In order to secure the routing for both types of communication, there is need to develop a solution. In this paper, a method for secure routing is introduced which can identify as well as eliminate the existing security threat.
{"title":"Prevention of denial of service attack over vehicle ad hoc networks using quick response table","authors":"P. Waraich, N. Batra","doi":"10.1109/ISPCC.2017.8269746","DOIUrl":"https://doi.org/10.1109/ISPCC.2017.8269746","url":null,"abstract":"Secure routing over VANET is a major issue due to its high mobility environment. Due to dynamic topology, routes are frequently updated and also suffers from link breaks due to the obstacles i.e. buildings, tunnels and bridges etc. Frequent link breaks can cause packet drop and thus result in degradation of network performance. In case of VANETs, it becomes very difficult to identify the reason of the packet drop as it can also occur due to the presence of a security threat. VANET is a type of wireless adhoc network and suffer from common attacks which exist for mobile adhoc network (MANET) i.e. Denial of Services (DoS), Black hole, Gray hole and Sybil attack etc. Researchers have already developed various security mechanisms for secure routing over MANET but these solutions are not fully compatible with unique attributes of VANET i.e. vehicles can communicate with each other (V2V) as well as communication can be initiated with infrastructure based network (V2I). In order to secure the routing for both types of communication, there is need to develop a solution. In this paper, a method for secure routing is introduced which can identify as well as eliminate the existing security threat.","PeriodicalId":142166,"journal":{"name":"2017 4th International Conference on Signal Processing, Computing and Control (ISPCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115450119","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-09-01DOI: 10.1109/ISPCC.2017.8269737
Anand Sharma, Amardeep Singh
In the modern era, the internet of things are gaining lot of attention because its provides a connecting of all devices with the internet. The users can access the all devices wirelessly from anywhere. The internet is public available network, anyone access the network. So, to provide the user's security and privacy data security and authentication is required. To provide security cryptography algorithms used but the limitation is that the standard algorithms which are approved by NIST such as AES large block, key size, and memory consumable and their performance not up to mark in resource constraint devices. In this paper, a hybrid lightweight improved technique is proposed for data security and authentication for RFID tags. The performance analysis for the proposed technique is done and compare with the existing algorithm. The result shows that the hybrid technique resolve brute force, linear and differential cryptanalysis attacks.
{"title":"Hybrid improved technique for data security and authentication for RFID tags","authors":"Anand Sharma, Amardeep Singh","doi":"10.1109/ISPCC.2017.8269737","DOIUrl":"https://doi.org/10.1109/ISPCC.2017.8269737","url":null,"abstract":"In the modern era, the internet of things are gaining lot of attention because its provides a connecting of all devices with the internet. The users can access the all devices wirelessly from anywhere. The internet is public available network, anyone access the network. So, to provide the user's security and privacy data security and authentication is required. To provide security cryptography algorithms used but the limitation is that the standard algorithms which are approved by NIST such as AES large block, key size, and memory consumable and their performance not up to mark in resource constraint devices. In this paper, a hybrid lightweight improved technique is proposed for data security and authentication for RFID tags. The performance analysis for the proposed technique is done and compare with the existing algorithm. The result shows that the hybrid technique resolve brute force, linear and differential cryptanalysis attacks.","PeriodicalId":142166,"journal":{"name":"2017 4th International Conference on Signal Processing, Computing and Control (ISPCC)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116428758","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-09-01DOI: 10.1109/ISPCC.2017.8269706
S. Kaundal, Shelja Kaushal, A. Rana
This paper investigates the Junctionless (JL) FinFET with laterally graded channel and differentially graded channel design using TCAD simulation. It is demonstrated that differentially graded-JL FinFET (DG-JL FinFET) provides better subthreshold characteristics as compared to laterally graded-JL FinFET (LG-JL FinFET) and conventional uniformly doped-JL FinFET (UD-JL FinFET). However, the drive current is higher in LD-JL FinFET.
{"title":"Performance estimation of junctionless FinFET with graded channel design","authors":"S. Kaundal, Shelja Kaushal, A. Rana","doi":"10.1109/ISPCC.2017.8269706","DOIUrl":"https://doi.org/10.1109/ISPCC.2017.8269706","url":null,"abstract":"This paper investigates the Junctionless (JL) FinFET with laterally graded channel and differentially graded channel design using TCAD simulation. It is demonstrated that differentially graded-JL FinFET (DG-JL FinFET) provides better subthreshold characteristics as compared to laterally graded-JL FinFET (LG-JL FinFET) and conventional uniformly doped-JL FinFET (UD-JL FinFET). However, the drive current is higher in LD-JL FinFET.","PeriodicalId":142166,"journal":{"name":"2017 4th International Conference on Signal Processing, Computing and Control (ISPCC)","volume":"443 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123963903","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-09-01DOI: 10.1109/ISPCC.2017.8269661
Durgesh Nandan, Anurag Mahajan, J. Kanungo
An efficient hardware implementation of logarithmic operations is a good choice in place of binary arithmetic operations. In this paper, we suggest an efficient antilogarithmic converter by using 11-region bit-level manipulation scheme by using the error correction scheme. The proposed hardware minimization technique provides a hardware (area, delay & power) efficient implementation at the same error cost. Existing and proposed antilogarithmic converters design is implemented on Xilinx ISE 12.1. Both converters design are evaluated on the Synopsys design compiler by using SAED 65 nm CMOS library and compared the results concerning of Data Arrival Time (DAT), Area, Power, Area Delay Product (ADP), and Energy. The proposed converter involves 52.33 % less ADP and 41.05 % Energy in comparisons of the existing two-bit regions antilogarithmic converter.
{"title":"An efficient antilogarithmic converter by using 11-regions error correction scheme","authors":"Durgesh Nandan, Anurag Mahajan, J. Kanungo","doi":"10.1109/ISPCC.2017.8269661","DOIUrl":"https://doi.org/10.1109/ISPCC.2017.8269661","url":null,"abstract":"An efficient hardware implementation of logarithmic operations is a good choice in place of binary arithmetic operations. In this paper, we suggest an efficient antilogarithmic converter by using 11-region bit-level manipulation scheme by using the error correction scheme. The proposed hardware minimization technique provides a hardware (area, delay & power) efficient implementation at the same error cost. Existing and proposed antilogarithmic converters design is implemented on Xilinx ISE 12.1. Both converters design are evaluated on the Synopsys design compiler by using SAED 65 nm CMOS library and compared the results concerning of Data Arrival Time (DAT), Area, Power, Area Delay Product (ADP), and Energy. The proposed converter involves 52.33 % less ADP and 41.05 % Energy in comparisons of the existing two-bit regions antilogarithmic converter.","PeriodicalId":142166,"journal":{"name":"2017 4th International Conference on Signal Processing, Computing and Control (ISPCC)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127226466","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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