Pub Date : 2008-05-12DOI: 10.1109/SPI.2008.4558391
A. Ligocka, W. Bandurski
The paper presents a new method of deriving the closed form formula for the output voltage and threshold crossing time for low-loss on-chip upper layer interconnects The threshold crossing time solution for the ramp excitation is derived. The calculation of output voltage of two coupled interconnects for the ramp input is also presented.
{"title":"Using Multiple Scales Method to calculate threshold crossing time for the ramp response for high inductance VLSI interconnects","authors":"A. Ligocka, W. Bandurski","doi":"10.1109/SPI.2008.4558391","DOIUrl":"https://doi.org/10.1109/SPI.2008.4558391","url":null,"abstract":"The paper presents a new method of deriving the closed form formula for the output voltage and threshold crossing time for low-loss on-chip upper layer interconnects The threshold crossing time solution for the ramp excitation is derived. The calculation of output voltage of two coupled interconnects for the ramp input is also presented.","PeriodicalId":142239,"journal":{"name":"2008 12th IEEE Workshop on Signal Propagation on Interconnects","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122334286","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-12DOI: 10.1109/SPI.2008.4558340
A. Scogna, A. Orlandi, V. Ricciuti
In this work the analysis of the signal and the power integrity performances of two different types of EBG structures in presence of single ended and differential striplines is proposed. The two EBG patterns have square patches and double L or meandered branches. The signal quality is measured in terms of the transmission parameter S21 and the eye pattern at the terminations; the power integrity is instead analyzed by means of the noise coefficient from the source to different positions along the planes.
{"title":"Signal and Power Integrity Performances of Striplines in Presence of 2D EBG planes","authors":"A. Scogna, A. Orlandi, V. Ricciuti","doi":"10.1109/SPI.2008.4558340","DOIUrl":"https://doi.org/10.1109/SPI.2008.4558340","url":null,"abstract":"In this work the analysis of the signal and the power integrity performances of two different types of EBG structures in presence of single ended and differential striplines is proposed. The two EBG patterns have square patches and double L or meandered branches. The signal quality is measured in terms of the transmission parameter S21 and the eye pattern at the terminations; the power integrity is instead analyzed by means of the noise coefficient from the source to different positions along the planes.","PeriodicalId":142239,"journal":{"name":"2008 12th IEEE Workshop on Signal Propagation on Interconnects","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121937240","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-12DOI: 10.1109/SPI.2008.4558347
B. Ravelo, A. Pérennec, M. Roy
This paper presents a new method developed to reduce the propagation delay by using a negative group delay (NGD) active circuit. Analytical expressions are proposed to demonstrate the validity of our approach in the case of an RC-transmission line model. The synthesis method of NGD circuits versus the line length is detailed. For a 0.5 Gbit/s digital signal and a 2-cm-long RC-line model, time-domain simulations carried out with a high-frequency circuit simulator showed that the 50% propagation delay was reduced by 94%. Finally, potential applications of this method to compensate for time delays in different interconnect configurations (VLSI, package, on-chip, long-line, ...) are discussed.
{"title":"Application of negative group delay active circuits to reduce the 50% propagation Delay of RC-line model","authors":"B. Ravelo, A. Pérennec, M. Roy","doi":"10.1109/SPI.2008.4558347","DOIUrl":"https://doi.org/10.1109/SPI.2008.4558347","url":null,"abstract":"This paper presents a new method developed to reduce the propagation delay by using a negative group delay (NGD) active circuit. Analytical expressions are proposed to demonstrate the validity of our approach in the case of an RC-transmission line model. The synthesis method of NGD circuits versus the line length is detailed. For a 0.5 Gbit/s digital signal and a 2-cm-long RC-line model, time-domain simulations carried out with a high-frequency circuit simulator showed that the 50% propagation delay was reduced by 94%. Finally, potential applications of this method to compensate for time delays in different interconnect configurations (VLSI, package, on-chip, long-line, ...) are discussed.","PeriodicalId":142239,"journal":{"name":"2008 12th IEEE Workshop on Signal Propagation on Interconnects","volume":"35 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120875129","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-12DOI: 10.1109/SPI.2008.4558367
Jinwook Jang, O. Franza, W. Burleson
Period jitter plays a critical role in global clock distribution design because it directly impacts the time available for logic operation between sequential elements in the presence of time-varying noise. The accurate evaluation of period jitter for a given clock tree topology is not only complicated to establish but also exceedingly time consuming and computer intensive due to its dependency upon many different parameters such as supply noise amplitude, supply noise frequency, clock driver size, physical structures of interconnects, number of clock stages, etc. In this paper, a novel recursive analytical expression is formulated to accurately predict period jitter for general binary global clock distribution trees. Simulation results are presented for a variety of topologies and compared with full-fledged HSPICE models, showing very good accuracy and requiring a fraction of the CPU time. Furthermore, this analytical expression is used to quantify the impact of power supply noise amplitude and frequency on worst-case period jitter and to determine general global clock distribution guidelines for its minimization.
{"title":"Period Jitter Estimation in Global Clock Trees","authors":"Jinwook Jang, O. Franza, W. Burleson","doi":"10.1109/SPI.2008.4558367","DOIUrl":"https://doi.org/10.1109/SPI.2008.4558367","url":null,"abstract":"Period jitter plays a critical role in global clock distribution design because it directly impacts the time available for logic operation between sequential elements in the presence of time-varying noise. The accurate evaluation of period jitter for a given clock tree topology is not only complicated to establish but also exceedingly time consuming and computer intensive due to its dependency upon many different parameters such as supply noise amplitude, supply noise frequency, clock driver size, physical structures of interconnects, number of clock stages, etc. In this paper, a novel recursive analytical expression is formulated to accurately predict period jitter for general binary global clock distribution trees. Simulation results are presented for a variety of topologies and compared with full-fledged HSPICE models, showing very good accuracy and requiring a fraction of the CPU time. Furthermore, this analytical expression is used to quantify the impact of power supply noise amplitude and frequency on worst-case period jitter and to determine general global clock distribution guidelines for its minimization.","PeriodicalId":142239,"journal":{"name":"2008 12th IEEE Workshop on Signal Propagation on Interconnects","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126634604","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-04-28DOI: 10.1109/ICCDCS.2008.4542623
H. Aghababa, N. Masoumi
Time-domain behavior of carbon nanotubes as the future candidates for interconnects is of great importance. In order to analyze an entire circuit containing carbon nanotube interconnects, we need to have an electrical circuit model for carbon nanotubes as well as the rest of the system. Several studies have demonstrated the extracted electrical elements of carbon nanotubes. At this paper, we're going to perform a comprehensive transient analysis on carbon nanotubes to achieve time-domain parameters like delay, rise time and overshoot. An overall transfer function of carbon nanotubes is obtained analytically. Besides, the time-domain quality metrics as well as relative stability based on the variation of the geometry of carbon nanotubes would be analyzed through simulations.
{"title":"Time-Domain Analysis of Carbon Nanotubes","authors":"H. Aghababa, N. Masoumi","doi":"10.1109/ICCDCS.2008.4542623","DOIUrl":"https://doi.org/10.1109/ICCDCS.2008.4542623","url":null,"abstract":"Time-domain behavior of carbon nanotubes as the future candidates for interconnects is of great importance. In order to analyze an entire circuit containing carbon nanotube interconnects, we need to have an electrical circuit model for carbon nanotubes as well as the rest of the system. Several studies have demonstrated the extracted electrical elements of carbon nanotubes. At this paper, we're going to perform a comprehensive transient analysis on carbon nanotubes to achieve time-domain parameters like delay, rise time and overshoot. An overall transfer function of carbon nanotubes is obtained analytically. Besides, the time-domain quality metrics as well as relative stability based on the variation of the geometry of carbon nanotubes would be analyzed through simulations.","PeriodicalId":142239,"journal":{"name":"2008 12th IEEE Workshop on Signal Propagation on Interconnects","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134387853","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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