Pub Date : 2021-06-07DOI: 10.1109/DTS52014.2021.9498055
M. Fradi, M. Machhout
Covid-19 disease has been known as a spreaded epidemic across the whole world that affects millions of people, causing deaths and catastrophic effects. For this reason, Computer Aided Diagnosis System (CAD), consists to be a crucial step using deep learning algorithms. In this context, a CNN network has been proposed using two optimizers networks such as Rmsprop and SGD with momentum.the whole system is implemented on both CPU and GPU with the aim to speed up the implementation time process. Then to have a medical real application which automatically detect the covid-19 class from X-rays images of chest. Classification results achieved in terms of accuracy, specificity and sensitivity 99.22%, 99.65% and 99.45% respectively, outperforming the state of the art. As a result, a medical real time application is achieved for Covid-19 class detection in a short time process.
{"title":"Real-Time Application for Covid-19 Class Detection based CNN Architecture","authors":"M. Fradi, M. Machhout","doi":"10.1109/DTS52014.2021.9498055","DOIUrl":"https://doi.org/10.1109/DTS52014.2021.9498055","url":null,"abstract":"Covid-19 disease has been known as a spreaded epidemic across the whole world that affects millions of people, causing deaths and catastrophic effects. For this reason, Computer Aided Diagnosis System (CAD), consists to be a crucial step using deep learning algorithms. In this context, a CNN network has been proposed using two optimizers networks such as Rmsprop and SGD with momentum.the whole system is implemented on both CPU and GPU with the aim to speed up the implementation time process. Then to have a medical real application which automatically detect the covid-19 class from X-rays images of chest. Classification results achieved in terms of accuracy, specificity and sensitivity 99.22%, 99.65% and 99.45% respectively, outperforming the state of the art. As a result, a medical real time application is achieved for Covid-19 class detection in a short time process.","PeriodicalId":158426,"journal":{"name":"2021 IEEE International Conference on Design & Test of Integrated Micro & Nano-Systems (DTS)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133013563","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-07DOI: 10.1109/DTS52014.2021.9498216
Arjun Narukkanchira Anilkumar, M. El-Sharkawy
Unlike Convolutional Neural Network (CNN), which works on the shift-invariance in image processing, Capsule Networks can understand hierarchical model relations in depth[1]. This aspect of Capsule Networks let them stand out even when models are enormous in size and have accuracy comparable to the CNNs, which are one-tenth of its size. The capsules in various capsule-based networks were cumbersome due to their intricate algorithm. Recent developments in the field of Capsule Networks have contributed to mitigating this problem. This paper focuses on bringing one of the Capsule Network, Residual Capsule Network (RCN) to a comparable size to modern CNNs and thus restating the importance of Capsule Networks. In this paper, Residual Capsule Network V2 (RCN2) is proposed as an efficient and finer version of RCN with a size of 1.95 M parameters and an accuracy of 85.12% for the CIFAR-10 dataset.
{"title":"RCN2: Residual Capsule Network V2","authors":"Arjun Narukkanchira Anilkumar, M. El-Sharkawy","doi":"10.1109/DTS52014.2021.9498216","DOIUrl":"https://doi.org/10.1109/DTS52014.2021.9498216","url":null,"abstract":"Unlike Convolutional Neural Network (CNN), which works on the shift-invariance in image processing, Capsule Networks can understand hierarchical model relations in depth[1]. This aspect of Capsule Networks let them stand out even when models are enormous in size and have accuracy comparable to the CNNs, which are one-tenth of its size. The capsules in various capsule-based networks were cumbersome due to their intricate algorithm. Recent developments in the field of Capsule Networks have contributed to mitigating this problem. This paper focuses on bringing one of the Capsule Network, Residual Capsule Network (RCN) to a comparable size to modern CNNs and thus restating the importance of Capsule Networks. In this paper, Residual Capsule Network V2 (RCN2) is proposed as an efficient and finer version of RCN with a size of 1.95 M parameters and an accuracy of 85.12% for the CIFAR-10 dataset.","PeriodicalId":158426,"journal":{"name":"2021 IEEE International Conference on Design & Test of Integrated Micro & Nano-Systems (DTS)","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132065306","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-07DOI: 10.1109/DTS52014.2021.9497889
H. Mestiri, I. Barraj, Mohsen Machhout
The third family Secure Hash Algorithm cryptographic function, named KECCAK, is implemented in cryptographic circuits to assure high security level to any system which necessitates hashing as the generation of random numbers and the data integrity checking. One of the most efficient physical attacks against KECCAK hardware implementation is the fault attacks which can extract the secret data. Until today, a few KECCAK fault detection schemes against the fault attacks have been presented. In this paper, in order to provide a high level of security against fault attacks, we perform a detailed fault analysis to estimate the impact of fault attacks against the KECCAK implementation. We then propose an efficient error detection scheme based on the KECCAK architecture modification. For this reason, the round of KECCAK is divided into two half rounds and a KECCAK pipeline register is implemented between them. The proposed scheme is independent of the method the KECCAK is implemented. Thus, it can be applied to both the pipeline and iterative architectures.To evaluate the KECCAK detection scheme robustness against faults injection attacks, we perform fault injection attacks and we determined the fault detection capability; it is about 99.997%. We have modeled the KECCAK detection scheme using the VHDL hardware language and through hardware FPGA implementation, the FPGA results demonstrate that our scheme can efficiently secure the KECCAK implementation against fault attacks. It can be simply implemented with low complexity. In addition, the FPGA implementation performances prove the low slice area overhead and the high working frequency for the proposed KECCAK detection scheme.
{"title":"Analysis and Detection of Errors in KECCAK Hardware Implementation","authors":"H. Mestiri, I. Barraj, Mohsen Machhout","doi":"10.1109/DTS52014.2021.9497889","DOIUrl":"https://doi.org/10.1109/DTS52014.2021.9497889","url":null,"abstract":"The third family Secure Hash Algorithm cryptographic function, named KECCAK, is implemented in cryptographic circuits to assure high security level to any system which necessitates hashing as the generation of random numbers and the data integrity checking. One of the most efficient physical attacks against KECCAK hardware implementation is the fault attacks which can extract the secret data. Until today, a few KECCAK fault detection schemes against the fault attacks have been presented. In this paper, in order to provide a high level of security against fault attacks, we perform a detailed fault analysis to estimate the impact of fault attacks against the KECCAK implementation. We then propose an efficient error detection scheme based on the KECCAK architecture modification. For this reason, the round of KECCAK is divided into two half rounds and a KECCAK pipeline register is implemented between them. The proposed scheme is independent of the method the KECCAK is implemented. Thus, it can be applied to both the pipeline and iterative architectures.To evaluate the KECCAK detection scheme robustness against faults injection attacks, we perform fault injection attacks and we determined the fault detection capability; it is about 99.997%. We have modeled the KECCAK detection scheme using the VHDL hardware language and through hardware FPGA implementation, the FPGA results demonstrate that our scheme can efficiently secure the KECCAK implementation against fault attacks. It can be simply implemented with low complexity. In addition, the FPGA implementation performances prove the low slice area overhead and the high working frequency for the proposed KECCAK detection scheme.","PeriodicalId":158426,"journal":{"name":"2021 IEEE International Conference on Design & Test of Integrated Micro & Nano-Systems (DTS)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116928461","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-07DOI: 10.1109/DTS52014.2021.9497916
Mohamed Boussif, Oussema Bouferas, Noureddine Aloui, A. Cherif
In this paper, we propose a novel robust blind crypto-watermarking method for medical images security based on hiding of DICOM (Digital Imaging and Communications in Medicine) patient information (patient name, patient ID, patient old…) in the medical imaging. The DICOM patient information are encrypted using the AES (Advanced Encryption Standard) standard algorithm before its insertion in the medical imaging. The medical imaging is divided in blocks of 8x8, in each we insert 1-bit of the encrypted watermark in the hybrid transform domain by applying respectively the 2D-LWT (Lifting wavelet transforms), the 2D-DCT (discrete cosine transforms), and the SVD (singular value decomposition). The scheme is tested by applying various attacks such as noise, filtering and compression. Experimental results show that the watermark (patient information) is imperceptible in the imaging and the test against attack shows the good robustness of the proposed algorithm.
本文提出了一种基于医学图像中DICOM (Digital Imaging and Communications In Medicine)患者信息(患者姓名、患者ID、患者年龄等)隐藏的医学图像鲁棒盲加密水印方法。DICOM患者信息在插入医学成像之前使用AES(高级加密标准)标准算法进行加密。将医学图像划分为8x8的块，在每个块中分别应用2D-LWT(提升小波变换)、2D-DCT(离散余弦变换)和SVD(奇异值分解)在混合变换域中插入1比特的加密水印。通过噪声、滤波和压缩等多种攻击对该方案进行了测试。实验结果表明，水印(患者信息)在图像中是不可察觉的，抗攻击测试表明该算法具有良好的鲁棒性。
{"title":"A Novel Robust Blind AES/LWT+DCT+SVD-Based Crypto-Watermarking schema for DICOM Images Security","authors":"Mohamed Boussif, Oussema Bouferas, Noureddine Aloui, A. Cherif","doi":"10.1109/DTS52014.2021.9497916","DOIUrl":"https://doi.org/10.1109/DTS52014.2021.9497916","url":null,"abstract":"In this paper, we propose a novel robust blind crypto-watermarking method for medical images security based on hiding of DICOM (Digital Imaging and Communications in Medicine) patient information (patient name, patient ID, patient old…) in the medical imaging. The DICOM patient information are encrypted using the AES (Advanced Encryption Standard) standard algorithm before its insertion in the medical imaging. The medical imaging is divided in blocks of 8x8, in each we insert 1-bit of the encrypted watermark in the hybrid transform domain by applying respectively the 2D-LWT (Lifting wavelet transforms), the 2D-DCT (discrete cosine transforms), and the SVD (singular value decomposition). The scheme is tested by applying various attacks such as noise, filtering and compression. Experimental results show that the watermark (patient information) is imperceptible in the imaging and the test against attack shows the good robustness of the proposed algorithm.","PeriodicalId":158426,"journal":{"name":"2021 IEEE International Conference on Design & Test of Integrated Micro & Nano-Systems (DTS)","volume":"600 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123161406","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-07DOI: 10.1109/DTS52014.2021.9498132
S. Abdennadher
The integration of High-bandwidth memory (HBM), is essentially one of the first proof points of in-package integration of heterogeneous silicon that gained steam using advanced packaging. Intel has demonstrated heterogenous integration through chiplet architecture and disaggregation in multiple products and different market segments. With the chiplet model gaining momentum as an alternative to developing monolithic SoC designs, which are becoming more complex and expensive at each node, Test is one of the major enablers of a wider adoption and development of chiplet ecosystem. Die-to-die (D2D) interconnect between chiplets raises complex test challenges, which are driving new standards and DfT approaches to advanced-package testing. This paper addresses these test challenges and emerging solutions for testing D2D interconnect in a disaggregated SoC design.
{"title":"Testing Inter-Chiplet Communication Interconnects in a Disaggregated SoC Design","authors":"S. Abdennadher","doi":"10.1109/DTS52014.2021.9498132","DOIUrl":"https://doi.org/10.1109/DTS52014.2021.9498132","url":null,"abstract":"The integration of High-bandwidth memory (HBM), is essentially one of the first proof points of in-package integration of heterogeneous silicon that gained steam using advanced packaging. Intel has demonstrated heterogenous integration through chiplet architecture and disaggregation in multiple products and different market segments. With the chiplet model gaining momentum as an alternative to developing monolithic SoC designs, which are becoming more complex and expensive at each node, Test is one of the major enablers of a wider adoption and development of chiplet ecosystem. Die-to-die (D2D) interconnect between chiplets raises complex test challenges, which are driving new standards and DfT approaches to advanced-package testing. This paper addresses these test challenges and emerging solutions for testing D2D interconnect in a disaggregated SoC design.","PeriodicalId":158426,"journal":{"name":"2021 IEEE International Conference on Design & Test of Integrated Micro & Nano-Systems (DTS)","volume":"120 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123230470","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-07DOI: 10.1109/DTS52014.2021.9498259
K. Lahbacha, H. Belgacem, W. Dghais, F. Zayer, A. Maffucci
This paper presents one-diode-one resistor-one-resistor-one-diode (1D1R-1R1D) based Resistive Random Access Memory (RRAM) crossbar architecture and introduces the Complementary Resistive Switching (CRS) structure as alternative improved strategies for the electrothermal RRAM integration. Signal integrity issue is mitigated by using the CRS topology. The CRS based RRAM integration as a single memory cross-point cell avoids the need for extra elements (i.e., diodes, transistors...) which in turn facilitates the prototyping process and increases the data stored in the targeted cross-point device. On the other hand, the alternative 1D1R-1R1D, compared to the 1D1R structure provides a new arrangement for diodes and memory cells, which allows resistive switching for the entire crossbar array. The proposed architecture leads to 2x memory density improvement with the same polarization conditions by rectifying the reverse integration of the diodes.
{"title":"Electrothermal RRAM Crossbar Improvement with 3-D CRS and 1D1R-1R1D Architectures","authors":"K. Lahbacha, H. Belgacem, W. Dghais, F. Zayer, A. Maffucci","doi":"10.1109/DTS52014.2021.9498259","DOIUrl":"https://doi.org/10.1109/DTS52014.2021.9498259","url":null,"abstract":"This paper presents one-diode-one resistor-one-resistor-one-diode (1D1R-1R1D) based Resistive Random Access Memory (RRAM) crossbar architecture and introduces the Complementary Resistive Switching (CRS) structure as alternative improved strategies for the electrothermal RRAM integration. Signal integrity issue is mitigated by using the CRS topology. The CRS based RRAM integration as a single memory cross-point cell avoids the need for extra elements (i.e., diodes, transistors...) which in turn facilitates the prototyping process and increases the data stored in the targeted cross-point device. On the other hand, the alternative 1D1R-1R1D, compared to the 1D1R structure provides a new arrangement for diodes and memory cells, which allows resistive switching for the entire crossbar array. The proposed architecture leads to 2x memory density improvement with the same polarization conditions by rectifying the reverse integration of the diodes.","PeriodicalId":158426,"journal":{"name":"2021 IEEE International Conference on Design & Test of Integrated Micro & Nano-Systems (DTS)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125519653","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-07DOI: 10.1109/DTS52014.2021.9498056
M. Rahmani, Mounica Patnala, T. Ytterdal, M. Rizkalla
The fifth generation (5G) wireless technology will provide the nation’s future telecommunications network, featuring higher bandwidth and data rates with lower delay and power consumption. This shift facilitates the ultra-level of integration, for systems loaded with embedded sensors that are enabled by this technology. A few challenges remain regarding the standards to proper interfacing, security for cellular based services, and ability of portable devices to be employed in this technology. These challenges include high-speed amplifiers and signal processors. Millimeter wave communications with frequencies above 10 GHz for mobile networks may be required to meet the propagation quality demands of this technology. This paper proposes the Graphene Nano Ribbon Field Effect Transistor (GNRFET) device as a potential candidate that fits well in this technology, featuring high frequency amplifiers and high switching speed in digital circuits with ultra-low power consumption. These advantages may be attributed to the high mobility and mean free path of the device, leading to major ballistic carrier transport. The simulation was conducted at a switching speed in the order of 10GHz and 0.7V supply. The device was also employed for high frequency amplifiers, achieving as much as 5.1 THz gain bandwidth product (70GHz at a gain of 75), with very clean output signals. Near 115 dBs attenuation losses for harmonics was determined within the operating bandwidth. This paper details the device model, circuit design, and power consumption, suitable for the 5-G communication system. The nanoscale size of the device provides the ultra-level of integration, incorporating the embedded and IoT devices supporting this technology.
{"title":"Characterization of GNRFET Devices for Applications towards 5G Communication","authors":"M. Rahmani, Mounica Patnala, T. Ytterdal, M. Rizkalla","doi":"10.1109/DTS52014.2021.9498056","DOIUrl":"https://doi.org/10.1109/DTS52014.2021.9498056","url":null,"abstract":"The fifth generation (5G) wireless technology will provide the nation’s future telecommunications network, featuring higher bandwidth and data rates with lower delay and power consumption. This shift facilitates the ultra-level of integration, for systems loaded with embedded sensors that are enabled by this technology. A few challenges remain regarding the standards to proper interfacing, security for cellular based services, and ability of portable devices to be employed in this technology. These challenges include high-speed amplifiers and signal processors. Millimeter wave communications with frequencies above 10 GHz for mobile networks may be required to meet the propagation quality demands of this technology. This paper proposes the Graphene Nano Ribbon Field Effect Transistor (GNRFET) device as a potential candidate that fits well in this technology, featuring high frequency amplifiers and high switching speed in digital circuits with ultra-low power consumption. These advantages may be attributed to the high mobility and mean free path of the device, leading to major ballistic carrier transport. The simulation was conducted at a switching speed in the order of 10GHz and 0.7V supply. The device was also employed for high frequency amplifiers, achieving as much as 5.1 THz gain bandwidth product (70GHz at a gain of 75), with very clean output signals. Near 115 dBs attenuation losses for harmonics was determined within the operating bandwidth. This paper details the device model, circuit design, and power consumption, suitable for the 5-G communication system. The nanoscale size of the device provides the ultra-level of integration, incorporating the embedded and IoT devices supporting this technology.","PeriodicalId":158426,"journal":{"name":"2021 IEEE International Conference on Design & Test of Integrated Micro & Nano-Systems (DTS)","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124680854","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-07DOI: 10.1109/DTS52014.2021.9497926
Maroua Moslah, K. Djebbi, C. Tlili, C. Dridi, Deqiang Wang
Herein, we develop a fluorescent sensor for simple detection of miRNA-10b, which combines the fluorescence quenching ability of graphene oxide (GO) and the duplex-specific nuclease (DSN) mediated target recycling amplification. Our sensor exhibits desirable sensitivity for miRNA-10b with a 530 fM detection limit that could be achieved within 75 min. Furthermore, our sensor showed good selectivity for discriminating target miRNA and other microRNAs.
{"title":"Development of graphene oxide-based fluorescent sensing nanoplatform for microRNA-10b detection","authors":"Maroua Moslah, K. Djebbi, C. Tlili, C. Dridi, Deqiang Wang","doi":"10.1109/DTS52014.2021.9497926","DOIUrl":"https://doi.org/10.1109/DTS52014.2021.9497926","url":null,"abstract":"Herein, we develop a fluorescent sensor for simple detection of miRNA-10b, which combines the fluorescence quenching ability of graphene oxide (GO) and the duplex-specific nuclease (DSN) mediated target recycling amplification. Our sensor exhibits desirable sensitivity for miRNA-10b with a 530 fM detection limit that could be achieved within 75 min. Furthermore, our sensor showed good selectivity for discriminating target miRNA and other microRNAs.","PeriodicalId":158426,"journal":{"name":"2021 IEEE International Conference on Design & Test of Integrated Micro & Nano-Systems (DTS)","volume":"157 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114388168","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-07DOI: 10.1109/DTS52014.2021.9498121
S. Joshi, M. El-Sharkawy
The top-performing deep CNN (DCNN) architectures are presented every year based on their compatibility and performance ability on the embedded edge applications, significantly for image classification. There are many obstacles in making these neural network architectures hardware friendly due to the limited memory, lesser computational resources, and the energy requirements of these devices. The addition of Bottleneck modules has further helped this classification problem, which explores the channel interdependencies, using either depthwise or groupwise convolutional features. The classical inverted residual block, a well-known design methodology, has now gained more attention due to its growing popularity in portable applications. This paper presents a mutated version of Harmonious Bottlenecks (DHbneck) with a Flipped version of Inverted Residual (FIR), which outperforms the existing HBONet architecture by giving the best accuracy value and the miniaturized model size. This FIR block performs identity mapping and spatial transformation at its higher dimensions, unlike the existing concept of inverted residual. The devised architecture is tested and validated using CIFAR-10 public dataset. The baseline HBONet architecture has an accuracy of 80.97% when tested on CIFAR-10 dataset and the model’s size is 22 MB. In contrast, the proposed architecture HBONext has an improved validation accuracy of 88.30% with a model reduction to a size of 7.66 MB.
{"title":"HBONext: HBONet with Flipped Inverted Residual","authors":"S. Joshi, M. El-Sharkawy","doi":"10.1109/DTS52014.2021.9498121","DOIUrl":"https://doi.org/10.1109/DTS52014.2021.9498121","url":null,"abstract":"The top-performing deep CNN (DCNN) architectures are presented every year based on their compatibility and performance ability on the embedded edge applications, significantly for image classification. There are many obstacles in making these neural network architectures hardware friendly due to the limited memory, lesser computational resources, and the energy requirements of these devices. The addition of Bottleneck modules has further helped this classification problem, which explores the channel interdependencies, using either depthwise or groupwise convolutional features. The classical inverted residual block, a well-known design methodology, has now gained more attention due to its growing popularity in portable applications. This paper presents a mutated version of Harmonious Bottlenecks (DHbneck) with a Flipped version of Inverted Residual (FIR), which outperforms the existing HBONet architecture by giving the best accuracy value and the miniaturized model size. This FIR block performs identity mapping and spatial transformation at its higher dimensions, unlike the existing concept of inverted residual. The devised architecture is tested and validated using CIFAR-10 public dataset. The baseline HBONet architecture has an accuracy of 80.97% when tested on CIFAR-10 dataset and the model’s size is 22 MB. In contrast, the proposed architecture HBONext has an improved validation accuracy of 88.30% with a model reduction to a size of 7.66 MB.","PeriodicalId":158426,"journal":{"name":"2021 IEEE International Conference on Design & Test of Integrated Micro & Nano-Systems (DTS)","volume":"117 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124194114","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-07DOI: 10.1109/DTS52014.2021.9498186
Amira Mehri, N. Belhadj, David Parello, A. Mtibaa
This paper presents an intra-prediction study comparing two software’s coding efficiency performance: the Versatile Video Coding (VVC) and the High-Efficiency Video Coding (HEVC). The VVC codec is a new video coding standard considered to improve its preceding standard HEVC (H.265). The primary goal of VVC is to enhance compression performance relative to existing standards. In this work, we establish two primary purposes; the first is to compare the complexity of these encoders, the second is to use the Bjontegaard metric for evaluating the coding efficiency compression of each standard.
{"title":"Intra-Prediction Rate-Distortion of Next-Generation VVC and HEVC Encoders","authors":"Amira Mehri, N. Belhadj, David Parello, A. Mtibaa","doi":"10.1109/DTS52014.2021.9498186","DOIUrl":"https://doi.org/10.1109/DTS52014.2021.9498186","url":null,"abstract":"This paper presents an intra-prediction study comparing two software’s coding efficiency performance: the Versatile Video Coding (VVC) and the High-Efficiency Video Coding (HEVC). The VVC codec is a new video coding standard considered to improve its preceding standard HEVC (H.265). The primary goal of VVC is to enhance compression performance relative to existing standards. In this work, we establish two primary purposes; the first is to compare the complexity of these encoders, the second is to use the Bjontegaard metric for evaluating the coding efficiency compression of each standard.","PeriodicalId":158426,"journal":{"name":"2021 IEEE International Conference on Design & Test of Integrated Micro & Nano-Systems (DTS)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130190467","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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