Pub Date : 2020-12-21DOI: 10.46300/91015.2020.14.14
S. H. Sumantri, Suyono Thamrin, I. Apriyanto, E. Suhardono, Beny Rudiawan, Arica Dwi Susanto
PT. XYZ in Surabaya is engaged in the production of commercial ships, providing ship repair and maintenance services as well as general engineering with specifications based on orders. Along with the development of the technology industry, ship production requires every shipyard to evaluate the system used. The time delay is the problem of building a 60 meter commercial ship. The Precedence Diagram Method (PDM) is a method for scheduling project time and showing critical trajectories of project activities. The results showed that in the project scheduling, there are 13 activities that have a zero value or critical activity which are activities Hull Fabrication, Hull Sub Assembly, Hull Assembly, Hull Erection, Blasting and Painting Raw Material, Finishing Hull, Anode, Machinery Outfitting, Cabling, Computing and Information, Machinery Commisioning, Equipment Commisioning, Harbour Acceptance Test, Yard Trial, Delivery to Customer So that it needs more strict control and supervision from the contractor in carrying out the activities of the 60 meter commercial ship building project activities for each activity/activity so that it does not experience delays and the project can be completed on time.
{"title":"Determination of Critical Pattern of 60 Meter Ship Construction Project Using Precedence Diagram Method (PDM)","authors":"S. H. Sumantri, Suyono Thamrin, I. Apriyanto, E. Suhardono, Beny Rudiawan, Arica Dwi Susanto","doi":"10.46300/91015.2020.14.14","DOIUrl":"https://doi.org/10.46300/91015.2020.14.14","url":null,"abstract":"PT. XYZ in Surabaya is engaged in the production of commercial ships, providing ship repair and maintenance services as well as general engineering with specifications based on orders. Along with the development of the technology industry, ship production requires every shipyard to evaluate the system used. The time delay is the problem of building a 60 meter commercial ship. The Precedence Diagram Method (PDM) is a method for scheduling project time and showing critical trajectories of project activities. The results showed that in the project scheduling, there are 13 activities that have a zero value or critical activity which are activities Hull Fabrication, Hull Sub Assembly, Hull Assembly, Hull Erection, Blasting and Painting Raw Material, Finishing Hull, Anode, Machinery Outfitting, Cabling, Computing and Information, Machinery Commisioning, Equipment Commisioning, Harbour Acceptance Test, Yard Trial, Delivery to Customer So that it needs more strict control and supervision from the contractor in carrying out the activities of the 60 meter commercial ship building project activities for each activity/activity so that it does not experience delays and the project can be completed on time.","PeriodicalId":158702,"journal":{"name":"International Journal of Systems Applications, Engineering & Development","volume":"38-40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123637663","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-21DOI: 10.46300/91015.2020.14.19
S. Arulpriya, P. Kumar
Image processing devices plays a vital role in several applications like medical, security, biometric etc. The devices ranges from portable size to larger machines with and without Human Computer Interface possibilities. As the image processing and human computer interface system application requires higher memory requirements, the power and area should be small. Searching of data is a high priority work in image classification. To perform high speed search through hardware Content Addressable Memory is used. But the circuit suffers from higher power consumption, precharging issues and low performance. For longer word length the elimination of precharge is needed. So for high speed applications self-controlled precharge-free CAM (SCPF-CAM) is suitable. A 4T hybrid self controlled pre charge free Content Addressable Memory is proposed in this paper using CMOS 32nm technology. The observation shows that the circuit works at high speed, minimizes the search time and has high performance operation. When compared to the conventional SCPF-CAM, 8T CAM the proposed design reduces the number of transistors. The reduction in area is about approximately 20% and can be used in low power and low energy applications. In Synopsis HSPICE Predictive technology models were used for the implementation in 32nm CMOS technology. The work will be extended in future using FinFET technology where the leakage current can be minimized.
{"title":"Low power CMOS based Self Controlled Precharge Free Content Addressable Memory with Minimum area for Image Processing Devices","authors":"S. Arulpriya, P. Kumar","doi":"10.46300/91015.2020.14.19","DOIUrl":"https://doi.org/10.46300/91015.2020.14.19","url":null,"abstract":"Image processing devices plays a vital role in several applications like medical, security, biometric etc. The devices ranges from portable size to larger machines with and without Human Computer Interface possibilities. As the image processing and human computer interface system application requires higher memory requirements, the power and area should be small. Searching of data is a high priority work in image classification. To perform high speed search through hardware Content Addressable Memory is used. But the circuit suffers from higher power consumption, precharging issues and low performance. For longer word length the elimination of precharge is needed. So for high speed applications self-controlled precharge-free CAM (SCPF-CAM) is suitable. A 4T hybrid self controlled pre charge free Content Addressable Memory is proposed in this paper using CMOS 32nm technology. The observation shows that the circuit works at high speed, minimizes the search time and has high performance operation. When compared to the conventional SCPF-CAM, 8T CAM the proposed design reduces the number of transistors. The reduction in area is about approximately 20% and can be used in low power and low energy applications. In Synopsis HSPICE Predictive technology models were used for the implementation in 32nm CMOS technology. The work will be extended in future using FinFET technology where the leakage current can be minimized.","PeriodicalId":158702,"journal":{"name":"International Journal of Systems Applications, Engineering & Development","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130996223","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-21DOI: 10.18178/ijeetc.9.3.132-141
T. Ettaghzouti, M. Bchir, N. Hassen
This paper describes a new CMOS realization of differential difference current conveyor circuit. The proposed design offers enhanced characteristics compared to DDCC circuits previously exhibited in the literature. It is characterized by a wide dynamic range with good accuracy thanks to use of adaptive biasing circuit instead of a constant bias current source as well as a wide bandwidth (560 MHz) and a low parasitic resistance at terminal X about 6.86 Ω. A voltage mode instrumentation amplifier circuit (VMIA) composed of a DDCC circuit and two active grounded resistances is shown as application. The proposed VMIA circuit is intended for high frequency applications. This configuration offers significant improvement in accuracy as compared to the state of the art. It is characterized by a controllable gain, a large dynamic range with THD less than 0.27 %, a low noise density (22 nV/Hz1/2) with a power consumption about 0.492 mW and a wide bandwidth nearly 83 MHz. All proposed circuits are simulated by TSPICE using CMOS 0.18 μm TSMC technology with ± 0.8 V supply voltage to verify the theoretical results.
{"title":"High CMRR Voltage Mode Instrumentation Amplifier Using a New CMOS Differential Difference Current Conveyor Realization","authors":"T. Ettaghzouti, M. Bchir, N. Hassen","doi":"10.18178/ijeetc.9.3.132-141","DOIUrl":"https://doi.org/10.18178/ijeetc.9.3.132-141","url":null,"abstract":"This paper describes a new CMOS realization of differential difference current conveyor circuit. The proposed design offers enhanced characteristics compared to DDCC circuits previously exhibited in the literature. It is characterized by a wide dynamic range with good accuracy thanks to use of adaptive biasing circuit instead of a constant bias current source as well as a wide bandwidth (560 MHz) and a low parasitic resistance at terminal X about 6.86 Ω. A voltage mode instrumentation amplifier circuit (VMIA) composed of a DDCC circuit and two active grounded resistances is shown as application. The proposed VMIA circuit is intended for high frequency applications. This configuration offers significant improvement in accuracy as compared to the state of the art. It is characterized by a controllable gain, a large dynamic range with THD less than 0.27 %, a low noise density (22 nV/Hz1/2) with a power consumption about 0.492 mW and a wide bandwidth nearly 83 MHz. All proposed circuits are simulated by TSPICE using CMOS 0.18 μm TSMC technology with ± 0.8 V supply voltage to verify the theoretical results.","PeriodicalId":158702,"journal":{"name":"International Journal of Systems Applications, Engineering & Development","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134046853","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-21DOI: 10.46300/91015.2020.14.10
V. Vijay, Sadulla Shaik, P. C. Shekar, P. Manoja, R. Abhinaya, M. Rachana, N. Nikhil
ince last few years, the tiny size of MOSFET, that is less than tens of nanometers, created some operational problems such as increased gate-oxide leakage, amplified junction leakage, high sub-threshold conduction, and reduced output resistance. To overcome the above challenges, FinFET has the advantages of an increase in the operating speed, reduced power consumption, decreased static leakage current is used to realize the majority of the applications by replacing MOSFET. By considering the attractive features of the FinFET, an ALU is designed as an application. In the digital processor, the arithmetic and logical operations are executed using the Arithmetic logic unit (ALU). In this paper, power efficient 8-bit ALU is designed with Full adder (FA) and multiplexers composed of Gate diffusion input (GDI) which gained designer's choice for digital combinational circuit realization at minimum power consumption. The design is simulated using Cadence virtuoso with 20nm technology. Comparative performance analysis is carried out in contrast to the other standard circuits by taking the critical performance metrics such as delay, power, and power delay product (PDP), energy-delay product (EDP) metrics into consideration.
{"title":"Design and Performance Evaluation of Energy Efficient 8-Bit ALU At Ultra Low Supply Voltages Using FinFET With 20nm Technology","authors":"V. Vijay, Sadulla Shaik, P. C. Shekar, P. Manoja, R. Abhinaya, M. Rachana, N. Nikhil","doi":"10.46300/91015.2020.14.10","DOIUrl":"https://doi.org/10.46300/91015.2020.14.10","url":null,"abstract":"ince last few years, the tiny size of MOSFET, that is less than tens of nanometers, created some operational problems such as increased gate-oxide leakage, amplified junction leakage, high sub-threshold conduction, and reduced output resistance. To overcome the above challenges, FinFET has the advantages of an increase in the operating speed, reduced power consumption, decreased static leakage current is used to realize the majority of the applications by replacing MOSFET. By considering the attractive features of the FinFET, an ALU is designed as an application. In the digital processor, the arithmetic and logical operations are executed using the Arithmetic logic unit (ALU). In this paper, power efficient 8-bit ALU is designed with Full adder (FA) and multiplexers composed of Gate diffusion input (GDI) which gained designer's choice for digital combinational circuit realization at minimum power consumption. The design is simulated using Cadence virtuoso with 20nm technology. Comparative performance analysis is carried out in contrast to the other standard circuits by taking the critical performance metrics such as delay, power, and power delay product (PDP), energy-delay product (EDP) metrics into consideration.","PeriodicalId":158702,"journal":{"name":"International Journal of Systems Applications, Engineering & Development","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129264094","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-21DOI: 10.46300/91015.2020.14.9
V. Prasad, Sandya Prasad
The high pace emergence in semiconductor technologies and associated application demands have revitalized industries to explore power efficient, stable and fault tolerant digital communication solutions, particularly for time critical applications operating at higher frequency ranges. Thus strengthening low cost CMOS digital design with Radiation Hardened by Design (RHBD) approach can be of paramount significance compared against the high cost Radiation Hard by Process (RHBP) approach. With this motivation, in this paper a novel and robust All-Digital-Phase Locked Loop (ADPLL) design has been developed for frequency synthesis. Our ADPLL design model encompasses multiple novelties and contributions including Feedback-Divider-Less-Counter (FDLC) based ADPLL, predictive phase-frequency detection (PFD), enhanced Time to Digital Converter (TDC) to detect next-edge occurrence of the reference clock that reduces locking period and complexity. The predictive PFD applies a phase-prediction scheme that delays the clock-edges of the reference frequency with a calibrated amount that it always aligned towards the expected frequency clock edge. It makes TDC to be narrow enough to cover the reference and oscillator jitter. Our proposed ADPLL design applied a narrow range converter (TDC) that assist phase-error prediction, correction and phase detection. The reference clock delay facilitates accurate timing relationship estimation with the variable frequency and hence performs retuning of the variable clock to reduce locking period and reduce noise. The ADPLL design has exhibited satisfactory performance for the frequency synthesis with reference frequency of 20MHz and the synthesis frequency of 2.4 GHz meeting radiation hardened features. The simulation results has revealed that the proposed Rad Hard ADPLL design can be a potential solution for space communication systems by maintaining low jitter of 340ps and power consumption of 371.7mW, as the narrow range TDC designed can detect sample radiation induced impulse noise of 20ns, 1mV and correct it.
{"title":"A Robust and Efficient Fault-Resilient RadHard ADPLL","authors":"V. Prasad, Sandya Prasad","doi":"10.46300/91015.2020.14.9","DOIUrl":"https://doi.org/10.46300/91015.2020.14.9","url":null,"abstract":"The high pace emergence in semiconductor technologies and associated application demands have revitalized industries to explore power efficient, stable and fault tolerant digital communication solutions, particularly for time critical applications operating at higher frequency ranges. Thus strengthening low cost CMOS digital design with Radiation Hardened by Design (RHBD) approach can be of paramount significance compared against the high cost Radiation Hard by Process (RHBP) approach. With this motivation, in this paper a novel and robust All-Digital-Phase Locked Loop (ADPLL) design has been developed for frequency synthesis. Our ADPLL design model encompasses multiple novelties and contributions including Feedback-Divider-Less-Counter (FDLC) based ADPLL, predictive phase-frequency detection (PFD), enhanced Time to Digital Converter (TDC) to detect next-edge occurrence of the reference clock that reduces locking period and complexity. The predictive PFD applies a phase-prediction scheme that delays the clock-edges of the reference frequency with a calibrated amount that it always aligned towards the expected frequency clock edge. It makes TDC to be narrow enough to cover the reference and oscillator jitter. Our proposed ADPLL design applied a narrow range converter (TDC) that assist phase-error prediction, correction and phase detection. The reference clock delay facilitates accurate timing relationship estimation with the variable frequency and hence performs retuning of the variable clock to reduce locking period and reduce noise. The ADPLL design has exhibited satisfactory performance for the frequency synthesis with reference frequency of 20MHz and the synthesis frequency of 2.4 GHz meeting radiation hardened features. The simulation results has revealed that the proposed Rad Hard ADPLL design can be a potential solution for space communication systems by maintaining low jitter of 340ps and power consumption of 371.7mW, as the narrow range TDC designed can detect sample radiation induced impulse noise of 20ns, 1mV and correct it.","PeriodicalId":158702,"journal":{"name":"International Journal of Systems Applications, Engineering & Development","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114989845","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-21DOI: 10.46300/91015.2020.14.21
Alaka Pradhan, S. K. Sarangi, K. C. Bhuyan
Nowadays, the real-time speaker recognition system is very popular due to its cost-effective nature. However, it is a very challenging one to produce a more efficient speaker identification system. In our work, we work on a multi-lingual real-time speaker identification system. We work in a novel way to enhance the efficiency of the said system. We take some real speech signals and use different speech enhancement methods and our proposed voice activity method (VAD) to enhance the efficiency of said system. By doing so, we increase the accuracy of the said system relatively by 2% as compared to existing methods.
{"title":"A Novel Approach to Increase the Efficiency of a Multi-lingual Real-time Speaker Identification System","authors":"Alaka Pradhan, S. K. Sarangi, K. C. Bhuyan","doi":"10.46300/91015.2020.14.21","DOIUrl":"https://doi.org/10.46300/91015.2020.14.21","url":null,"abstract":"Nowadays, the real-time speaker recognition system is very popular due to its cost-effective nature. However, it is a very challenging one to produce a more efficient speaker identification system. In our work, we work on a multi-lingual real-time speaker identification system. We work in a novel way to enhance the efficiency of the said system. We take some real speech signals and use different speech enhancement methods and our proposed voice activity method (VAD) to enhance the efficiency of said system. By doing so, we increase the accuracy of the said system relatively by 2% as compared to existing methods.","PeriodicalId":158702,"journal":{"name":"International Journal of Systems Applications, Engineering & Development","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130097056","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-21DOI: 10.46300/91015.2020.14.16
E. Benyoussef, S. Barkat
This work relates to the study of direct torque control of the double star induction machine drive fed by two five-level diode-clamped inverters. The analysis of the three-phase direct torque control shows that this concept can be extended easily to double star induction machine even when it is fed by a multilevel inverter. Diode-clamped inverter, as one of the prominent multilevel inverters, has several advantages like high voltage and low current waveform distortion. However, it suffers from the problem of neutral point potential variation. The variation causes an unbalance in the DC-link voltage levels and increases consequently the current waveform distortion. This problem can be solved in satisfactory way by using multilevel direct torque control equipped by a balancing strategy. The simulation results, illustrating the steady state and dynamic performances, prove the effectiveness of the proposed control approach.
{"title":"Five-level Direct Torque Control with Balancing Strategy of Double Star Induction Machine","authors":"E. Benyoussef, S. Barkat","doi":"10.46300/91015.2020.14.16","DOIUrl":"https://doi.org/10.46300/91015.2020.14.16","url":null,"abstract":"This work relates to the study of direct torque control of the double star induction machine drive fed by two five-level diode-clamped inverters. The analysis of the three-phase direct torque control shows that this concept can be extended easily to double star induction machine even when it is fed by a multilevel inverter. Diode-clamped inverter, as one of the prominent multilevel inverters, has several advantages like high voltage and low current waveform distortion. However, it suffers from the problem of neutral point potential variation. The variation causes an unbalance in the DC-link voltage levels and increases consequently the current waveform distortion. This problem can be solved in satisfactory way by using multilevel direct torque control equipped by a balancing strategy. The simulation results, illustrating the steady state and dynamic performances, prove the effectiveness of the proposed control approach.","PeriodicalId":158702,"journal":{"name":"International Journal of Systems Applications, Engineering & Development","volume":"216 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113984942","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A wood-plastic composite extruder (single screw extruder) was designed, fabricated and evaluated to recycle and produce a product for non-structural purposes. The extruder is separated into four units: The feeding, conveying, heating and forming unit. The material is fed by gravity into a hopper and conveyed by a screw conveyor at a predetermined speed through a heated barrel and the extrudate is metered through the breaker plate and the die. The output rate is directly related to the screw speed. Test samples were produced with the machine and experimental tests were conducted to determine its suitability for non-structural purposes and applications. The performance evaluation test on the machine shows that at speeds of 4rpm and 50.25rpm, the machine performs at 87% and 82% efficiency respectively which makes it effective for production. The machine takes a maximum of 5mins to recycle a batch with an average capacity of 14.04kg/hr at 4rpm and 17.55kg/hr at 50.25rpm. The machine conserves cost and energy due to low specific mechanical energy consumption of 191.21kJ/kg
{"title":"Development of a Single Screw Extruder For The Production of Wood-Plastic Composite","authors":"T. Omoniyi, D. Adesanya","doi":"10.5937/poljteh2003053o","DOIUrl":"https://doi.org/10.5937/poljteh2003053o","url":null,"abstract":"A wood-plastic composite extruder (single screw extruder) was designed, fabricated and evaluated to recycle and produce a product for non-structural purposes. The extruder is separated into four units: The feeding, conveying, heating and forming unit. The material is fed by gravity into a hopper and conveyed by a screw conveyor at a predetermined speed through a heated barrel and the extrudate is metered through the breaker plate and the die. The output rate is directly related to the screw speed. Test samples were produced with the machine and experimental tests were conducted to determine its suitability for non-structural purposes and applications. The performance evaluation test on the machine shows that at speeds of 4rpm and 50.25rpm, the machine performs at 87% and 82% efficiency respectively which makes it effective for production. The machine takes a maximum of 5mins to recycle a batch with an average capacity of 14.04kg/hr at 4rpm and 17.55kg/hr at 50.25rpm. The machine conserves cost and energy due to low specific mechanical energy consumption of 191.21kJ/kg","PeriodicalId":158702,"journal":{"name":"International Journal of Systems Applications, Engineering & Development","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130590413","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-05-07DOI: 10.46300/91015.2020.14.4
After more than thirty years of their establishment, 26 New Cities in Egypt are attracting less people than the informal areas. The main objective of this paper is to form a new vision for liveable sustainable Egyptian new cities that attract people to live in, using the descriptive, analytical, deductive methodologies to achieve the research goals. The research starts with discussing the “NCs” definition and its dimensions, and then it explores the major features of sustainability, explains the relationship between the economic, urban, environmental, and social forces shaping the sustainability in developing the new cities. Afterwards, the research focuses on presenting the current situation of the Egyptian experience in developing new cities in the desert areas and the major pertinent impediments, and then analyses the international experiences of sustainable New Cities, Columbia, Maryland in USA. In addition, the case study analysis is a part of a field visit and surveys done by the researcher during Winter and Summer 2015. Finally, the research draws from the previous analyses, the lessons learned from the American experience, the implications for developing Sustainable NCs from inception through completion, in addition to managing the following on-going operations.
{"title":"Towards Liveable and Sustainable Egyptian New Cities: Learned Lessons from Columbia, Maryland","authors":"","doi":"10.46300/91015.2020.14.4","DOIUrl":"https://doi.org/10.46300/91015.2020.14.4","url":null,"abstract":"After more than thirty years of their establishment, 26 New Cities in Egypt are attracting less people than the informal areas. The main objective of this paper is to form a new vision for liveable sustainable Egyptian new cities that attract people to live in, using the descriptive, analytical, deductive methodologies to achieve the research goals. The research starts with discussing the “NCs” definition and its dimensions, and then it explores the major features of sustainability, explains the relationship between the economic, urban, environmental, and social forces shaping the sustainability in developing the new cities. Afterwards, the research focuses on presenting the current situation of the Egyptian experience in developing new cities in the desert areas and the major pertinent impediments, and then analyses the international experiences of sustainable New Cities, Columbia, Maryland in USA. In addition, the case study analysis is a part of a field visit and surveys done by the researcher during Winter and Summer 2015. Finally, the research draws from the previous analyses, the lessons learned from the American experience, the implications for developing Sustainable NCs from inception through completion, in addition to managing the following on-going operations.","PeriodicalId":158702,"journal":{"name":"International Journal of Systems Applications, Engineering & Development","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-05-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117171075","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-05-04DOI: 10.46300/91015.2020.14.2
This paper was aimed on system design of electric energy converting from thermal energy. This electric energy was harvested by human actions or from human impact on the device. The first part of this article describes principles of thermal energy conversion to electric energy. The second part of this paper describes design of the thermoelectric generator for the autonomous broadcast systems
{"title":"The Power Options for Transmitting Systems Using Thermal Energy Generator","authors":"","doi":"10.46300/91015.2020.14.2","DOIUrl":"https://doi.org/10.46300/91015.2020.14.2","url":null,"abstract":"This paper was aimed on system design of electric energy converting from thermal energy. This electric energy was harvested by human actions or from human impact on the device. The first part of this article describes principles of thermal energy conversion to electric energy. The second part of this paper describes design of the thermoelectric generator for the autonomous broadcast systems","PeriodicalId":158702,"journal":{"name":"International Journal of Systems Applications, Engineering & Development","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130167147","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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