Pub Date : 2015-07-09DOI: 10.1109/ReTIS.2015.7232880
S. Obaidullah, N. Das, C. Halder, K. Roy
In a multi-script country like India, prior identification of script from document images is an essential step before choosing appropriate script specific OCR. The problem becomes more complex and challenging in case of HSI (Handwritten Script Identification). An automatic HSI technique for document images of six popular Indic scripts namely Bangla, Devanagari, Malayalam, Oriya, Roman and Urdu is proposed in this paper. A Block-level approach is followed for the same and initially 34-dimensional feature vector is constructed applying transform based (BRT, BDCT, BFFT and BDT), textural and statistical techniques. Finally using a GAS (Greedy Attribute Selection) method 20 attributes are selected for learning process. Total 600 unconstrained document image blocks of size 512×512 each, are prepared with equal distribution of each script type. The whole dataset is divided into 2:1 ratio for training and testing. Extensive experimentation is carried out for Six-scripts, Tetra-scripts, Tri-scripts and Bi-scripts combinations. Experimental result shows promising and comparable performance.
{"title":"Indic script identification from handwritten document images — An unconstrained block-level approach","authors":"S. Obaidullah, N. Das, C. Halder, K. Roy","doi":"10.1109/ReTIS.2015.7232880","DOIUrl":"https://doi.org/10.1109/ReTIS.2015.7232880","url":null,"abstract":"In a multi-script country like India, prior identification of script from document images is an essential step before choosing appropriate script specific OCR. The problem becomes more complex and challenging in case of HSI (Handwritten Script Identification). An automatic HSI technique for document images of six popular Indic scripts namely Bangla, Devanagari, Malayalam, Oriya, Roman and Urdu is proposed in this paper. A Block-level approach is followed for the same and initially 34-dimensional feature vector is constructed applying transform based (BRT, BDCT, BFFT and BDT), textural and statistical techniques. Finally using a GAS (Greedy Attribute Selection) method 20 attributes are selected for learning process. Total 600 unconstrained document image blocks of size 512×512 each, are prepared with equal distribution of each script type. The whole dataset is divided into 2:1 ratio for training and testing. Extensive experimentation is carried out for Six-scripts, Tetra-scripts, Tri-scripts and Bi-scripts combinations. Experimental result shows promising and comparable performance.","PeriodicalId":161306,"journal":{"name":"2015 IEEE 2nd International Conference on Recent Trends in Information Systems (ReTIS)","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126064712","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-07-09DOI: 10.1109/ReTIS.2015.7232926
Rajneesh Sharma, A. Rana
For the nanoscale MOSFET technology, the strain engineering is emerge as the most important performance booster technique in terms of carrier mobility, low scattering and consequently the high on current. In this paper, the state of art for nanoscale strained MOSFET has been reviewed in terms of performance improvement and manufacturability. Further, the strain engineering along with advanced performance booster technique/structure, raised Source/Drain (S/D), S/D extension engineering (underlap structure), High-K/Metal-gate, Extremely Thin Silicon On Insulator (ETSOI) and multigate device structure, have been studied to provide the guidelines for performance enhancement in nanoscale devices. In above cases, we will focus on reliability, advantages and probable solutions to the related issues. Although strain provide mobility enhancement for both NMOS and PMOS without alleviating leakage current but the use of strain Si in nanoscale MOSFET still create new challenges. The literature review has been extended to cover the various challenges of nanoscale strained MOSFET, scaling of strained MOSFET, mobility limitation in ballistic range and self-heating. The review signify that the strain engineering become the integral part of nanoscale MOSFET due to its various potential benefits without much fabrication overhead.
{"title":"Strained Si: Opportunities and challenges in nanoscale MOSFET","authors":"Rajneesh Sharma, A. Rana","doi":"10.1109/ReTIS.2015.7232926","DOIUrl":"https://doi.org/10.1109/ReTIS.2015.7232926","url":null,"abstract":"For the nanoscale MOSFET technology, the strain engineering is emerge as the most important performance booster technique in terms of carrier mobility, low scattering and consequently the high on current. In this paper, the state of art for nanoscale strained MOSFET has been reviewed in terms of performance improvement and manufacturability. Further, the strain engineering along with advanced performance booster technique/structure, raised Source/Drain (S/D), S/D extension engineering (underlap structure), High-K/Metal-gate, Extremely Thin Silicon On Insulator (ETSOI) and multigate device structure, have been studied to provide the guidelines for performance enhancement in nanoscale devices. In above cases, we will focus on reliability, advantages and probable solutions to the related issues. Although strain provide mobility enhancement for both NMOS and PMOS without alleviating leakage current but the use of strain Si in nanoscale MOSFET still create new challenges. The literature review has been extended to cover the various challenges of nanoscale strained MOSFET, scaling of strained MOSFET, mobility limitation in ballistic range and self-heating. The review signify that the strain engineering become the integral part of nanoscale MOSFET due to its various potential benefits without much fabrication overhead.","PeriodicalId":161306,"journal":{"name":"2015 IEEE 2nd International Conference on Recent Trends in Information Systems (ReTIS)","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127485504","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-07-09DOI: 10.1109/ReTIS.2015.7232878
Rajitha Bakthula, Anjana Tiwari, S. Agarwal
This paper presents a new technique for defect detection in various images like fabric, paper, metal surface, film surface, nonwoven, coated coil and glass surface etc images. To detect such unstructured defects, it is required to analyze the underlying texture information of the image. All of these images have some similar texture properties. These texture features can be achieved through local homogeneity analysis (H-image) such as edges and boundaries which arise due to sudden changes in intensity levels of pixels. The defected regions can be one or more in a texture based image which may vary in shape and gray levels as well, thus the defect detection is a challenging task. Traditional homogeneity based approaches gives the fine edge details as well, some of them can be treated as a defect which is not a defect. So, this paper proposes a new technique to find the local homogeneity image using pixel intensity differences among neighboring pixels. Thereafter for thresholding a DWT (Discrete Wavelet Transform) and Hotelling T2 model are used. The performance of the proposed approach has been evaluated against various measures like precision, specificity, recall, accuracy and error rate. In comparison to the existing H-Image the proposed approach had 98% accuracy when tested on 100 different types of images.
{"title":"A new local homogeneity analysis method based on pixel intensities for image defect detection","authors":"Rajitha Bakthula, Anjana Tiwari, S. Agarwal","doi":"10.1109/ReTIS.2015.7232878","DOIUrl":"https://doi.org/10.1109/ReTIS.2015.7232878","url":null,"abstract":"This paper presents a new technique for defect detection in various images like fabric, paper, metal surface, film surface, nonwoven, coated coil and glass surface etc images. To detect such unstructured defects, it is required to analyze the underlying texture information of the image. All of these images have some similar texture properties. These texture features can be achieved through local homogeneity analysis (H-image) such as edges and boundaries which arise due to sudden changes in intensity levels of pixels. The defected regions can be one or more in a texture based image which may vary in shape and gray levels as well, thus the defect detection is a challenging task. Traditional homogeneity based approaches gives the fine edge details as well, some of them can be treated as a defect which is not a defect. So, this paper proposes a new technique to find the local homogeneity image using pixel intensity differences among neighboring pixels. Thereafter for thresholding a DWT (Discrete Wavelet Transform) and Hotelling T2 model are used. The performance of the proposed approach has been evaluated against various measures like precision, specificity, recall, accuracy and error rate. In comparison to the existing H-Image the proposed approach had 98% accuracy when tested on 100 different types of images.","PeriodicalId":161306,"journal":{"name":"2015 IEEE 2nd International Conference on Recent Trends in Information Systems (ReTIS)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122224199","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-07-09DOI: 10.1109/ReTIS.2015.7232845
Vijaya Kumar, C M Sreedhar, S. Khushu, R. P. Tripathi
Cochlear nerve deficiency (CND) is one of the primary causes of congenital hearing loss experienced by the new-born babies. The objective of this study was to assess the benefit of new diffusion kurtosis method in evaluating neuronal integrity of the cochlear nerve in order to assess cochlear nerve deficiency. In this study, the fourth-order kurtosis tensor has been estimated using the kurtosis model and the parameters such as mean kurtosis, axial kurtosis and radial kurtosis has been computed for the assessment of demyelination status of cochlear nerve. Estimations of these kurtosis parameters were carried out in the locations of internal auditory canal (IAC), lateral lemniscus (LL) and inferior colliculus (IC). The adaptive wavelet transform system was used to remove the rician noise from the diffusion data used for estimation the kurtosis parameters in the kurtosis model. The estimated kurtosis parameters found to be lower in cochlear nerve deficiency patients than normal control cases. The kurtosis parameters found to be capable of providing new tissue microstructural information and neuronal integrity and their demyelination status of cochlear nerve.
{"title":"Diffusion kurtosis model to evaluate the cochlear nerve deficiency in MRI images","authors":"Vijaya Kumar, C M Sreedhar, S. Khushu, R. P. Tripathi","doi":"10.1109/ReTIS.2015.7232845","DOIUrl":"https://doi.org/10.1109/ReTIS.2015.7232845","url":null,"abstract":"Cochlear nerve deficiency (CND) is one of the primary causes of congenital hearing loss experienced by the new-born babies. The objective of this study was to assess the benefit of new diffusion kurtosis method in evaluating neuronal integrity of the cochlear nerve in order to assess cochlear nerve deficiency. In this study, the fourth-order kurtosis tensor has been estimated using the kurtosis model and the parameters such as mean kurtosis, axial kurtosis and radial kurtosis has been computed for the assessment of demyelination status of cochlear nerve. Estimations of these kurtosis parameters were carried out in the locations of internal auditory canal (IAC), lateral lemniscus (LL) and inferior colliculus (IC). The adaptive wavelet transform system was used to remove the rician noise from the diffusion data used for estimation the kurtosis parameters in the kurtosis model. The estimated kurtosis parameters found to be lower in cochlear nerve deficiency patients than normal control cases. The kurtosis parameters found to be capable of providing new tissue microstructural information and neuronal integrity and their demyelination status of cochlear nerve.","PeriodicalId":161306,"journal":{"name":"2015 IEEE 2nd International Conference on Recent Trends in Information Systems (ReTIS)","volume":"15 7","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120882969","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-07-09DOI: 10.1109/ReTIS.2015.7232931
Subhasree Sengupta, A. Sinharay, T. Bakshi
The movement of preplaced cells among a prescribed existing placement to solve a set of worst designed placement related facts - for example, routing problems, timings, integrity of signals and distribution of heat. To solve this design related problems one has to prefer to translate the design. The translation should be as small as possible while retaining the originality of the placement integrity. The current paper proposes a new algorithmic treatment of the above problem through computational geometry. Our theoretical proposals established through experimental proofs.
{"title":"A computational geometry based cell migration technique for VLSI placement problem","authors":"Subhasree Sengupta, A. Sinharay, T. Bakshi","doi":"10.1109/ReTIS.2015.7232931","DOIUrl":"https://doi.org/10.1109/ReTIS.2015.7232931","url":null,"abstract":"The movement of preplaced cells among a prescribed existing placement to solve a set of worst designed placement related facts - for example, routing problems, timings, integrity of signals and distribution of heat. To solve this design related problems one has to prefer to translate the design. The translation should be as small as possible while retaining the originality of the placement integrity. The current paper proposes a new algorithmic treatment of the above problem through computational geometry. Our theoretical proposals established through experimental proofs.","PeriodicalId":161306,"journal":{"name":"2015 IEEE 2nd International Conference on Recent Trends in Information Systems (ReTIS)","volume":"248 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116487791","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-07-09DOI: 10.1109/ReTIS.2015.7232933
Chandrajit Pal, Pabitra Das, S. B. Mandal, A. Chakrabarti, Samik Basu, R. Ghosh
Scale Invariant Feature Transform (SIFT) algorithm is used to generate image features which is very essential for object recognition, feature detection, image matching etc. This paper proposes an optimized hardware architecture for realizing the SIFT algorithm with reversible logic prototyped using Field Programmable Gate Array (FPGA). The digital hardware logic has been implemented with reversible and fault tolerant capabilities at significant design sections substituting the adder and multiplier functions which is one of the first of its kind of implementation of this application needed for designing energy efficient systems such as SoC (System on Chip) based robotic vision system. Reversible logic is emerging as an important research area for low power CMOS design, DSP applications and battery operated embedded systems meant for image processing. The reversible logic is implemented using our new proposed RFT (Reversible Fault Tolerant) gates (which is reversible as well as fault tolerant) that is used to design a new innovated adder circuit. The new adder circuit uses very less hardware resource which is again substituted with minimum complexity reversible gate. The proposed design shows invariancy to various image parameters such as scale, rotation, viewpoint and noise unlike other state of the art works. Moreover our design can process a frame of resolution 640*480 in 15 millisecond, at a rate of 64 frames per second which meets the real time video rate constraint, what represents a speed up of 415x compared to the software execution of the method.
{"title":"An efficient hardware design of SIFT algorithm using fault tolerant reversible logic","authors":"Chandrajit Pal, Pabitra Das, S. B. Mandal, A. Chakrabarti, Samik Basu, R. Ghosh","doi":"10.1109/ReTIS.2015.7232933","DOIUrl":"https://doi.org/10.1109/ReTIS.2015.7232933","url":null,"abstract":"Scale Invariant Feature Transform (SIFT) algorithm is used to generate image features which is very essential for object recognition, feature detection, image matching etc. This paper proposes an optimized hardware architecture for realizing the SIFT algorithm with reversible logic prototyped using Field Programmable Gate Array (FPGA). The digital hardware logic has been implemented with reversible and fault tolerant capabilities at significant design sections substituting the adder and multiplier functions which is one of the first of its kind of implementation of this application needed for designing energy efficient systems such as SoC (System on Chip) based robotic vision system. Reversible logic is emerging as an important research area for low power CMOS design, DSP applications and battery operated embedded systems meant for image processing. The reversible logic is implemented using our new proposed RFT (Reversible Fault Tolerant) gates (which is reversible as well as fault tolerant) that is used to design a new innovated adder circuit. The new adder circuit uses very less hardware resource which is again substituted with minimum complexity reversible gate. The proposed design shows invariancy to various image parameters such as scale, rotation, viewpoint and noise unlike other state of the art works. Moreover our design can process a frame of resolution 640*480 in 15 millisecond, at a rate of 64 frames per second which meets the real time video rate constraint, what represents a speed up of 415x compared to the software execution of the method.","PeriodicalId":161306,"journal":{"name":"2015 IEEE 2nd International Conference on Recent Trends in Information Systems (ReTIS)","volume":"183 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129636939","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-07-09DOI: 10.1109/ReTIS.2015.7232870
H. Singh, T. Bezboruah
An interactive .NET web application is designed for use in remote monitoring of sensor response within a Local Area Network zone. Key performance metrics of the web application such as response times, throughput, processor and disk utilization are measured by employing a standard testing tool. The impact of concurrent users' activities on the performance metrics of the web application have been observed by using two test scenarios.
{"title":"Performance metrics of a customized web application developed for monitoring sensor data","authors":"H. Singh, T. Bezboruah","doi":"10.1109/ReTIS.2015.7232870","DOIUrl":"https://doi.org/10.1109/ReTIS.2015.7232870","url":null,"abstract":"An interactive .NET web application is designed for use in remote monitoring of sensor response within a Local Area Network zone. Key performance metrics of the web application such as response times, throughput, processor and disk utilization are measured by employing a standard testing tool. The impact of concurrent users' activities on the performance metrics of the web application have been observed by using two test scenarios.","PeriodicalId":161306,"journal":{"name":"2015 IEEE 2nd International Conference on Recent Trends in Information Systems (ReTIS)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131010322","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-07-09DOI: 10.1109/ReTIS.2015.7232847
Saprativa Bhattacharjee, Anirban Das, U. Bhattacharya, S. K. Parui, S. Roy
The opinion of other people is often a major factor influencing our decisions. For a consumer it affects purchase decisions and for a producer or a service provider it helps in making business decisions. Companies spend a lot of money and time on surveys for gathering the public opinion on products and services. Now-a-days the web has become a hotspot for finding user opinions on almost anything under the sun. Both money and time can be saved by mining opinions from the web. Moreover, no survey can have a sample size, which can match that of the web. Each opinion generally expresses either positive, negative or neutral sentiment. The task of identifying these sentiments is called Sentiment Analysis. This work deals with the analysis of user sentiments in the Telecom domain. Since no such related standard database of users' opinions could be found, we developed one by mining the WWW. A major issue with these sample comments is that these are usually extremely noisy, containing numerous spelling and grammatical errors, acronyms, abbreviations, shortened or slang words etc. Such data cannot be used directly for analyzing sentiments. Hence, a lexicon based preprocessing algorithm is proposed for noise reduction. A novel idea based on Cosine Similarity measure is proposed for classifying the sentiment expressed by a user's comment into a five point scale of -2 (highly negative) to +2 (highly positive). The performance of the proposed strategy is compared with some of the well-known machine learning algorithms namely, Naive Bayes, Maximum Entropy and SVM. The proposed Cosine Similarity based classifier gives 82.09% accuracy for the 2-class problem of identifying positive and negative sentiments. It outperforms all other classifiers by a considerable margin in the 5-class sentiment classification problem with an accuracy of 71.5%. The same strategy is also used for categorizing each user comment into six different Telecom specific categories.
{"title":"Sentiment analysis using cosine similarity measure","authors":"Saprativa Bhattacharjee, Anirban Das, U. Bhattacharya, S. K. Parui, S. Roy","doi":"10.1109/ReTIS.2015.7232847","DOIUrl":"https://doi.org/10.1109/ReTIS.2015.7232847","url":null,"abstract":"The opinion of other people is often a major factor influencing our decisions. For a consumer it affects purchase decisions and for a producer or a service provider it helps in making business decisions. Companies spend a lot of money and time on surveys for gathering the public opinion on products and services. Now-a-days the web has become a hotspot for finding user opinions on almost anything under the sun. Both money and time can be saved by mining opinions from the web. Moreover, no survey can have a sample size, which can match that of the web. Each opinion generally expresses either positive, negative or neutral sentiment. The task of identifying these sentiments is called Sentiment Analysis. This work deals with the analysis of user sentiments in the Telecom domain. Since no such related standard database of users' opinions could be found, we developed one by mining the WWW. A major issue with these sample comments is that these are usually extremely noisy, containing numerous spelling and grammatical errors, acronyms, abbreviations, shortened or slang words etc. Such data cannot be used directly for analyzing sentiments. Hence, a lexicon based preprocessing algorithm is proposed for noise reduction. A novel idea based on Cosine Similarity measure is proposed for classifying the sentiment expressed by a user's comment into a five point scale of -2 (highly negative) to +2 (highly positive). The performance of the proposed strategy is compared with some of the well-known machine learning algorithms namely, Naive Bayes, Maximum Entropy and SVM. The proposed Cosine Similarity based classifier gives 82.09% accuracy for the 2-class problem of identifying positive and negative sentiments. It outperforms all other classifiers by a considerable margin in the 5-class sentiment classification problem with an accuracy of 71.5%. The same strategy is also used for categorizing each user comment into six different Telecom specific categories.","PeriodicalId":161306,"journal":{"name":"2015 IEEE 2nd International Conference on Recent Trends in Information Systems (ReTIS)","volume":"83 22","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113944171","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-07-09DOI: 10.1109/ReTIS.2015.7232932
Bhabani Sankar Choudhury, S. Maity
This work is dedicated to a Phase Locked Loop design that works with a sub 1GHz frequency band. Medical Implant Communication Service operates at 402-405 MHz frequency of operation. The PLL design used in this paper uses a novel two stage ring VCO that can generate 179MHz to 438MHz by changing the control voltage from 0.3-V to 1-V. The worst case phase noise of -106dBc/Hz is obtained at an offset of 1MHz. The VCO is controlled by changing the resistance in the forward path by varying the gate voltage of the transmission gate. Thus the design challenge to achieve oscillation at two stages is achieved. For small frequency to have small size device is not possible in conventional design has been achieved in this design. The lock in time of the PLL is 8μS with a charge pump current of 100μA. The PLL architecture consumes 280μW of power from a supply voltage of 1-V. The loop filter and its stability analysis have been verified by MATLAB. The Simulink model has been developed in order to verify the theoretical operation of the PLL. The Transistor level analysis has been done using Cadence virtuoso 90nm CMOS technology.
{"title":"A 405MHz integer-N CMOS PLL for implantable biomedical application","authors":"Bhabani Sankar Choudhury, S. Maity","doi":"10.1109/ReTIS.2015.7232932","DOIUrl":"https://doi.org/10.1109/ReTIS.2015.7232932","url":null,"abstract":"This work is dedicated to a Phase Locked Loop design that works with a sub 1GHz frequency band. Medical Implant Communication Service operates at 402-405 MHz frequency of operation. The PLL design used in this paper uses a novel two stage ring VCO that can generate 179MHz to 438MHz by changing the control voltage from 0.3-V to 1-V. The worst case phase noise of -106dBc/Hz is obtained at an offset of 1MHz. The VCO is controlled by changing the resistance in the forward path by varying the gate voltage of the transmission gate. Thus the design challenge to achieve oscillation at two stages is achieved. For small frequency to have small size device is not possible in conventional design has been achieved in this design. The lock in time of the PLL is 8μS with a charge pump current of 100μA. The PLL architecture consumes 280μW of power from a supply voltage of 1-V. The loop filter and its stability analysis have been verified by MATLAB. The Simulink model has been developed in order to verify the theoretical operation of the PLL. The Transistor level analysis has been done using Cadence virtuoso 90nm CMOS technology.","PeriodicalId":161306,"journal":{"name":"2015 IEEE 2nd International Conference on Recent Trends in Information Systems (ReTIS)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128402975","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-07-09DOI: 10.1109/ReTIS.2015.7232868
Debapriyay Mukhopadhyay, S. Nandy
This work makes two major contributions to architectural support for the debugging of memory related bugs. First, it proposes a novel framework for detecting memory related bugs, where the application can be selective, can be extended to kernel modules, and is based on the virtual memory simulation of the application in hand. Secondly, we have tried to formalize the code instrumentation given our framework. It has not been dealt in details in the earlier works. This will generate scopes for future research in this area and a better formalism can help to come up with a much more usable and robust tool for detecting memory related bugs.
{"title":"YAHMD — Yet another heap memory debugger","authors":"Debapriyay Mukhopadhyay, S. Nandy","doi":"10.1109/ReTIS.2015.7232868","DOIUrl":"https://doi.org/10.1109/ReTIS.2015.7232868","url":null,"abstract":"This work makes two major contributions to architectural support for the debugging of memory related bugs. First, it proposes a novel framework for detecting memory related bugs, where the application can be selective, can be extended to kernel modules, and is based on the virtual memory simulation of the application in hand. Secondly, we have tried to formalize the code instrumentation given our framework. It has not been dealt in details in the earlier works. This will generate scopes for future research in this area and a better formalism can help to come up with a much more usable and robust tool for detecting memory related bugs.","PeriodicalId":161306,"journal":{"name":"2015 IEEE 2nd International Conference on Recent Trends in Information Systems (ReTIS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134031815","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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