Pub Date : 1995-08-13DOI: 10.1109/MWSCAS.1995.510281
Ryan Pinto, H.L.C.P. Pinto, L. Calôba
This paper describes an automatic speaker recognition method for telephone speech, using acoustic processing of a single trisyllabic Portuguese word. Cepstrum coefficients are extracted from the linear predictive coefficients and no further processing is needed. In this method, the traditional classification method (non-Euclidean distance measurement) was efficiently substituted by a multi-layer neural network with encouraging results.
{"title":"Using neural networks for automatic speaker recognition: a practical approach","authors":"Ryan Pinto, H.L.C.P. Pinto, L. Calôba","doi":"10.1109/MWSCAS.1995.510281","DOIUrl":"https://doi.org/10.1109/MWSCAS.1995.510281","url":null,"abstract":"This paper describes an automatic speaker recognition method for telephone speech, using acoustic processing of a single trisyllabic Portuguese word. Cepstrum coefficients are extracted from the linear predictive coefficients and no further processing is needed. In this method, the traditional classification method (non-Euclidean distance measurement) was efficiently substituted by a multi-layer neural network with encouraging results.","PeriodicalId":165081,"journal":{"name":"38th Midwest Symposium on Circuits and Systems. Proceedings","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114202425","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-13DOI: 10.1109/MWSCAS.1995.504378
R. Bouchakour, L. Hardy, J. Naviner, I. Limbourg, M. Jourdain, M. Jelloul
This paper presents the modeling and characterization of degradation effects by hot-carrier injection on the electrical behavior of the nMOS transistor. The one-dimensional analytical model developed is based on the sharing out of the channel in cells and is able to take into account a distribution of defects along the channel.
{"title":"Modeling and characterization of the nMOS transistor stressed by hot-carrier injection","authors":"R. Bouchakour, L. Hardy, J. Naviner, I. Limbourg, M. Jourdain, M. Jelloul","doi":"10.1109/MWSCAS.1995.504378","DOIUrl":"https://doi.org/10.1109/MWSCAS.1995.504378","url":null,"abstract":"This paper presents the modeling and characterization of degradation effects by hot-carrier injection on the electrical behavior of the nMOS transistor. The one-dimensional analytical model developed is based on the sharing out of the channel in cells and is able to take into account a distribution of defects along the channel.","PeriodicalId":165081,"journal":{"name":"38th Midwest Symposium on Circuits and Systems. Proceedings","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122826769","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-13DOI: 10.1109/MWSCAS.1995.504488
H. Abdel-Aty-Zohdy, F. El-licy
A Sixteen Input Maximum/Minimum Analog signal-selector Circuit (SIMMAC) is designed, simulated, and implemented using 2 /spl mu/m p-well (Orbit) CMOS technology. The circuit is useful in recognition of gas types from measurements of thin-film gas-sensor arrays. The output signal of each thin-film gas detector is typically a function of bias voltages, temperature and pressure, film type, frequency, and gas type. Gas sensor arrays provide profiles of resistivity vs. temperature, for a particular PPM, and/or profiles of resistivity vs. pressure at a particular temperature. Since different chemical gas types have peak resistivity values at a certain temperature and a certain pressure, a selector circuit is needed to identify chemical gas components. The SIMMAC design is based on a multiple-input current comparator median circuit. Simulation results gave an accuracy of better than 94% with analog input signal values from 1.6 to 3.6 V. The SIMMAC is suitable for gas detection from a sensor-array of up to 16-elements with known models and negligible signal distortion. Further, it may be used as a post processor to select the winning synapse in an unsupervised neural network for pattern recognition with distorted and unidentified models of gas mixtures.
{"title":"Analog signal-selector circuit for quick gas detection from gas-sensor arrays","authors":"H. Abdel-Aty-Zohdy, F. El-licy","doi":"10.1109/MWSCAS.1995.504488","DOIUrl":"https://doi.org/10.1109/MWSCAS.1995.504488","url":null,"abstract":"A Sixteen Input Maximum/Minimum Analog signal-selector Circuit (SIMMAC) is designed, simulated, and implemented using 2 /spl mu/m p-well (Orbit) CMOS technology. The circuit is useful in recognition of gas types from measurements of thin-film gas-sensor arrays. The output signal of each thin-film gas detector is typically a function of bias voltages, temperature and pressure, film type, frequency, and gas type. Gas sensor arrays provide profiles of resistivity vs. temperature, for a particular PPM, and/or profiles of resistivity vs. pressure at a particular temperature. Since different chemical gas types have peak resistivity values at a certain temperature and a certain pressure, a selector circuit is needed to identify chemical gas components. The SIMMAC design is based on a multiple-input current comparator median circuit. Simulation results gave an accuracy of better than 94% with analog input signal values from 1.6 to 3.6 V. The SIMMAC is suitable for gas detection from a sensor-array of up to 16-elements with known models and negligible signal distortion. Further, it may be used as a post processor to select the winning synapse in an unsupervised neural network for pattern recognition with distorted and unidentified models of gas mixtures.","PeriodicalId":165081,"journal":{"name":"38th Midwest Symposium on Circuits and Systems. Proceedings","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121744259","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-13DOI: 10.1109/MWSCAS.1995.510254
T. Serrano-Gotarredona, B. Linares-Barranco, J. Huertas
Summary form only given, as follows. We describe an analog VLSI implementation of the ART1 algorithm (Carpenter, 1987). A prototype chip has been fabricated in a standard low cost 1.5 /spl mu/m double-mental single-poly CMOS process. It has a die area of 1 cm/sup 2/ and is mounted in a 120 pin PGA package. The chip realizes a modified version of the original ART1 architecture. Such modification has been shown to preserve all computational properties of the original algorithm (Serrano, 1994), while being more appropriate for VLSI realizations. The chip implements on ART1 network with 100 F1 nodes and 18 F2 nodes. It can, therefore, cluster 100 binary pixels input patterns into up to 18 different categories. Modular expansibility of the system is possible by assembling an N/spl times/M array of chips without any extra interfacing circuitry, resulting in an F1 layer with 100/spl times/N nodes, and an F2 layer with 18/spl times/M nodes. Pattern classification is performed in less than 1.8 /spl mu/s, which means an equivalent computing power of 2.2/spl times/10/sup 9/ connections and connection-updates per second. Although internally the chip is analog in nature, it interfaces to the outside world through digital signals, thus having a true asynchronous digital behavior. Experimental chip test results are available, which have been obtained through test equipment for digital chips.
{"title":"A real time clustering CMOS neural engine","authors":"T. Serrano-Gotarredona, B. Linares-Barranco, J. Huertas","doi":"10.1109/MWSCAS.1995.510254","DOIUrl":"https://doi.org/10.1109/MWSCAS.1995.510254","url":null,"abstract":"Summary form only given, as follows. We describe an analog VLSI implementation of the ART1 algorithm (Carpenter, 1987). A prototype chip has been fabricated in a standard low cost 1.5 /spl mu/m double-mental single-poly CMOS process. It has a die area of 1 cm/sup 2/ and is mounted in a 120 pin PGA package. The chip realizes a modified version of the original ART1 architecture. Such modification has been shown to preserve all computational properties of the original algorithm (Serrano, 1994), while being more appropriate for VLSI realizations. The chip implements on ART1 network with 100 F1 nodes and 18 F2 nodes. It can, therefore, cluster 100 binary pixels input patterns into up to 18 different categories. Modular expansibility of the system is possible by assembling an N/spl times/M array of chips without any extra interfacing circuitry, resulting in an F1 layer with 100/spl times/N nodes, and an F2 layer with 18/spl times/M nodes. Pattern classification is performed in less than 1.8 /spl mu/s, which means an equivalent computing power of 2.2/spl times/10/sup 9/ connections and connection-updates per second. Although internally the chip is analog in nature, it interfaces to the outside world through digital signals, thus having a true asynchronous digital behavior. Experimental chip test results are available, which have been obtained through test equipment for digital chips.","PeriodicalId":165081,"journal":{"name":"38th Midwest Symposium on Circuits and Systems. Proceedings","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122065535","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-13DOI: 10.1109/MWSCAS.1995.504390
J.E. de Araujo Filho, K. Kienitz
A method to design stabilizing controllers for a class of discrete time varying systems with bounded time variance is presented in this contribution. It uses the guaranteed cost concept to assess the system's performance and the direct method of Lyapunov for stability considerations. Thus it resorts to techniques already known for uncertain systems. The controller determined using this method is given in terms of the solution to one of two modified Riccati equations.
{"title":"Guaranteed cost stabilization of a class of discrete time varying systems","authors":"J.E. de Araujo Filho, K. Kienitz","doi":"10.1109/MWSCAS.1995.504390","DOIUrl":"https://doi.org/10.1109/MWSCAS.1995.504390","url":null,"abstract":"A method to design stabilizing controllers for a class of discrete time varying systems with bounded time variance is presented in this contribution. It uses the guaranteed cost concept to assess the system's performance and the direct method of Lyapunov for stability considerations. Thus it resorts to techniques already known for uncertain systems. The controller determined using this method is given in terms of the solution to one of two modified Riccati equations.","PeriodicalId":165081,"journal":{"name":"38th Midwest Symposium on Circuits and Systems. Proceedings","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121075928","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-13DOI: 10.1109/MWSCAS.1995.504382
S.T. Lee, K.T. Lau
Using a normalized Gaussian function for feedforward neural networks with a single hidden layer has been proven to have the capability of universal approximation in a satisfactory sense. Back-propagation neural networks with Gaussian function synapses have better convergence over those with linear multiplying synapses. A compact analog Gaussian synapse is presented in this paper. The standard deviation and the magnitude of the proposed Gaussian synapse can be programmed externally.
{"title":"An analog Gaussian synapse for artificial neural networks","authors":"S.T. Lee, K.T. Lau","doi":"10.1109/MWSCAS.1995.504382","DOIUrl":"https://doi.org/10.1109/MWSCAS.1995.504382","url":null,"abstract":"Using a normalized Gaussian function for feedforward neural networks with a single hidden layer has been proven to have the capability of universal approximation in a satisfactory sense. Back-propagation neural networks with Gaussian function synapses have better convergence over those with linear multiplying synapses. A compact analog Gaussian synapse is presented in this paper. The standard deviation and the magnitude of the proposed Gaussian synapse can be programmed externally.","PeriodicalId":165081,"journal":{"name":"38th Midwest Symposium on Circuits and Systems. Proceedings","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125799689","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-13DOI: 10.1109/MWSCAS.1995.504466
J. M. Galvez, L.P. de Araujo
A major difficulty in the design of controllers for multivariable linear systems is the cross-coupling between inputs and outputs which obscures the effects of a specific loop controller on the system behavior. In the case of thermodynamic processes, the control problem is still more complex due to the time delay involved in the process itself. This paper considers the application of frequency domain techniques to the design of multivariable feedback controllers for a nonlinear, six-heating-zones electrical oven system. Multivariable frequency domain techniques are used to analyze the system, to improve the system decoupling and to validate a single-input single-output (SISO) linear design approach. Classical SISO techniques are applied to design a controller. Feasible temperatures profiles and their effects on the controller design are discussed. Simulation results are presented. Finally, a general procedure for control design is suggested.
{"title":"Multivariable control design in the frequency domain for an industrial electrical tubular oven","authors":"J. M. Galvez, L.P. de Araujo","doi":"10.1109/MWSCAS.1995.504466","DOIUrl":"https://doi.org/10.1109/MWSCAS.1995.504466","url":null,"abstract":"A major difficulty in the design of controllers for multivariable linear systems is the cross-coupling between inputs and outputs which obscures the effects of a specific loop controller on the system behavior. In the case of thermodynamic processes, the control problem is still more complex due to the time delay involved in the process itself. This paper considers the application of frequency domain techniques to the design of multivariable feedback controllers for a nonlinear, six-heating-zones electrical oven system. Multivariable frequency domain techniques are used to analyze the system, to improve the system decoupling and to validate a single-input single-output (SISO) linear design approach. Classical SISO techniques are applied to design a controller. Feasible temperatures profiles and their effects on the controller design are discussed. Simulation results are presented. Finally, a general procedure for control design is suggested.","PeriodicalId":165081,"journal":{"name":"38th Midwest Symposium on Circuits and Systems. Proceedings","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126349315","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-13DOI: 10.1109/MWSCAS.1995.504429
S. L. Netto, M. de Campos, A. Antoniou, P. Agathoklis
A stable parameterization of the direct-form structure with simple stability monitoring is introduced for adaptive IIR filtering. The proposed structure is obtained directly from passive RLC realizations. The stability of the resulting adaptive IIR filter is guaranteed by ensuring positive values for the equivalent passive RLC elements. Special attention is given to doubly terminated RLC networks to achieve optimal sensitivity properties of the overall transfer function with respect to parameter variations. Examples are included to demonstrate the application of the proposed technique.
{"title":"A stable RLC parameterization of the direct structure for adaptive IIR filters","authors":"S. L. Netto, M. de Campos, A. Antoniou, P. Agathoklis","doi":"10.1109/MWSCAS.1995.504429","DOIUrl":"https://doi.org/10.1109/MWSCAS.1995.504429","url":null,"abstract":"A stable parameterization of the direct-form structure with simple stability monitoring is introduced for adaptive IIR filtering. The proposed structure is obtained directly from passive RLC realizations. The stability of the resulting adaptive IIR filter is guaranteed by ensuring positive values for the equivalent passive RLC elements. Special attention is given to doubly terminated RLC networks to achieve optimal sensitivity properties of the overall transfer function with respect to parameter variations. Examples are included to demonstrate the application of the proposed technique.","PeriodicalId":165081,"journal":{"name":"38th Midwest Symposium on Circuits and Systems. Proceedings","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131358568","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-13DOI: 10.1109/MWSCAS.1995.510306
J.M.F.D. Costa, M.M. Silva
Small-signal models of quasi-square-wave (QSW) converters are obtained by using state-space averaging. These models are used to perform a comparative study which shows that current-mode control of QSW converters does not provide the improved dynamic performance with respect to voltage-mode control that can be found in the case of PWM and quasi-resonant converters.
{"title":"Small-signal models and dynamic performance of quasi-square-wave ZVS converters with voltage-mode and current-mode control","authors":"J.M.F.D. Costa, M.M. Silva","doi":"10.1109/MWSCAS.1995.510306","DOIUrl":"https://doi.org/10.1109/MWSCAS.1995.510306","url":null,"abstract":"Small-signal models of quasi-square-wave (QSW) converters are obtained by using state-space averaging. These models are used to perform a comparative study which shows that current-mode control of QSW converters does not provide the improved dynamic performance with respect to voltage-mode control that can be found in the case of PWM and quasi-resonant converters.","PeriodicalId":165081,"journal":{"name":"38th Midwest Symposium on Circuits and Systems. Proceedings","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133446669","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-13DOI: 10.1109/MWSCAS.1995.510204
N. Maheshwari, S. Sapatnekar
A transistor sizing algorithm for row-based layouts is presented under an improved area model. This algorithm uses convex programming to find a minimal area circuit for a given delay specification. The new area model uses a concept of row heights as opposed to the conventional metric of sum of gate sizes. Results over a number of circuits indicate a significant reduction both in the minimum delay achievable and area as compared to TILOS-like optimizer.
{"title":"Gate size optimization for row-based layouts","authors":"N. Maheshwari, S. Sapatnekar","doi":"10.1109/MWSCAS.1995.510204","DOIUrl":"https://doi.org/10.1109/MWSCAS.1995.510204","url":null,"abstract":"A transistor sizing algorithm for row-based layouts is presented under an improved area model. This algorithm uses convex programming to find a minimal area circuit for a given delay specification. The new area model uses a concept of row heights as opposed to the conventional metric of sum of gate sizes. Results over a number of circuits indicate a significant reduction both in the minimum delay achievable and area as compared to TILOS-like optimizer.","PeriodicalId":165081,"journal":{"name":"38th Midwest Symposium on Circuits and Systems. Proceedings","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122373385","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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