Pub Date : 1995-08-13DOI: 10.1109/MWSCAS.1995.504446
C. Soto, R. Saleh, T. Kwasniewski
A time warping algorithm is included in the waveform relaxation circuit simulation in a distributed environment in a multicomputer network. The algorithm feature, is that it can exploit parallelism in the spatial, iteration and temporal domains. The algorithm is characterized by a relative insensitivity to the interprocessor communication overhead. The simulator is ported on a network of Sun Sparc-2 workstations using a 10 Mbits/sec. communication link. Speedups results obtained are comparable for a shared memory architecture.
{"title":"Time warping-waveform relaxation in a distributed circuit simulation environment","authors":"C. Soto, R. Saleh, T. Kwasniewski","doi":"10.1109/MWSCAS.1995.504446","DOIUrl":"https://doi.org/10.1109/MWSCAS.1995.504446","url":null,"abstract":"A time warping algorithm is included in the waveform relaxation circuit simulation in a distributed environment in a multicomputer network. The algorithm feature, is that it can exploit parallelism in the spatial, iteration and temporal domains. The algorithm is characterized by a relative insensitivity to the interprocessor communication overhead. The simulator is ported on a network of Sun Sparc-2 workstations using a 10 Mbits/sec. communication link. Speedups results obtained are comparable for a shared memory architecture.","PeriodicalId":165081,"journal":{"name":"38th Midwest Symposium on Circuits and Systems. Proceedings","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121696982","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-13DOI: 10.1109/MWSCAS.1995.510297
A. Richardson, T. Olbrich, V. Liberali, F. Maloberti
Recent advances in technology are leading to increases in the complexity and applications of analogue and mixed-signal integrated circuits. This trend has been accompanied by an increase in the complexity of associated test specifications. Furthermore, the use of functional and specification based test programs for the analogue circuitry is being questioned due to high implementation costs, the difficulties associated with quantifying the effectiveness of the tests and in many cases difficulties in accessing embedded analogue macros. In addition quality levels expected by integrated circuit (IC) users are increasing, with typical targets currently being better than 40 ppm defect levels. New test solutions are therefore required for these circuit types. Design-for-Test (DfT) strategies are well established for digital circuits, whilst for analogue and mixed signal circuits, few techniques have been proposed and implementation of custom approaches is rare. This paper presents a summary of a number of possible approaches for improving test access by increasing both controllability and observability of internal functional blocks in analogue and mixed-signal ICs, evaluating both their effectiveness and their impact on circuit performance.
{"title":"Design-for-test strategies for analogue and mixed-signal integrated circuits","authors":"A. Richardson, T. Olbrich, V. Liberali, F. Maloberti","doi":"10.1109/MWSCAS.1995.510297","DOIUrl":"https://doi.org/10.1109/MWSCAS.1995.510297","url":null,"abstract":"Recent advances in technology are leading to increases in the complexity and applications of analogue and mixed-signal integrated circuits. This trend has been accompanied by an increase in the complexity of associated test specifications. Furthermore, the use of functional and specification based test programs for the analogue circuitry is being questioned due to high implementation costs, the difficulties associated with quantifying the effectiveness of the tests and in many cases difficulties in accessing embedded analogue macros. In addition quality levels expected by integrated circuit (IC) users are increasing, with typical targets currently being better than 40 ppm defect levels. New test solutions are therefore required for these circuit types. Design-for-Test (DfT) strategies are well established for digital circuits, whilst for analogue and mixed signal circuits, few techniques have been proposed and implementation of custom approaches is rare. This paper presents a summary of a number of possible approaches for improving test access by increasing both controllability and observability of internal functional blocks in analogue and mixed-signal ICs, evaluating both their effectiveness and their impact on circuit performance.","PeriodicalId":165081,"journal":{"name":"38th Midwest Symposium on Circuits and Systems. Proceedings","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123750124","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-13DOI: 10.1109/MWSCAS.1995.504504
L. Fernandes, C. Leme, J. Franca
This paper presents a compact realization of cascaded biquad digital filters using 2nd order /spl Delta//spl Sigma/ modulators to avoid the need for multibit multipliers. A bit stream biquad is derived with just one /spl Delta//spl Sigma/ modulator for each pair of poles with no significant degradation of sensitivity nor of dynamic range. The proposed structure leads to a straightforward programmable implementation due to its compactness and modularity.
{"title":"Programmable IIR bitstream filters","authors":"L. Fernandes, C. Leme, J. Franca","doi":"10.1109/MWSCAS.1995.504504","DOIUrl":"https://doi.org/10.1109/MWSCAS.1995.504504","url":null,"abstract":"This paper presents a compact realization of cascaded biquad digital filters using 2nd order /spl Delta//spl Sigma/ modulators to avoid the need for multibit multipliers. A bit stream biquad is derived with just one /spl Delta//spl Sigma/ modulator for each pair of poles with no significant degradation of sensitivity nor of dynamic range. The proposed structure leads to a straightforward programmable implementation due to its compactness and modularity.","PeriodicalId":165081,"journal":{"name":"38th Midwest Symposium on Circuits and Systems. Proceedings","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132779524","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-13DOI: 10.1109/MWSCAS.1995.510283
H. Arango, J. Abreu
This paper deals with the interconnection of systems having different number of phases (heterophasic systems). A matrix theory is developed in order that heterophasic transformations could be devised preserving transmission balance. A three/four-phase transformer exemplifies the theory, showing how the energy flows and electrical symmetry is kept.
{"title":"On the synthesis of heterophasic ideal transformers","authors":"H. Arango, J. Abreu","doi":"10.1109/MWSCAS.1995.510283","DOIUrl":"https://doi.org/10.1109/MWSCAS.1995.510283","url":null,"abstract":"This paper deals with the interconnection of systems having different number of phases (heterophasic systems). A matrix theory is developed in order that heterophasic transformations could be devised preserving transmission balance. A three/four-phase transformer exemplifies the theory, showing how the energy flows and electrical symmetry is kept.","PeriodicalId":165081,"journal":{"name":"38th Midwest Symposium on Circuits and Systems. Proceedings","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133790662","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-13DOI: 10.1109/MWSCAS.1995.504479
C. Gargour, V. Ramachandran
A graphical technique is described, which permits one to obtain the limits of a coefficient of a multiplier in a 2-D stable transfer function having variable magnitude characteristics. It is shown that this method obviates the necessity of evaluating the various determinants and inequalities required for the same purpose, if the method of inners is employed. A computer program is developed to plot such graphs.
{"title":"A graphical technique for the determination of the range of a multiplier in a stable 2-D variable magnitude filter","authors":"C. Gargour, V. Ramachandran","doi":"10.1109/MWSCAS.1995.504479","DOIUrl":"https://doi.org/10.1109/MWSCAS.1995.504479","url":null,"abstract":"A graphical technique is described, which permits one to obtain the limits of a coefficient of a multiplier in a 2-D stable transfer function having variable magnitude characteristics. It is shown that this method obviates the necessity of evaluating the various determinants and inequalities required for the same purpose, if the method of inners is employed. A computer program is developed to plot such graphs.","PeriodicalId":165081,"journal":{"name":"38th Midwest Symposium on Circuits and Systems. Proceedings","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130387634","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-13DOI: 10.1109/MWSCAS.1995.510321
J. Matos, A. Gameiro, J. Perez
In the communication we consider the use of signal injection to improve the acquisition and tracking performance of PLLs (PLLI). A dynamic model describing the PLLI behaviour is derived. Based on this model we show that by a proper design the injected signal can be used to improve the acquisition capabilities of conventional PLLs without changing the loop response. Experimental measurements of a PLLI, with a Colpitts VCO designed to allow current injection, are presented which show that this type of loop has wider locking range and a reduced acquisition time relatively to the conventional PLL. With this experimental set-up we also confirm that with low signal injection power the loop response remains identical if injection is made in quadrature.
{"title":"Improved acquisition and tracking performance of PLLs through signal injection","authors":"J. Matos, A. Gameiro, J. Perez","doi":"10.1109/MWSCAS.1995.510321","DOIUrl":"https://doi.org/10.1109/MWSCAS.1995.510321","url":null,"abstract":"In the communication we consider the use of signal injection to improve the acquisition and tracking performance of PLLs (PLLI). A dynamic model describing the PLLI behaviour is derived. Based on this model we show that by a proper design the injected signal can be used to improve the acquisition capabilities of conventional PLLs without changing the loop response. Experimental measurements of a PLLI, with a Colpitts VCO designed to allow current injection, are presented which show that this type of loop has wider locking range and a reduced acquisition time relatively to the conventional PLL. With this experimental set-up we also confirm that with low signal injection power the loop response remains identical if injection is made in quadrature.","PeriodicalId":165081,"journal":{"name":"38th Midwest Symposium on Circuits and Systems. Proceedings","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115543956","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-13DOI: 10.1109/MWSCAS.1995.510182
T.P. Borsodi, B. Nowrouzian
This paper undertakes an investigation of the closed-form solution of the quantization error for the conventional multi-loop sigma-delta (/spl Sigma/-/spl Delta/) modulator configurations. The underlying assumption in this investigation is that the constituent coarse quantizer operates in its no-overload region. The required overload-free quantizer operation is achieved by placing an appropriate bound on the /spl Sigma/-/spl Delta/ modulator input signal. The main results are illustrated through their application to the determination of the quantization error for a number of multi-loop /spl Sigma/-/spl Delta/ modulator configurations for both DC as well as AC input signals.
{"title":"Closed form solution of granular quantization error for multi-loop sigma-delta modulator configurations","authors":"T.P. Borsodi, B. Nowrouzian","doi":"10.1109/MWSCAS.1995.510182","DOIUrl":"https://doi.org/10.1109/MWSCAS.1995.510182","url":null,"abstract":"This paper undertakes an investigation of the closed-form solution of the quantization error for the conventional multi-loop sigma-delta (/spl Sigma/-/spl Delta/) modulator configurations. The underlying assumption in this investigation is that the constituent coarse quantizer operates in its no-overload region. The required overload-free quantizer operation is achieved by placing an appropriate bound on the /spl Sigma/-/spl Delta/ modulator input signal. The main results are illustrated through their application to the determination of the quantization error for a number of multi-loop /spl Sigma/-/spl Delta/ modulator configurations for both DC as well as AC input signals.","PeriodicalId":165081,"journal":{"name":"38th Midwest Symposium on Circuits and Systems. Proceedings","volume":"885 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114683282","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-13DOI: 10.1109/MWSCAS.1995.510281
Ryan Pinto, H.L.C.P. Pinto, L. Calôba
This paper describes an automatic speaker recognition method for telephone speech, using acoustic processing of a single trisyllabic Portuguese word. Cepstrum coefficients are extracted from the linear predictive coefficients and no further processing is needed. In this method, the traditional classification method (non-Euclidean distance measurement) was efficiently substituted by a multi-layer neural network with encouraging results.
{"title":"Using neural networks for automatic speaker recognition: a practical approach","authors":"Ryan Pinto, H.L.C.P. Pinto, L. Calôba","doi":"10.1109/MWSCAS.1995.510281","DOIUrl":"https://doi.org/10.1109/MWSCAS.1995.510281","url":null,"abstract":"This paper describes an automatic speaker recognition method for telephone speech, using acoustic processing of a single trisyllabic Portuguese word. Cepstrum coefficients are extracted from the linear predictive coefficients and no further processing is needed. In this method, the traditional classification method (non-Euclidean distance measurement) was efficiently substituted by a multi-layer neural network with encouraging results.","PeriodicalId":165081,"journal":{"name":"38th Midwest Symposium on Circuits and Systems. Proceedings","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114202425","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-13DOI: 10.1109/MWSCAS.1995.510255
Dong-Wook Kim, Han-Bit Kang, M. Eun, Jongsoo Choi
Variable step size LMS (VS-LMS) algorithms improve performance of LMS algorithm by means of varying the step size. This paper presents a new VS-LMS algorithm using normalized absolute estimation error. The performance of the proposed algorithm is analyzed theoretically and estimated through simulations. Based on the theoretical analysis and computer simulations, the proposed algorithm is shown to be effective compared to conventional VS-LMS algorithms.
{"title":"A variable step size algorithm using normalized absolute estimation error","authors":"Dong-Wook Kim, Han-Bit Kang, M. Eun, Jongsoo Choi","doi":"10.1109/MWSCAS.1995.510255","DOIUrl":"https://doi.org/10.1109/MWSCAS.1995.510255","url":null,"abstract":"Variable step size LMS (VS-LMS) algorithms improve performance of LMS algorithm by means of varying the step size. This paper presents a new VS-LMS algorithm using normalized absolute estimation error. The performance of the proposed algorithm is analyzed theoretically and estimated through simulations. Based on the theoretical analysis and computer simulations, the proposed algorithm is shown to be effective compared to conventional VS-LMS algorithms.","PeriodicalId":165081,"journal":{"name":"38th Midwest Symposium on Circuits and Systems. Proceedings","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117199021","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-13DOI: 10.1109/MWSCAS.1995.510170
J. M. Galvez
This paper presents a dynamic model reduction (DMR) technique based on the concept of pole dominance applied to direct model reference adaptive control (DMRAC). The stability analysis is performed through Lyapunov's theory and does not require the plant to be strictly positive real (SPR). It is shown how asymptotic stability can be obtained through the implementation of the DMR scheme together with residual mode filters (RMF). Simulation results are carry out to illustrate the regulation and tracking outstanding performances of the proposed scheme.
{"title":"A pole dominance approach for adaptive control and dynamic model reduction of large scale systems","authors":"J. M. Galvez","doi":"10.1109/MWSCAS.1995.510170","DOIUrl":"https://doi.org/10.1109/MWSCAS.1995.510170","url":null,"abstract":"This paper presents a dynamic model reduction (DMR) technique based on the concept of pole dominance applied to direct model reference adaptive control (DMRAC). The stability analysis is performed through Lyapunov's theory and does not require the plant to be strictly positive real (SPR). It is shown how asymptotic stability can be obtained through the implementation of the DMR scheme together with residual mode filters (RMF). Simulation results are carry out to illustrate the regulation and tracking outstanding performances of the proposed scheme.","PeriodicalId":165081,"journal":{"name":"38th Midwest Symposium on Circuits and Systems. Proceedings","volume":"109 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115890193","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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