Pub Date : 1995-08-13DOI: 10.1109/MWSCAS.1995.504446
C. Soto, R. Saleh, T. Kwasniewski
A time warping algorithm is included in the waveform relaxation circuit simulation in a distributed environment in a multicomputer network. The algorithm feature, is that it can exploit parallelism in the spatial, iteration and temporal domains. The algorithm is characterized by a relative insensitivity to the interprocessor communication overhead. The simulator is ported on a network of Sun Sparc-2 workstations using a 10 Mbits/sec. communication link. Speedups results obtained are comparable for a shared memory architecture.
{"title":"Time warping-waveform relaxation in a distributed circuit simulation environment","authors":"C. Soto, R. Saleh, T. Kwasniewski","doi":"10.1109/MWSCAS.1995.504446","DOIUrl":"https://doi.org/10.1109/MWSCAS.1995.504446","url":null,"abstract":"A time warping algorithm is included in the waveform relaxation circuit simulation in a distributed environment in a multicomputer network. The algorithm feature, is that it can exploit parallelism in the spatial, iteration and temporal domains. The algorithm is characterized by a relative insensitivity to the interprocessor communication overhead. The simulator is ported on a network of Sun Sparc-2 workstations using a 10 Mbits/sec. communication link. Speedups results obtained are comparable for a shared memory architecture.","PeriodicalId":165081,"journal":{"name":"38th Midwest Symposium on Circuits and Systems. Proceedings","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121696982","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-13DOI: 10.1109/MWSCAS.1995.510297
A. Richardson, T. Olbrich, V. Liberali, F. Maloberti
Recent advances in technology are leading to increases in the complexity and applications of analogue and mixed-signal integrated circuits. This trend has been accompanied by an increase in the complexity of associated test specifications. Furthermore, the use of functional and specification based test programs for the analogue circuitry is being questioned due to high implementation costs, the difficulties associated with quantifying the effectiveness of the tests and in many cases difficulties in accessing embedded analogue macros. In addition quality levels expected by integrated circuit (IC) users are increasing, with typical targets currently being better than 40 ppm defect levels. New test solutions are therefore required for these circuit types. Design-for-Test (DfT) strategies are well established for digital circuits, whilst for analogue and mixed signal circuits, few techniques have been proposed and implementation of custom approaches is rare. This paper presents a summary of a number of possible approaches for improving test access by increasing both controllability and observability of internal functional blocks in analogue and mixed-signal ICs, evaluating both their effectiveness and their impact on circuit performance.
{"title":"Design-for-test strategies for analogue and mixed-signal integrated circuits","authors":"A. Richardson, T. Olbrich, V. Liberali, F. Maloberti","doi":"10.1109/MWSCAS.1995.510297","DOIUrl":"https://doi.org/10.1109/MWSCAS.1995.510297","url":null,"abstract":"Recent advances in technology are leading to increases in the complexity and applications of analogue and mixed-signal integrated circuits. This trend has been accompanied by an increase in the complexity of associated test specifications. Furthermore, the use of functional and specification based test programs for the analogue circuitry is being questioned due to high implementation costs, the difficulties associated with quantifying the effectiveness of the tests and in many cases difficulties in accessing embedded analogue macros. In addition quality levels expected by integrated circuit (IC) users are increasing, with typical targets currently being better than 40 ppm defect levels. New test solutions are therefore required for these circuit types. Design-for-Test (DfT) strategies are well established for digital circuits, whilst for analogue and mixed signal circuits, few techniques have been proposed and implementation of custom approaches is rare. This paper presents a summary of a number of possible approaches for improving test access by increasing both controllability and observability of internal functional blocks in analogue and mixed-signal ICs, evaluating both their effectiveness and their impact on circuit performance.","PeriodicalId":165081,"journal":{"name":"38th Midwest Symposium on Circuits and Systems. Proceedings","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123750124","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-13DOI: 10.1109/MWSCAS.1995.504504
L. Fernandes, C. Leme, J. Franca
This paper presents a compact realization of cascaded biquad digital filters using 2nd order /spl Delta//spl Sigma/ modulators to avoid the need for multibit multipliers. A bit stream biquad is derived with just one /spl Delta//spl Sigma/ modulator for each pair of poles with no significant degradation of sensitivity nor of dynamic range. The proposed structure leads to a straightforward programmable implementation due to its compactness and modularity.
{"title":"Programmable IIR bitstream filters","authors":"L. Fernandes, C. Leme, J. Franca","doi":"10.1109/MWSCAS.1995.504504","DOIUrl":"https://doi.org/10.1109/MWSCAS.1995.504504","url":null,"abstract":"This paper presents a compact realization of cascaded biquad digital filters using 2nd order /spl Delta//spl Sigma/ modulators to avoid the need for multibit multipliers. A bit stream biquad is derived with just one /spl Delta//spl Sigma/ modulator for each pair of poles with no significant degradation of sensitivity nor of dynamic range. The proposed structure leads to a straightforward programmable implementation due to its compactness and modularity.","PeriodicalId":165081,"journal":{"name":"38th Midwest Symposium on Circuits and Systems. Proceedings","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132779524","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-13DOI: 10.1109/MWSCAS.1995.510283
H. Arango, J. Abreu
This paper deals with the interconnection of systems having different number of phases (heterophasic systems). A matrix theory is developed in order that heterophasic transformations could be devised preserving transmission balance. A three/four-phase transformer exemplifies the theory, showing how the energy flows and electrical symmetry is kept.
{"title":"On the synthesis of heterophasic ideal transformers","authors":"H. Arango, J. Abreu","doi":"10.1109/MWSCAS.1995.510283","DOIUrl":"https://doi.org/10.1109/MWSCAS.1995.510283","url":null,"abstract":"This paper deals with the interconnection of systems having different number of phases (heterophasic systems). A matrix theory is developed in order that heterophasic transformations could be devised preserving transmission balance. A three/four-phase transformer exemplifies the theory, showing how the energy flows and electrical symmetry is kept.","PeriodicalId":165081,"journal":{"name":"38th Midwest Symposium on Circuits and Systems. Proceedings","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133790662","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-13DOI: 10.1109/MWSCAS.1995.504479
C. Gargour, V. Ramachandran
A graphical technique is described, which permits one to obtain the limits of a coefficient of a multiplier in a 2-D stable transfer function having variable magnitude characteristics. It is shown that this method obviates the necessity of evaluating the various determinants and inequalities required for the same purpose, if the method of inners is employed. A computer program is developed to plot such graphs.
{"title":"A graphical technique for the determination of the range of a multiplier in a stable 2-D variable magnitude filter","authors":"C. Gargour, V. Ramachandran","doi":"10.1109/MWSCAS.1995.504479","DOIUrl":"https://doi.org/10.1109/MWSCAS.1995.504479","url":null,"abstract":"A graphical technique is described, which permits one to obtain the limits of a coefficient of a multiplier in a 2-D stable transfer function having variable magnitude characteristics. It is shown that this method obviates the necessity of evaluating the various determinants and inequalities required for the same purpose, if the method of inners is employed. A computer program is developed to plot such graphs.","PeriodicalId":165081,"journal":{"name":"38th Midwest Symposium on Circuits and Systems. Proceedings","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130387634","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-13DOI: 10.1109/MWSCAS.1995.510344
C. Hwang, A. Motamed, M. Ismail
In this paper we propose a new implementation method for the design of op amp input stage with rail-to-rail constant-g/sub m/. The new implementation is based on processing signal currents rather than handling DC tail currents. As a result, it is universal in that the constant-g/sub m/ can be obtained independent of input transistor types (MOS or bipolar) and their operating regions (weak or strong inversion for MOS and active for bipolar). To demonstrate the idea, a new MOS-type input stage has been designed with a 2-/spl mu/m CMOS process and simulation results of input stage transconductance are provided. The common mode input voltage can even exceed the positive and the negative rails by 300 mV.
本文提出了一种轨对轨常数为g/sub / m/的运放输入级设计的新实现方法。新的实现是基于处理信号电流，而不是处理直流尾电流。因此，它是通用的，因为常数g/sub m/可以独立于输入晶体管类型(MOS或双极)及其工作区域(MOS为弱反转或强反转，双极为有源)而获得。为了验证这一思想，采用2-/spl μ m CMOS工艺设计了一种新型mos型输入级，并给出了输入级跨导的仿真结果。共模输入电压甚至可以超过正负轨300毫伏。
{"title":"A new implementation of constant-g/sub m/ op amp input stage for CMOS low voltage applications","authors":"C. Hwang, A. Motamed, M. Ismail","doi":"10.1109/MWSCAS.1995.510344","DOIUrl":"https://doi.org/10.1109/MWSCAS.1995.510344","url":null,"abstract":"In this paper we propose a new implementation method for the design of op amp input stage with rail-to-rail constant-g/sub m/. The new implementation is based on processing signal currents rather than handling DC tail currents. As a result, it is universal in that the constant-g/sub m/ can be obtained independent of input transistor types (MOS or bipolar) and their operating regions (weak or strong inversion for MOS and active for bipolar). To demonstrate the idea, a new MOS-type input stage has been designed with a 2-/spl mu/m CMOS process and simulation results of input stage transconductance are provided. The common mode input voltage can even exceed the positive and the negative rails by 300 mV.","PeriodicalId":165081,"journal":{"name":"38th Midwest Symposium on Circuits and Systems. Proceedings","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134502120","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-13DOI: 10.1109/MWSCAS.1995.510172
M. Jordan
This paper presents a new approach to adaptive predictive control systems with robust characteristics based on nonparametric descriptions. The estimator deals with a parsimonious model of a linear stable plant based on discrete Laguerre functions. The model uncertainties are captured by the estimator as time-varying upper and lower bounds for the Laguerre coefficients. Combining the family of uncertain models with predictive control techniques in an adaptive control loop robust stability can be ensured in a Kharitonov hypercube in the space of controller coefficient. Robust stability conditions and convergence properties of the adaptive control system are performed.
{"title":"Adaptive robust control using discrete Laguerre functions","authors":"M. Jordan","doi":"10.1109/MWSCAS.1995.510172","DOIUrl":"https://doi.org/10.1109/MWSCAS.1995.510172","url":null,"abstract":"This paper presents a new approach to adaptive predictive control systems with robust characteristics based on nonparametric descriptions. The estimator deals with a parsimonious model of a linear stable plant based on discrete Laguerre functions. The model uncertainties are captured by the estimator as time-varying upper and lower bounds for the Laguerre coefficients. Combining the family of uncertain models with predictive control techniques in an adaptive control loop robust stability can be ensured in a Kharitonov hypercube in the space of controller coefficient. Robust stability conditions and convergence properties of the adaptive control system are performed.","PeriodicalId":165081,"journal":{"name":"38th Midwest Symposium on Circuits and Systems. Proceedings","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134383076","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-13DOI: 10.1109/MWSCAS.1995.504368
L. Pirmez, F. C. Carneiro, A. Pedroza, A.C. de Mesquita
A methodology that efficiently transforms Estelle specifications into VHDL descriptions, so that later on integrated circuits can be easily created, is presented. The methodology is based on the silicon compilation technique and its aim is to implement an integrated circuit from a specification in VHDL. Simulation results in Estelle and in VHDL languages are discussed.
{"title":"A methodology to develop integrated circuits from Estelle specifications","authors":"L. Pirmez, F. C. Carneiro, A. Pedroza, A.C. de Mesquita","doi":"10.1109/MWSCAS.1995.504368","DOIUrl":"https://doi.org/10.1109/MWSCAS.1995.504368","url":null,"abstract":"A methodology that efficiently transforms Estelle specifications into VHDL descriptions, so that later on integrated circuits can be easily created, is presented. The methodology is based on the silicon compilation technique and its aim is to implement an integrated circuit from a specification in VHDL. Simulation results in Estelle and in VHDL languages are discussed.","PeriodicalId":165081,"journal":{"name":"38th Midwest Symposium on Circuits and Systems. Proceedings","volume":"50 10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132335988","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-13DOI: 10.1109/MWSCAS.1995.510224
J. S. Neto, S.doN. Neto, Francisco Nascimento
A Self-Organizing Map (SOM) Neural Network for dynamic bit allocation in Adaptive Image Transform Coding is presented. The results shown in this paper are for nets with 30, 96 and 128 neurons in the input layer and 100 (10/spl times/10) neurons in the competition layer. The Learning Vector Quantization LVQ1 algorithm was used to enhance the clustering in the map.
{"title":"Dynamic bit allocation in image coding using a Self-Organizing Map with Learning Vector Quantization","authors":"J. S. Neto, S.doN. Neto, Francisco Nascimento","doi":"10.1109/MWSCAS.1995.510224","DOIUrl":"https://doi.org/10.1109/MWSCAS.1995.510224","url":null,"abstract":"A Self-Organizing Map (SOM) Neural Network for dynamic bit allocation in Adaptive Image Transform Coding is presented. The results shown in this paper are for nets with 30, 96 and 128 neurons in the input layer and 100 (10/spl times/10) neurons in the competition layer. The Learning Vector Quantization LVQ1 algorithm was used to enhance the clustering in the map.","PeriodicalId":165081,"journal":{"name":"38th Midwest Symposium on Circuits and Systems. Proceedings","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131907555","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-13DOI: 10.1109/MWSCAS.1995.510348
M. H. Costa, M. C. Tavares, C. M. Richter, L. Castagno
The vestibular system is important to the maintenance of the static and dynamic equilibrium system of the human body. Disfunctions within this system may lead to abnormal reflex eye movements named nystagmus. The study and analysis of these nystagmus are needed to the precise diagnosis of various pathologies, and is best done with electronystagmography (ENG). Manual analysis of the ENG record is time-consuming, therefore a computerized system was developed for data processing and an algorithm for the automatic evaluation of the nystagmus' slow-component velocity. This algorithm allows a faster and precise evaluation of the nystagmus, through artifact rejection techniques. Comparisons among results obtained with the computerized algorithm and analysis of four specialists over a collection of selected signals presented an error lower than 1/spl deg//s (degrees per second) related to the clinically obtained mean.
{"title":"Automatic analysis of electronystagmographic signals","authors":"M. H. Costa, M. C. Tavares, C. M. Richter, L. Castagno","doi":"10.1109/MWSCAS.1995.510348","DOIUrl":"https://doi.org/10.1109/MWSCAS.1995.510348","url":null,"abstract":"The vestibular system is important to the maintenance of the static and dynamic equilibrium system of the human body. Disfunctions within this system may lead to abnormal reflex eye movements named nystagmus. The study and analysis of these nystagmus are needed to the precise diagnosis of various pathologies, and is best done with electronystagmography (ENG). Manual analysis of the ENG record is time-consuming, therefore a computerized system was developed for data processing and an algorithm for the automatic evaluation of the nystagmus' slow-component velocity. This algorithm allows a faster and precise evaluation of the nystagmus, through artifact rejection techniques. Comparisons among results obtained with the computerized algorithm and analysis of four specialists over a collection of selected signals presented an error lower than 1/spl deg//s (degrees per second) related to the clinically obtained mean.","PeriodicalId":165081,"journal":{"name":"38th Midwest Symposium on Circuits and Systems. Proceedings","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132240831","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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