Pub Date : 2003-06-02DOI: 10.1109/DAC.2003.1219046
Xianfeng Li, T. Mitra, Abhik Roychoudhury
Schedulability analysis of real-time embedded systems requires worst case timing guarantees of embedded software performance. This involves not only language level program analysis, but also modeling the effects of complex micro-architectural features in modern processors. Speculative execution and caching are very common in current processors. Hence one needs to model the effects of these features on the Worst Case Execution (WCET) of a program. Even though the individual effects of these features have been studied recently, their combined effects have not been investigated. We do so in this paper. This is a non-trivial task because speculative execution can indirectly affect cache performance (e.g., speculatively executed blocks can cause additional cache misses). Our technique starts from the control flow graph of the embedded program, and uses integer linear programming to estimate the program's WCET. The accuracy of our modeling is illustrated by tight estimates obtained on realistic benchmarks.
{"title":"Accurate timing analysis by modeling caches, speculation and their interaction","authors":"Xianfeng Li, T. Mitra, Abhik Roychoudhury","doi":"10.1109/DAC.2003.1219046","DOIUrl":"https://doi.org/10.1109/DAC.2003.1219046","url":null,"abstract":"Schedulability analysis of real-time embedded systems requires worst case timing guarantees of embedded software performance. This involves not only language level program analysis, but also modeling the effects of complex micro-architectural features in modern processors. Speculative execution and caching are very common in current processors. Hence one needs to model the effects of these features on the Worst Case Execution (WCET) of a program. Even though the individual effects of these features have been studied recently, their combined effects have not been investigated. We do so in this paper. This is a non-trivial task because speculative execution can indirectly affect cache performance (e.g., speculatively executed blocks can cause additional cache misses). Our technique starts from the control flow graph of the embedded program, and uses integer linear programming to estimate the program's WCET. The accuracy of our modeling is illustrated by tight estimates obtained on realistic benchmarks.","PeriodicalId":167477,"journal":{"name":"Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115344451","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
R. Dahlberg, S. Rawat, J. Bernier, G. Gloski, Aurangzeb Khan, K. Patel, P. Ruddy, N. Sherwani, R. Vasishta
Increasingly, system houses are attracted to the customer-owned tooling (COT) model to gain more control of their schedules and costs. COT project risk and cost are high, often seeming more like customer owned "trouble," so the design team needs to be expertly prepared. The pathways to implement a COT design include (a) Manage the sourcing (internal or third party resources) of individual supply chain and cost reduction functions; (b) Use an integrated design-to-parts service; or (c) A hybrid of these two extremes. This panel will consider the pros and cons for each approach.
{"title":"COT - customer owned trouble","authors":"R. Dahlberg, S. Rawat, J. Bernier, G. Gloski, Aurangzeb Khan, K. Patel, P. Ruddy, N. Sherwani, R. Vasishta","doi":"10.1145/775832.775858","DOIUrl":"https://doi.org/10.1145/775832.775858","url":null,"abstract":"Increasingly, system houses are attracted to the customer-owned tooling (COT) model to gain more control of their schedules and costs. COT project risk and cost are high, often seeming more like customer owned \"trouble,\" so the design team needs to be expertly prepared. The pathways to implement a COT design include (a) Manage the sourcing (internal or third party resources) of individual supply chain and cost reduction functions; (b) Use an integrated design-to-parts service; or (c) A hybrid of these two extremes. This panel will consider the pros and cons for each approach.","PeriodicalId":167477,"journal":{"name":"Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115418217","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
R. Senger, E. Marsman, M. McCorquodale, F. Gebara, K. L. Kraver, Matthew R. Guthaus, Richard B. Brown
In this work, we report on an unprecedented design where digital, analog, and MEMS technologies are combined to realize a general-purpose single-chip CMOS microsystem. The convergence of these technologies has enabled the development of a low power, portable microinstrument ideally suited for controlling environmental and bio-implantable sensors.
{"title":"A 16-bit mixed-signal microsystem with integrated CMOS-MEMS clock reference","authors":"R. Senger, E. Marsman, M. McCorquodale, F. Gebara, K. L. Kraver, Matthew R. Guthaus, Richard B. Brown","doi":"10.1145/775832.775965","DOIUrl":"https://doi.org/10.1145/775832.775965","url":null,"abstract":"In this work, we report on an unprecedented design where digital, analog, and MEMS technologies are combined to realize a general-purpose single-chip CMOS microsystem. The convergence of these technologies has enabled the development of a low power, portable microinstrument ideally suited for controlling environmental and bio-implantable sensors.","PeriodicalId":167477,"journal":{"name":"Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116939259","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Donald Chai, A. Kondratyev, Y. Ran, Ken Tseng, Yosinori Watanabe, M. Marek-Sadowska
Noise affects circuit operation by increasing gate delays and causing latches to capture incorrect values. This paper proposes a method of characterizing correlation of signal transitions in multiple nets by considering both timing and functionality of the signals, and uses it in an analysis procedure to eliminate noise faults that cannot actually happen when such correlations are considered. It uses four-variable Boolean logic to characterize signal transitions in a time interval, and formulates Boolean satisfiability between aggressors and a victim under the min-max delay model for gates. The technique has been successfully applied to commercial ASIC designs and has eliminated up to 35% of delay noise faults reported by a state-of-the-art noise analysis tool.
{"title":"Temporofunctional crosstalk noise analysis","authors":"Donald Chai, A. Kondratyev, Y. Ran, Ken Tseng, Yosinori Watanabe, M. Marek-Sadowska","doi":"10.1145/775832.776048","DOIUrl":"https://doi.org/10.1145/775832.776048","url":null,"abstract":"Noise affects circuit operation by increasing gate delays and causing latches to capture incorrect values. This paper proposes a method of characterizing correlation of signal transitions in multiple nets by considering both timing and functionality of the signals, and uses it in an analysis procedure to eliminate noise faults that cannot actually happen when such correlations are considered. It uses four-variable Boolean logic to characterize signal transitions in a time interval, and formulates Boolean satisfiability between aggressors and a victim under the min-max delay model for gates. The technique has been successfully applied to commercial ASIC designs and has eliminated up to 35% of delay noise faults reported by a state-of-the-art noise analysis tool.","PeriodicalId":167477,"journal":{"name":"Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123751703","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a novel partial assignment technique (PAT) that decides which tasks should be assigned to the same resource without explicitly defining assignment of these tasks to a particular resource. Our method simplifies the assignment and scheduling steps while imposing a small or no penalty on the final solution quality. This technique is specially suited for problems which have different resources constraints. Our method does not cluster tasks into a new task, as typical clustering techniques do, but specifies which tasks need to be executed on the same processor. Our experiments have shown that PAT, which may produce nonlinear groups of tasks, gives better results than linear clustering when multi-resource constraints are present. Linear clustering was proved to be optimal comparing to all other clusterings for problems with timing constraints only. In this paper, we show that, if used for multi-resource synthesis problem, as it is often used nowadays, linear clustering will produce inferior solutions.
{"title":"Partial task assignment of task graphs under heterogeneous resource constraints","authors":"R. Szymanek, K. Kuchcinski","doi":"10.1145/775832.775895","DOIUrl":"https://doi.org/10.1145/775832.775895","url":null,"abstract":"This paper presents a novel partial assignment technique (PAT) that decides which tasks should be assigned to the same resource without explicitly defining assignment of these tasks to a particular resource. Our method simplifies the assignment and scheduling steps while imposing a small or no penalty on the final solution quality. This technique is specially suited for problems which have different resources constraints. Our method does not cluster tasks into a new task, as typical clustering techniques do, but specifies which tasks need to be executed on the same processor. Our experiments have shown that PAT, which may produce nonlinear groups of tasks, gives better results than linear clustering when multi-resource constraints are present. Linear clustering was proved to be optimal comparing to all other clusterings for problems with timing constraints only. In this paper, we show that, if used for multi-resource synthesis problem, as it is often used nowadays, linear clustering will produce inferior solutions.","PeriodicalId":167477,"journal":{"name":"Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123958045","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A time-domain algorithm for computation of the noise power spectral density (PSD) is proposed by V. Vasudevan. When applied to periodically varying circuits, this formulation requires efficient methods to obtain the quasi-periodic steady-state solution of a set of linear time-varying ordinary differential equations. We use both the mixed frequency-time technique (MFT) and the shooting Newton method for this computation. We show that, at each frequency for which the spectral density is sought, MFT requires only two integrations over the duration of the clock period. The results are compared with published experimental and computed data.
V. Vasudevan提出了一种时域噪声功率谱密度(PSD)计算算法。当应用于周期变化电路时，需要有效的方法来获得一组线性时变常微分方程的准周期稳态解。我们使用混合频时技术(MFT)和射击牛顿法进行计算。我们表明，在寻求谱密度的每个频率上，MFT只需要在时钟周期内进行两次积分。结果与已发表的实验和计算数据进行了比较。
{"title":"Computation of noise spectral density in switched capacitor circuits using the mixed-frequency-time technique","authors":"V. Vasudevan, M. Ramakrishna","doi":"10.1145/775832.775968","DOIUrl":"https://doi.org/10.1145/775832.775968","url":null,"abstract":"A time-domain algorithm for computation of the noise power spectral density (PSD) is proposed by V. Vasudevan. When applied to periodically varying circuits, this formulation requires efficient methods to obtain the quasi-periodic steady-state solution of a set of linear time-varying ordinary differential equations. We use both the mixed frequency-time technique (MFT) and the shooting Newton method for this computation. We show that, at each frequency for which the spectral density is sought, MFT requires only two integrations over the duration of the clock period. The results are compared with published experimental and computed data.","PeriodicalId":167477,"journal":{"name":"Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122656561","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In the Artemis project according to A.D. Pimentel et al. (2001), design space exploration of embedded systems is provided by modeling application behavior and architectural performance constraints separately. Mapping an application model onto an architecture model is performed using trace-driven co-simulation, where event traces generated by an application model drive the underlying architecture model. The abstract communication events from the application model may, however, not match the architecture-level communication primitives. This paper presents a trace transformation method, which is based on integer-controlled data-flow models, to perform communication refinement of application-level events. We discuss the proposed method in the context of our prototype modeling and simulation environment. Moreover, using several examples and a case study, we demonstrate that our method allows for efficient exploration of different communication behaviors at architecture level without affecting the application model.
{"title":"An IDF-based trace transformation method for communication refinement","authors":"A. Pimentel, Cagkan Erbas","doi":"10.1145/775832.775937","DOIUrl":"https://doi.org/10.1145/775832.775937","url":null,"abstract":"In the Artemis project according to A.D. Pimentel et al. (2001), design space exploration of embedded systems is provided by modeling application behavior and architectural performance constraints separately. Mapping an application model onto an architecture model is performed using trace-driven co-simulation, where event traces generated by an application model drive the underlying architecture model. The abstract communication events from the application model may, however, not match the architecture-level communication primitives. This paper presents a trace transformation method, which is based on integer-controlled data-flow models, to perform communication refinement of application-level events. We discuss the proposed method in the context of our prototype modeling and simulation environment. Moreover, using several examples and a case study, we demonstrate that our method allows for efficient exploration of different communication behaviors at architecture level without affecting the application model.","PeriodicalId":167477,"journal":{"name":"Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451)","volume":"116 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128654217","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
C. F. Fang, Rob A. Rutenbar, Markus Püschel, Tsuhan Chen
We introduce a static error analysis technique, based on smart interval methods from affine arithmetic, to help designers translate DSP codes from full-precision floating-point to smaller finite-precision formats. The technique gives results for numerical error estimation comparable to detailed simulation, but achieves speedups of three orders of magnitude by avoiding actual bit-level simulation. We show results for experiments mapping common DSP transform algorithms to implementations using small custom floating point formats.
{"title":"Toward efficient static analysis of finite-precision effects in DSP applications via affine arithmetic modeling","authors":"C. F. Fang, Rob A. Rutenbar, Markus Püschel, Tsuhan Chen","doi":"10.1145/775832.775960","DOIUrl":"https://doi.org/10.1145/775832.775960","url":null,"abstract":"We introduce a static error analysis technique, based on smart interval methods from affine arithmetic, to help designers translate DSP codes from full-precision floating-point to smaller finite-precision formats. The technique gives results for numerical error estimation comparable to detailed simulation, but achieves speedups of three orders of magnitude by avoiding actual bit-level simulation. We show results for experiments mapping common DSP transform algorithms to implementations using small custom floating point formats.","PeriodicalId":167477,"journal":{"name":"Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129250028","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-02DOI: 10.1109/DAC.2003.1219012
Jun Yuan, Ken Albin, A. Aziz, C. Pixley
Modeling design environment with constraints instead of a traditional testbench is advantageous in a hybrid verification framework that encompasses simulation and formal verification. This movement is gaining popularity n industry and sparks research in the constraint-based environment modeling and stimulus generation problem. We present an approach, called constraint synthesis, to this problem. Constraint synthesis falls in the general category of parametric Boolean equation solving but is novel in utilizing don't care information unique to hardware constraints and heuristic variable removal to simplify the solution. Experimental results have demonstrated the effectiveness of the proposed approach.
{"title":"Constraint synthesis for environment modeling in functional verification","authors":"Jun Yuan, Ken Albin, A. Aziz, C. Pixley","doi":"10.1109/DAC.2003.1219012","DOIUrl":"https://doi.org/10.1109/DAC.2003.1219012","url":null,"abstract":"Modeling design environment with constraints instead of a traditional testbench is advantageous in a hybrid verification framework that encompasses simulation and formal verification. This movement is gaining popularity n industry and sparks research in the constraint-based environment modeling and stimulus generation problem. We present an approach, called constraint synthesis, to this problem. Constraint synthesis falls in the general category of parametric Boolean equation solving but is novel in utilizing don't care information unique to hardware constraints and heuristic variable removal to simplify the solution. Experimental results have demonstrated the effectiveness of the proposed approach.","PeriodicalId":167477,"journal":{"name":"Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451)","volume":"117 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129283273","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a set of new important results for the problem of task scheduling and voltage allocation in dynamically variable voltage processor for minimizing the total processor energy consumption. The contributions are two folds: 1. for given multiple discrete supply voltages and tasks with arbitrary arrival-time/deadline constraints, we propose a voltage allocation technique which produces a feasible task schedule with optimal processor energy consumption; 2. we then extend the problem to include the case in which tasks have non-uniform load (i.e., switched) capacitances, and solve it optimally.
{"title":"Optimal voltage allocation techniques for dynamically variable voltage processors","authors":"Woo-Cheol Kwon, Taewhan Kim","doi":"10.1145/775832.775867","DOIUrl":"https://doi.org/10.1145/775832.775867","url":null,"abstract":"This paper presents a set of new important results for the problem of task scheduling and voltage allocation in dynamically variable voltage processor for minimizing the total processor energy consumption. The contributions are two folds: 1. for given multiple discrete supply voltages and tasks with arbitrary arrival-time/deadline constraints, we propose a voltage allocation technique which produces a feasible task schedule with optimal processor energy consumption; 2. we then extend the problem to include the case in which tasks have non-uniform load (i.e., switched) capacitances, and solve it optimally.","PeriodicalId":167477,"journal":{"name":"Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130238886","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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