Design verification must be included the power grid. Checking that the voltage on the power grid does not drop by more than some critical threshold is a very difficult problem, for at least two reasons: 1. the obviously large size of the power grids for modern high-performance chips, and 2. the difficulty of setting up the right simulation conditions for the power grid that provide some measure of a realistic worst case voltage drop. The huge number of possible circuit operational modes or workloads makes it impossible to do exhaustive analysis. We propose a static technique for power grid verification, where static is in the sense of static timing analysis, meaning that it does not depend on, nor require, user-specified stimulus to drive a simulation. The verification is posed as an optimization problem under user-supplied current constraints. We propose that current constraints are the right kind of abstraction to use in order to develop a practical methodology for power grid verification. We present our verification approach, and report on the results of applying it to a number of test-case power grids
{"title":"A static pattern-independent technique for power grid voltage integrity verification","authors":"D. Kouroussis, F. Najm","doi":"10.1145/775832.775861","DOIUrl":"https://doi.org/10.1145/775832.775861","url":null,"abstract":"Design verification must be included the power grid. Checking that the voltage on the power grid does not drop by more than some critical threshold is a very difficult problem, for at least two reasons: 1. the obviously large size of the power grids for modern high-performance chips, and 2. the difficulty of setting up the right simulation conditions for the power grid that provide some measure of a realistic worst case voltage drop. The huge number of possible circuit operational modes or workloads makes it impossible to do exhaustive analysis. We propose a static technique for power grid verification, where static is in the sense of static timing analysis, meaning that it does not depend on, nor require, user-specified stimulus to drive a simulation. The verification is posed as an optimization problem under user-supplied current constraints. We propose that current constraints are the right kind of abstraction to use in order to develop a practical methodology for power grid verification. We present our verification approach, and report on the results of applying it to a number of test-case power grids","PeriodicalId":167477,"journal":{"name":"Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127610363","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Recently, Markov sources were shown to be effective in designing pseudo-random test pattern generators with low area overhead for built-in self-test of scan designs. This paper presents a new test pattern generation scheme based on a Markov source and a partial bit-fixing technique. A new method is proposed for the computation of the state transition probabilities of the Markov source based on the statistics of a deterministic test set. This is enhanced by partial bit-fixing logic, which fixes a group of consecutive inputs to all-0 or all-1. Experimental results show that the proposed BIST scheme can achieve 100% fault coverage for large benchmark circuits with reduced hardware overhead and reduced pattern counts compared to the earlier method using Markov sources.
{"title":"A scan BIST generation method using a Markov source and partial bit-fixing","authors":"Wei Li, Chaowen Yu, S. Reddy, I. Pomeranz","doi":"10.1145/775832.775974","DOIUrl":"https://doi.org/10.1145/775832.775974","url":null,"abstract":"Recently, Markov sources were shown to be effective in designing pseudo-random test pattern generators with low area overhead for built-in self-test of scan designs. This paper presents a new test pattern generation scheme based on a Markov source and a partial bit-fixing technique. A new method is proposed for the computation of the state transition probabilities of the Markov source based on the statistics of a deterministic test set. This is enhanced by partial bit-fixing logic, which fixes a group of consecutive inputs to all-0 or all-1. Experimental results show that the proposed BIST scheme can achieve 100% fault coverage for large benchmark circuits with reduced hardware overhead and reduced pattern counts compared to the earlier method using Markov sources.","PeriodicalId":167477,"journal":{"name":"Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127712420","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
L. Benini, A. Macii, E. Macii, Elvira Omerbegovic, Fabrizio Pro, M. Poncino
Differential power analysis is a very effective cryptanalysis technique that extracts information on secret keys by monitoring instantaneous power consumption of cryptoprocessors. To protect against differential power analysis, power supply noise is added in cryptographic computations, at the price of an increase in power consumption. We present a technique, based on well-known power-reducing transformations coupled with randomized clock gating, that introduces a significant amount of scrambling in the power profile without increasing (and, in some cases, by even reducing) circuit power consumption.
{"title":"Energy-aware design techniques for differential power analysis protection","authors":"L. Benini, A. Macii, E. Macii, Elvira Omerbegovic, Fabrizio Pro, M. Poncino","doi":"10.1145/775832.775845","DOIUrl":"https://doi.org/10.1145/775832.775845","url":null,"abstract":"Differential power analysis is a very effective cryptanalysis technique that extracts information on secret keys by monitoring instantaneous power consumption of cryptoprocessors. To protect against differential power analysis, power supply noise is added in cryptographic computations, at the price of an increase in power consumption. We present a technique, based on well-known power-reducing transformations coupled with randomized clock gating, that introduces a significant amount of scrambling in the power profile without increasing (and, in some cases, by even reducing) circuit power consumption.","PeriodicalId":167477,"journal":{"name":"Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127998748","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-02DOI: 10.1109/DAC.2003.1218937
C. Long, Lei He
Sleep transistors are effective to reduce dynamic and leakage power. The cluster-based design was proposed to reduce the sleep transistor area by clustering gates to minimize the simultaneous switching current per cluster and then inserting a sleep transistor per cluster. In the paper, we propose a novel distributed sleep transistor network (DSTN), and show that DSTN is intrinsically better than the cluster-based design in terms of the sleep transistor area and circuit performance. We reveal properties of optimal DSTN designs, and then develop an efficient algorithm for gate level DSTN synthesis. The algorithm obtains DSTN designs with up to 70.7% sleep transistor area reduction compared to cluster-based designs. Furthermore, we present custom layout designs to verify the area reduction by DSTN.
{"title":"Distributed sleep transistors network for power reduction","authors":"C. Long, Lei He","doi":"10.1109/DAC.2003.1218937","DOIUrl":"https://doi.org/10.1109/DAC.2003.1218937","url":null,"abstract":"Sleep transistors are effective to reduce dynamic and leakage power. The cluster-based design was proposed to reduce the sleep transistor area by clustering gates to minimize the simultaneous switching current per cluster and then inserting a sleep transistor per cluster. In the paper, we propose a novel distributed sleep transistor network (DSTN), and show that DSTN is intrinsically better than the cluster-based design in terms of the sleep transistor area and circuit performance. We reveal properties of optimal DSTN designs, and then develop an efficient algorithm for gate level DSTN synthesis. The algorithm obtains DSTN designs with up to 70.7% sleep transistor area reduction compared to cluster-based designs. Furthermore, we present custom layout designs to verify the area reduction by DSTN.","PeriodicalId":167477,"journal":{"name":"Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132620641","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Early power analysis for systems-on-chip (SoC) is crucial for determining the appropriate packaging and cost. This early analysis commonly relies on evaluating power formulas for all cores for multiple configurations of voltage, frequency, technology and application parameters, which is a tedious and error-prone process. This work presents a methodology and algorithms for automating the power analysis of SoCs. Given the power state machines for individual cores, this work defines the product power state machine for the whole SoC and uses formal symbolic simulation algorithms for traversing and computing the minimum and maximum power dissipated by sets of power states in the SoC.
{"title":"State-based power analysis for systems-on-chip","authors":"R. Bergamaschi, Yunjian Jiang","doi":"10.1145/775832.775992","DOIUrl":"https://doi.org/10.1145/775832.775992","url":null,"abstract":"Early power analysis for systems-on-chip (SoC) is crucial for determining the appropriate packaging and cost. This early analysis commonly relies on evaluating power formulas for all cores for multiple configurations of voltage, frequency, technology and application parameters, which is a tedious and error-prone process. This work presents a methodology and algorithms for automating the power analysis of SoCs. Given the power state machines for individual cores, this work defines the product power state machine for the whole SoC and uses formal symbolic simulation algorithms for traversing and computing the minimum and maximum power dissipated by sets of power states in the SoC.","PeriodicalId":167477,"journal":{"name":"Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131825201","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Sungwoo Hur, Tung Cao, K. Rajagopal, Yegna Parasuram, Amit Chowdhary, V. Tiourin, Bill Halpin
This paper describes a new force directed global placement algorithm that exploits and extends techniques from two leading placers, force-directed according to H. Eisenmann and F.M. Johannes (1998) and T. Cao et al. (2003) and Mongrel by S. Hur and J. Lillis (2000). It combines the strengths of force directed global placement with Mongrel's cell congestion removal to significantly improve the quality of placement during the difficult overlap removal stage of global placement. This is accomplished by using the spreading force in according to H. Eisenmann and F. M. Johannes (1998) to direct and control Mongrel's ripple move optimization. This new placer is called force directed Mongrel (FD-Mongrel). FD-Mongrel also incorporates physical net constraints according to T. Cao et al. (2003), and improves the congestion model for sparse placements. We propose a new placement flow that uses a limited number of the spreading iterations of generic global placement by H. Eisenmann and F. M. Johannes (1998) to form a preliminary global placement. We then use the new FD-Mongrel described in this paper to remove cell overlaps, while meeting net constraints and optimizing wirelength. We present results on wirelength as well as timing driven placement flows.
本文描述了一种新的力导向全局放置算法，该算法利用并扩展了两种领先的放置技术，即H. Eisenmann和F.M. Johannes(1998)以及T. Cao等人(2003)的力导向技术，以及S. Hur和J. Lillis(2000)的Mongrel。它结合了力定向全局布局的优势和Mongrel的蜂窝拥塞去除，在全局布局的困难重叠去除阶段显著提高了布局质量。根据H. Eisenmann和F. M. Johannes(1998)的说法，这是通过使用扩展力来指导和控制Mongrel的涟漪移动优化来实现的。这种新的砂矿被称为力定向混合砂矿(FD-Mongrel)。根据T. Cao等人(2003)，FD-Mongrel还纳入了物理网络约束，并改进了稀疏位置的拥塞模型。我们提出了一种新的安置流程，该流程使用H. Eisenmann和F. M. Johannes(1998)的通用全局安置的有限数量的传播迭代来形成初步的全局安置。然后，我们使用本文中描述的新的FD-Mongrel来去除单元重叠，同时满足网络约束并优化无线长度。我们提出的结果在无线以及定时驱动的安置流。
{"title":"Force directed Mongrel with physical net constraints","authors":"Sungwoo Hur, Tung Cao, K. Rajagopal, Yegna Parasuram, Amit Chowdhary, V. Tiourin, Bill Halpin","doi":"10.1145/775832.775888","DOIUrl":"https://doi.org/10.1145/775832.775888","url":null,"abstract":"This paper describes a new force directed global placement algorithm that exploits and extends techniques from two leading placers, force-directed according to H. Eisenmann and F.M. Johannes (1998) and T. Cao et al. (2003) and Mongrel by S. Hur and J. Lillis (2000). It combines the strengths of force directed global placement with Mongrel's cell congestion removal to significantly improve the quality of placement during the difficult overlap removal stage of global placement. This is accomplished by using the spreading force in according to H. Eisenmann and F. M. Johannes (1998) to direct and control Mongrel's ripple move optimization. This new placer is called force directed Mongrel (FD-Mongrel). FD-Mongrel also incorporates physical net constraints according to T. Cao et al. (2003), and improves the congestion model for sparse placements. We propose a new placement flow that uses a limited number of the spreading iterations of generic global placement by H. Eisenmann and F. M. Johannes (1998) to form a preliminary global placement. We then use the new FD-Mongrel described in this paper to remove cell overlaps, while meeting net constraints and optimizing wirelength. We present results on wirelength as well as timing driven placement flows.","PeriodicalId":167477,"journal":{"name":"Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134482813","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Bo Hu, Yosinori Watanabe, A. Kondratyev, M. Marek-Sadowska
In this paper we describe a technology mapping technique based on the logical effort theory by I. Sutherland and R. Sproull (1991). First, we appropriately characterize a given standard cell library and extract from it a set of cell classes. Each cell-class is assigned a constant-delay model and corresponding load-bounds, which define the conditions of the delay model's validity. Next, we perform technology mapping using the classes determined in the first step. We propose several effective area-optimization heuristics which allow us to apply our algorithm directly to general graphs. Experimental results show that our gain-based mapping algorithm achieves reduced delay with less area, compared to the mapper in SIS by E. Sentovich et al. (1992). By adjusting the constant delay model associated with each class, we determine the area-delay trade-off curve. We achieve the best area-delay trade-off using a design-specific constant delay models.
本文描述了一种基于I. Sutherland和R. Sproull(1991)的逻辑努力理论的技术映射技术。首先，我们适当地描述给定的标准细胞库，并从中提取一组细胞类。每个单元格类被赋予一个恒定延迟模型和相应的负载边界，定义了延迟模型的有效性条件。接下来，我们使用第一步中确定的类执行技术映射。我们提出了几种有效的面积优化启发式算法，使我们能够将我们的算法直接应用于一般图。实验结果表明，与E. Sentovich et al.(1992)在SIS中的映射器相比，我们基于增益的映射算法实现了以更小的面积减少延迟。通过调整与每个类相关的恒定延迟模型，确定了区域延迟权衡曲线。我们使用特定于设计的常数延迟模型实现了最佳的区域延迟权衡。
{"title":"Gain-based technology mapping for discrete-size cell libraries","authors":"Bo Hu, Yosinori Watanabe, A. Kondratyev, M. Marek-Sadowska","doi":"10.1145/775832.775979","DOIUrl":"https://doi.org/10.1145/775832.775979","url":null,"abstract":"In this paper we describe a technology mapping technique based on the logical effort theory by I. Sutherland and R. Sproull (1991). First, we appropriately characterize a given standard cell library and extract from it a set of cell classes. Each cell-class is assigned a constant-delay model and corresponding load-bounds, which define the conditions of the delay model's validity. Next, we perform technology mapping using the classes determined in the first step. We propose several effective area-optimization heuristics which allow us to apply our algorithm directly to general graphs. Experimental results show that our gain-based mapping algorithm achieves reduced delay with less area, compared to the mapper in SIS by E. Sentovich et al. (1992). By adjusting the constant delay model associated with each class, we determine the area-delay trade-off curve. We achieve the best area-delay trade-off using a design-specific constant delay models.","PeriodicalId":167477,"journal":{"name":"Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451)","volume":"362 Pt 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124268606","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-02DOI: 10.1109/DAC.2003.1219130
Hsun-Cheng Lee, Yao-Wen Chang, J. Hsu, Hannah Honghua Yang
We present in this paper a multilevel floorplanning/placement framework based on the B*-tree representation, called MB*-tree, to handle the floorplanning and packing for large-scale building modules. The MB*-tree adopts a two-stage technique, clustering followed by declustering. The clustering stage iteratively groups a set of modules based on a cost metric guided by area utilization and module connectivity, and at the same time establishes the geometric relations for the newly clustered modules by constructing a corresponding B*-tree for them. The declustering stage iteratively ungroup a set of the previously clustered modules (i.e., perform tree expansion) and then refines the floorplanning/placement solution by using a simulated annealing scheme. In particular, the MB*-tree preserves the geometric relations among modules during declustering, which makes the MB*-tree an ideal data structure for the multilevel floorplanning/placement framework. Experimental results show that the MB*-tree obtains significantly better silicon area and wirelength than previous works. Further, unlike previous works, MB*-tree scales very well as the circuit size increases.
{"title":"Multilevel floorplanning/placement for large-scale modules using B*-trees","authors":"Hsun-Cheng Lee, Yao-Wen Chang, J. Hsu, Hannah Honghua Yang","doi":"10.1109/DAC.2003.1219130","DOIUrl":"https://doi.org/10.1109/DAC.2003.1219130","url":null,"abstract":"We present in this paper a multilevel floorplanning/placement framework based on the B*-tree representation, called MB*-tree, to handle the floorplanning and packing for large-scale building modules. The MB*-tree adopts a two-stage technique, clustering followed by declustering. The clustering stage iteratively groups a set of modules based on a cost metric guided by area utilization and module connectivity, and at the same time establishes the geometric relations for the newly clustered modules by constructing a corresponding B*-tree for them. The declustering stage iteratively ungroup a set of the previously clustered modules (i.e., perform tree expansion) and then refines the floorplanning/placement solution by using a simulated annealing scheme. In particular, the MB*-tree preserves the geometric relations among modules during declustering, which makes the MB*-tree an ideal data structure for the multilevel floorplanning/placement framework. Experimental results show that the MB*-tree obtains significantly better silicon area and wirelength than previous works. Further, unlike previous works, MB*-tree scales very well as the circuit size increases.","PeriodicalId":167477,"journal":{"name":"Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451)","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133150074","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, we discuss the many issues around the system and circuit design of advanced RF front ends for mobile, wireless and consumer RF applications. After an analysis of the application trends, technology choices linked to the different systems solutions is discussed.
{"title":"RF front end application and technology trends","authors":"P. Hooijmans","doi":"10.1145/775832.775854","DOIUrl":"https://doi.org/10.1145/775832.775854","url":null,"abstract":"In this paper, we discuss the many issues around the system and circuit design of advanced RF front ends for mobile, wireless and consumer RF applications. After an analysis of the application trends, technology choices linked to the different systems solutions is discussed.","PeriodicalId":167477,"journal":{"name":"Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451)","volume":"40 11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132760683","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
To save energy, many power management policies rely on issuing mode-change commands to the components of the system. Efforts to date have focused on how these policies interact with the external workload. However, the energy savings are ultimately limited by the set of power-saving modes available to the power manager. This paper proposes new power-saving opportunities to existing system-level power managers by handling each desired mode change in terms of an optimal sequence of mode transitions involving multiple components. We employ algorithms to optimize these transition sequences in polynomial time, making them applicable to static and dynamic policies. The decoupling between policies and mechanisms also makes this approach modular and scalable to devices with complex modes and intricate dependencies on other devices in the system. Experimental results show significant energy savings due to these sequentialized mode-change opportunities that would otherwise be difficult to discover manually even by experienced designers.
{"title":"Scalable modeling and optimization of mode transitions based on decoupled power management architecture","authors":"Dexin Li, Q. Xie, P. Chou","doi":"10.1145/775832.775866","DOIUrl":"https://doi.org/10.1145/775832.775866","url":null,"abstract":"To save energy, many power management policies rely on issuing mode-change commands to the components of the system. Efforts to date have focused on how these policies interact with the external workload. However, the energy savings are ultimately limited by the set of power-saving modes available to the power manager. This paper proposes new power-saving opportunities to existing system-level power managers by handling each desired mode change in terms of an optimal sequence of mode transitions involving multiple components. We employ algorithms to optimize these transition sequences in polynomial time, making them applicable to static and dynamic policies. The decoupling between policies and mechanisms also makes this approach modular and scalable to devices with complex modes and intricate dependencies on other devices in the system. Experimental results show significant energy savings due to these sequentialized mode-change opportunities that would otherwise be difficult to discover manually even by experienced designers.","PeriodicalId":167477,"journal":{"name":"Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451)","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121727054","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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