Pub Date : 1980-09-01DOI: 10.1109/ESSCIRC.1980.5468752
B. Hennion, G. Mazaré
After having first introduced what is an integrated CAD system and the functions it has to perform, this paper describes the particularities of CASSIOPEE, a prototype under development at CNET-GRENOBLE, of its realization, and of the timing simulator which is its first running component.
{"title":"CASSIOPEE-An Integrated CAD System for Integrated Circuits","authors":"B. Hennion, G. Mazaré","doi":"10.1109/ESSCIRC.1980.5468752","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1980.5468752","url":null,"abstract":"After having first introduced what is an integrated CAD system and the functions it has to perform, this paper describes the particularities of CASSIOPEE, a prototype under development at CNET-GRENOBLE, of its realization, and of the timing simulator which is its first running component.","PeriodicalId":168272,"journal":{"name":"ESSCIRC 80: 6th European Solid State Circuits Conference","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1980-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117253493","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1980-09-01DOI: 10.1109/ESSCIRC.1980.5468773
J. Rainard, Y. Vernay
A single chip integrated multiplier working on 16 bit words dotted with two different operating modes (serial or parallel) and able to signal out any failure by means of an internal supervision system (for some 25% extra silicon area).
{"title":"A 16 Bit Self-Testing Multiplier","authors":"J. Rainard, Y. Vernay","doi":"10.1109/ESSCIRC.1980.5468773","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1980.5468773","url":null,"abstract":"A single chip integrated multiplier working on 16 bit words dotted with two different operating modes (serial or parallel) and able to signal out any failure by means of an internal supervision system (for some 25% extra silicon area).","PeriodicalId":168272,"journal":{"name":"ESSCIRC 80: 6th European Solid State Circuits Conference","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1980-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126813068","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1980-09-01DOI: 10.1109/ESSCIRC.1980.5468769
R. Ranfft, H. Rein
A simple rapidly converging optimization routine for non saturated digital IC's is described. It yields the minimum delay for a given power dissipation per gate by varying easily controllable technological parameters. The basic gates of various circuit techniques are compared using this routine.
{"title":"Optimization and Comparison of Various Subnanosecond Bipolar IC's with Low Power Dissipation","authors":"R. Ranfft, H. Rein","doi":"10.1109/ESSCIRC.1980.5468769","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1980.5468769","url":null,"abstract":"A simple rapidly converging optimization routine for non saturated digital IC's is described. It yields the minimum delay for a given power dissipation per gate by varying easily controllable technological parameters. The basic gates of various circuit techniques are compared using this routine.","PeriodicalId":168272,"journal":{"name":"ESSCIRC 80: 6th European Solid State Circuits Conference","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1980-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116593651","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1980-09-01DOI: 10.1109/ESSCIRC.1980.5468756
F. Durbin, M. Heydemann, J. Montaron
2 new and efficient methods of solution for the general non-linear programming problem: minimize F(x)=F(x1, x2,...xn) in the domain S:ai<;xi<;bi such that g(x)>;0, h(x)=0, have been implemented in the C.A.D. program ASTEC-3. As an illustration, we present the results we obtained in the D.C. operation optimization of a CMOS/SOS differential amplifier.
{"title":"Towards Global Optimization of Electronic Circuits for D.C. Operation","authors":"F. Durbin, M. Heydemann, J. Montaron","doi":"10.1109/ESSCIRC.1980.5468756","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1980.5468756","url":null,"abstract":"2 new and efficient methods of solution for the general non-linear programming problem: minimize F(x)=F(x<sub>1</sub>, x<sub>2</sub>,...x<sub>n</sub>) in the domain S:a<sub>i</sub><;x<sub>i</sub><;b<sub>i</sub> such that g(x)>;0, h(x)=0, have been implemented in the C.A.D. program ASTEC-3. As an illustration, we present the results we obtained in the D.C. operation optimization of a CMOS/SOS differential amplifier.","PeriodicalId":168272,"journal":{"name":"ESSCIRC 80: 6th European Solid State Circuits Conference","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1980-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127893657","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1980-09-01DOI: 10.1109/ESSCIRC.1980.5468804
G. Weckler
The marriage of switched capacitor filter technology with fuseable links from ROM technology has resulted in a basic analog filter building block. This device is user programmable and may be used to realize a wide range of bandpass and low-pass responses.
{"title":"User Programmable Switched Capacitor Filters","authors":"G. Weckler","doi":"10.1109/ESSCIRC.1980.5468804","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1980.5468804","url":null,"abstract":"The marriage of switched capacitor filter technology with fuseable links from ROM technology has resulted in a basic analog filter building block. This device is user programmable and may be used to realize a wide range of bandpass and low-pass responses.","PeriodicalId":168272,"journal":{"name":"ESSCIRC 80: 6th European Solid State Circuits Conference","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1980-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115266454","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1980-09-01DOI: 10.1109/ESSCIRC.1980.5468780
E. Habekotté, B. Hofflinger, W. Renker, G. Zimmer
A 300 V power switch using planar n-channel DMOS and p-channel pinched resistance transistors to switch dynamically currents of 300 mA will be presented here.
{"title":"A 300 Volt CMOS Coplanar Power Switch","authors":"E. Habekotté, B. Hofflinger, W. Renker, G. Zimmer","doi":"10.1109/ESSCIRC.1980.5468780","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1980.5468780","url":null,"abstract":"A 300 V power switch using planar n-channel DMOS and p-channel pinched resistance transistors to switch dynamically currents of 300 mA will be presented here.","PeriodicalId":168272,"journal":{"name":"ESSCIRC 80: 6th European Solid State Circuits Conference","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1980-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123863747","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1980-09-01DOI: 10.1109/ESSCIRC.1980.5468785
W. Barber, E. Brown
This paper describes a limiting amplifier designed for radar intermediate frequency applications where negligible phase shift with change of input signal level is required.
本文介绍了一种用于雷达中频应用的限幅放大器，该应用要求随输入信号电平变化而产生的相移可以忽略不计。
{"title":"A Constant Phase Limiting Amplifier","authors":"W. Barber, E. Brown","doi":"10.1109/ESSCIRC.1980.5468785","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1980.5468785","url":null,"abstract":"This paper describes a limiting amplifier designed for radar intermediate frequency applications where negligible phase shift with change of input signal level is required.","PeriodicalId":168272,"journal":{"name":"ESSCIRC 80: 6th European Solid State Circuits Conference","volume":"110 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1980-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121413107","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1980-09-01DOI: 10.1109/ESSCIRC.1980.5468757
A. El Moselhi, R. Castagné, C. Rault
Both implementation and practical applications of a macro-simulator for GaAs IC circuits are described. The program is based on a macromodeling technique using presolved symbolic input-output relationships and a simulation technique taking advantage of unidirectionality and latency.
{"title":"A Macromodel and a Macrosimulator for GaAs FET Digital Integrated Circuits","authors":"A. El Moselhi, R. Castagné, C. Rault","doi":"10.1109/ESSCIRC.1980.5468757","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1980.5468757","url":null,"abstract":"Both implementation and practical applications of a macro-simulator for GaAs IC circuits are described. The program is based on a macromodeling technique using presolved symbolic input-output relationships and a simulation technique taking advantage of unidirectionality and latency.","PeriodicalId":168272,"journal":{"name":"ESSCIRC 80: 6th European Solid State Circuits Conference","volume":"508 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1980-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123568440","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1980-09-01DOI: 10.1109/ESSCIRC.1980.5468800
J. Blachere, C. Benichou, H. Braquet
A 144 elements array of transistor crosspoints has been realized. It achieves low insertion loss and high dynamic breakdown using a conventional bipolar technology. The chip measures 4.3 × 4.1 mm2 and is mounted on a 76 pins substrate.
{"title":"An Integrated MSI Crosspoints Array","authors":"J. Blachere, C. Benichou, H. Braquet","doi":"10.1109/ESSCIRC.1980.5468800","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1980.5468800","url":null,"abstract":"A 144 elements array of transistor crosspoints has been realized. It achieves low insertion loss and high dynamic breakdown using a conventional bipolar technology. The chip measures 4.3 × 4.1 mm2 and is mounted on a 76 pins substrate.","PeriodicalId":168272,"journal":{"name":"ESSCIRC 80: 6th European Solid State Circuits Conference","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1980-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124870862","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1980-09-01DOI: 10.1109/ESSCIRC.1980.5468759
N. Ballay, B. Baylac, Patrick Ledanois
We present a CAD model of SOS-MOS transistor with the channel length in the range of 2 μm, and the method for the parameter acquisition on an automatic system driven by a desk-top computer, for the case of the bulk not externally available.
{"title":"CAD Modeling of 2 μm SOS-MOS Transistor and the Parameter Acquisition on an Automatic System","authors":"N. Ballay, B. Baylac, Patrick Ledanois","doi":"10.1109/ESSCIRC.1980.5468759","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1980.5468759","url":null,"abstract":"We present a CAD model of SOS-MOS transistor with the channel length in the range of 2 μm, and the method for the parameter acquisition on an automatic system driven by a desk-top computer, for the case of the bulk not externally available.","PeriodicalId":168272,"journal":{"name":"ESSCIRC 80: 6th European Solid State Circuits Conference","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1980-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124921953","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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