Pub Date : 1980-09-01DOI: 10.1109/ESSCIRC.1980.5468814
M. Tuthill
A 16 bit monolithic D/A converter is described. The device is fabricated with a thin film on CMOS process and uses laser wafer trimming (LWT) to obtain the required performance. The paper briefly discusses design techniques for high resolution D/A converters which have been investigated and describes the circuit finally used.
{"title":"A 16 Bit Monolithic CMOS D/A Converter","authors":"M. Tuthill","doi":"10.1109/ESSCIRC.1980.5468814","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1980.5468814","url":null,"abstract":"A 16 bit monolithic D/A converter is described. The device is fabricated with a thin film on CMOS process and uses laser wafer trimming (LWT) to obtain the required performance. The paper briefly discusses design techniques for high resolution D/A converters which have been investigated and describes the circuit finally used.","PeriodicalId":168272,"journal":{"name":"ESSCIRC 80: 6th European Solid State Circuits Conference","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1980-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126107297","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1980-09-01DOI: 10.1109/ESSCIRC.1980.5468764
W. Haug, R. Schnadt
The twin cell - a double-ended dynamic two-device FET memory cell - is the basic element for a really symmetrical sense system. This new approach has successfully been used in three different byte wide 18K RAM chips.
{"title":"The Twin Cell for a New Dynamic Storage Approach in Three 18K FET RAM Chips","authors":"W. Haug, R. Schnadt","doi":"10.1109/ESSCIRC.1980.5468764","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1980.5468764","url":null,"abstract":"The twin cell - a double-ended dynamic two-device FET memory cell - is the basic element for a really symmetrical sense system. This new approach has successfully been used in three different byte wide 18K RAM chips.","PeriodicalId":168272,"journal":{"name":"ESSCIRC 80: 6th European Solid State Circuits Conference","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1980-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122422597","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1980-09-01DOI: 10.1109/ESSCIRC.1980.5468807
M. Feil, A. Bardl, H. Betzl, O. Poenisch, R. Sehreiber
Two high-grade monolithic bandselect filters are presented using the advantages of a novel passive CCD resonator. The relative bandwidths are 0.08% and 3.1% at respective center frequencies of 131.85 kHz and 10.41 kHz.
{"title":"High Selective Recursive CCD Filters","authors":"M. Feil, A. Bardl, H. Betzl, O. Poenisch, R. Sehreiber","doi":"10.1109/ESSCIRC.1980.5468807","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1980.5468807","url":null,"abstract":"Two high-grade monolithic bandselect filters are presented using the advantages of a novel passive CCD resonator. The relative bandwidths are 0.08% and 3.1% at respective center frequencies of 131.85 kHz and 10.41 kHz.","PeriodicalId":168272,"journal":{"name":"ESSCIRC 80: 6th European Solid State Circuits Conference","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1980-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122619216","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1980-09-01DOI: 10.1109/ESSCIRC.1980.5468790
K. Horninger, G. Grassl, I. Bromme, U. Schwabe
An 8 kbit RAM + I/O peripheral circuit for microprocessors has been realized in a scaled NMOS single-layer poly technology. Cycle time is 250 ns, counter frequency is 10 MHz, chip size is 27.6 mm2 and the supply current is approx. 200 mA, with 5 V supply voltage.
{"title":"An 8kbit RAM + I/O Peripheral Circuit for Microprocessors","authors":"K. Horninger, G. Grassl, I. Bromme, U. Schwabe","doi":"10.1109/ESSCIRC.1980.5468790","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1980.5468790","url":null,"abstract":"An 8 kbit RAM + I/O peripheral circuit for microprocessors has been realized in a scaled NMOS single-layer poly technology. Cycle time is 250 ns, counter frequency is 10 MHz, chip size is 27.6 mm2 and the supply current is approx. 200 mA, with 5 V supply voltage.","PeriodicalId":168272,"journal":{"name":"ESSCIRC 80: 6th European Solid State Circuits Conference","volume":"140 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1980-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127012006","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1980-09-01DOI: 10.1109/ESSCIRC.1980.5468731
J. Picquendar
Functioning of telematic systems uses three types of equipments. The microprocessors, RAM, ROM and the keyboard interface are standard components, whereas the character generators and the image generators and lastly specific power supply and sweep circuits don't fall in the same category. The modems are also too expensive in relation to the prices which should be attained.
{"title":"Components for the telematics","authors":"J. Picquendar","doi":"10.1109/ESSCIRC.1980.5468731","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1980.5468731","url":null,"abstract":"Functioning of telematic systems uses three types of equipments. The microprocessors, RAM, ROM and the keyboard interface are standard components, whereas the character generators and the image generators and lastly specific power supply and sweep circuits don't fall in the same category. The modems are also too expensive in relation to the prices which should be attained.","PeriodicalId":168272,"journal":{"name":"ESSCIRC 80: 6th European Solid State Circuits Conference","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1980-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121776729","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1980-09-01DOI: 10.1109/ESSCIRC.1980.5468715
R. Noyce
Further advances in microelectronics will require a shift from process technology to design technology, and from hardware to software. Political, societal, and environmental constraints may present a larger challenge in the next decade than the development of the technology.
{"title":"Challenges in the 80's for Microelectronics","authors":"R. Noyce","doi":"10.1109/ESSCIRC.1980.5468715","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1980.5468715","url":null,"abstract":"Further advances in microelectronics will require a shift from process technology to design technology, and from hardware to software. Political, societal, and environmental constraints may present a larger challenge in the next decade than the development of the technology.","PeriodicalId":168272,"journal":{"name":"ESSCIRC 80: 6th European Solid State Circuits Conference","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1980-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133984201","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1980-09-01DOI: 10.1109/ESSCIRC.1980.5468771
H. E. Oldham
Two high performance CMOS/SOS devices for use in digital signal processing applications are described: a 16-bit parallel multiplier featuring a novel logic implementation and a 3 × 8-bit adder-subtractor circuit.
{"title":"CMOS/SOS 16-Bit Parallel Multiplier and Adder-Subtractor","authors":"H. E. Oldham","doi":"10.1109/ESSCIRC.1980.5468771","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1980.5468771","url":null,"abstract":"Two high performance CMOS/SOS devices for use in digital signal processing applications are described: a 16-bit parallel multiplier featuring a novel logic implementation and a 3 × 8-bit adder-subtractor circuit.","PeriodicalId":168272,"journal":{"name":"ESSCIRC 80: 6th European Solid State Circuits Conference","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1980-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130308472","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1980-09-01DOI: 10.1109/ESSCIRC.1980.5468798
J. Harbridge, R. H. Macmillan
This paper describes a digital filter and level detector (FAD) circuit realised in MOS technology. The architecture makes it suitable for a wide range of applications, particularly in the telecommunications field.
{"title":"An MOS Digital Filter Circuit","authors":"J. Harbridge, R. H. Macmillan","doi":"10.1109/ESSCIRC.1980.5468798","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1980.5468798","url":null,"abstract":"This paper describes a digital filter and level detector (FAD) circuit realised in MOS technology. The architecture makes it suitable for a wide range of applications, particularly in the telecommunications field.","PeriodicalId":168272,"journal":{"name":"ESSCIRC 80: 6th European Solid State Circuits Conference","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1980-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131731721","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1980-09-01DOI: 10.1109/ESSCIRC.1980.5468755
Hariom Gupta, J. Sharma
For the analysis of large circuits,a decomposition technique is presented which requires less computer memory and is efficient. Decomposition is carried out at physical structure level by removing few interconnections. This method is applicable for the analysis of linear and nonlinear circuits.
{"title":"Decomposition Technique for Circuit Analysis","authors":"Hariom Gupta, J. Sharma","doi":"10.1109/ESSCIRC.1980.5468755","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1980.5468755","url":null,"abstract":"For the analysis of large circuits,a decomposition technique is presented which requires less computer memory and is efficient. Decomposition is carried out at physical structure level by removing few interconnections. This method is applicable for the analysis of linear and nonlinear circuits.","PeriodicalId":168272,"journal":{"name":"ESSCIRC 80: 6th European Solid State Circuits Conference","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1980-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132448498","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1980-09-01DOI: 10.1109/ESSCIRC.1980.5468746
A. D. Newton, G. W. Perkins
A bipolar linear PAL colour decoder, with provision for multi-standard operation, on-screen display and an automatic C.R.T. current set-up system, is described. This device uses a 40 pin DIL plastic package.
{"title":"A Monolithic PAL Colour T.V. Processor with Automatic C.R.T. Current Set-Up","authors":"A. D. Newton, G. W. Perkins","doi":"10.1109/ESSCIRC.1980.5468746","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1980.5468746","url":null,"abstract":"A bipolar linear PAL colour decoder, with provision for multi-standard operation, on-screen display and an automatic C.R.T. current set-up system, is described. This device uses a 40 pin DIL plastic package.","PeriodicalId":168272,"journal":{"name":"ESSCIRC 80: 6th European Solid State Circuits Conference","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1980-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122357747","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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