Pub Date : 1998-02-23DOI: 10.1109/DATE.1998.655859
Bill Lin
Currently, run-time operating systems are widely used to implement concurrent embedded applications. This run-time approach to multi-tasking and inter-process communication can introduce significant overhead to execution times and memory requirements-prohibitive in many cases for embedded applications where processor and memory resources are scarce. In this paper, we present a static compilation approach that generates ordinary C programs at compile-time that can be readily retargeted to different processors, without including or generating a run-time scheduler. Our method is based on a novel Petri net theoretic approach.
{"title":"Efficient compilation of process-based concurrent programs without run-time scheduling","authors":"Bill Lin","doi":"10.1109/DATE.1998.655859","DOIUrl":"https://doi.org/10.1109/DATE.1998.655859","url":null,"abstract":"Currently, run-time operating systems are widely used to implement concurrent embedded applications. This run-time approach to multi-tasking and inter-process communication can introduce significant overhead to execution times and memory requirements-prohibitive in many cases for embedded applications where processor and memory resources are scarce. In this paper, we present a static compilation approach that generates ordinary C programs at compile-time that can be readily retargeted to different processors, without including or generating a run-time scheduler. Our method is based on a novel Petri net theoretic approach.","PeriodicalId":179207,"journal":{"name":"Proceedings Design, Automation and Test in Europe","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125139807","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-02-23DOI: 10.1109/DATE.1998.655981
Wonyong Sung, S. Ha
An optimized hardware software cosimulation method based on the backplane approach is presented in this paper. To enhance the performance of cosimulation, efforts are focused on reducing control packets between simulators as well as concurrent execution of simulators without roll-back.
{"title":"Optimized timed hardware software cosimulation without roll-back","authors":"Wonyong Sung, S. Ha","doi":"10.1109/DATE.1998.655981","DOIUrl":"https://doi.org/10.1109/DATE.1998.655981","url":null,"abstract":"An optimized hardware software cosimulation method based on the backplane approach is presented in this paper. To enhance the performance of cosimulation, efforts are focused on reducing control packets between simulators as well as concurrent execution of simulators without roll-back.","PeriodicalId":179207,"journal":{"name":"Proceedings Design, Automation and Test in Europe","volume":"104 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122604934","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-02-23DOI: 10.1109/DATE.1998.655864
M. Mrva
This paper presents a proposal for enabling VHDL to better support reuse and collaboration. The base idea is passing on the adequate information to partners working in an object-oriented hardware design environment. Appropriate subgoals for achieving this are: (a) an optimal mix of necessary abstraction and sufficient precision, (b) a formal description consisting of implementation constraints and knowledge requirements, and (c) the non-formal concept of mutual consideration. Several loans are made from (a) the software domain: Java interfaces, type models, and the request for habitability, (b) the VHDL Annotation Language. This is not an experience report, for the idea of adopting the mentioned software concepts to hardware design is new. It is rather a guided tour to some "panorama views". Although they may not seem related to each other at first glance, they turn out to altogether support a common goal: understanding and communicating VHDL-based designs better.
{"title":"Enhanced reuse and teamwork capabilities for an object-oriented extension of VHDL","authors":"M. Mrva","doi":"10.1109/DATE.1998.655864","DOIUrl":"https://doi.org/10.1109/DATE.1998.655864","url":null,"abstract":"This paper presents a proposal for enabling VHDL to better support reuse and collaboration. The base idea is passing on the adequate information to partners working in an object-oriented hardware design environment. Appropriate subgoals for achieving this are: (a) an optimal mix of necessary abstraction and sufficient precision, (b) a formal description consisting of implementation constraints and knowledge requirements, and (c) the non-formal concept of mutual consideration. Several loans are made from (a) the software domain: Java interfaces, type models, and the request for habitability, (b) the VHDL Annotation Language. This is not an experience report, for the idea of adopting the mentioned software concepts to hardware design is new. It is rather a guided tour to some \"panorama views\". Although they may not seem related to each other at first glance, they turn out to altogether support a common goal: understanding and communicating VHDL-based designs better.","PeriodicalId":179207,"journal":{"name":"Proceedings Design, Automation and Test in Europe","volume":"66 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121062506","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-02-23DOI: 10.1109/DATE.1998.655929
A. Lu, Guenter Stenz, F. Johannes
This paper presents a technology mapping approach for the standard cell technology, which takes into account both gate area and routing area so as to minimize the total chip area after layout. The routing area is estimated using two parameters available at the mapping stage; one is the fanout count of a gate, and the other is the "overlap of fanin level intervals". To estimate the routing area in terms of accurate fanout counts, an algorithm is proposed which solves the problem of dynamic fanout changes in the mapping process. This also enables us to calculate the gate area more accurately. Experimental results show that this approach provides an average reduction of 15% in the final chip area after placement and routing.
{"title":"Technology mapping for minimizing gate and routing area","authors":"A. Lu, Guenter Stenz, F. Johannes","doi":"10.1109/DATE.1998.655929","DOIUrl":"https://doi.org/10.1109/DATE.1998.655929","url":null,"abstract":"This paper presents a technology mapping approach for the standard cell technology, which takes into account both gate area and routing area so as to minimize the total chip area after layout. The routing area is estimated using two parameters available at the mapping stage; one is the fanout count of a gate, and the other is the \"overlap of fanin level intervals\". To estimate the routing area in terms of accurate fanout counts, an algorithm is proposed which solves the problem of dynamic fanout changes in the mapping process. This also enables us to calculate the gate area more accurately. Experimental results show that this approach provides an average reduction of 15% in the final chip area after placement and routing.","PeriodicalId":179207,"journal":{"name":"Proceedings Design, Automation and Test in Europe","volume":"192 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121106022","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-02-23DOI: 10.1109/DATE.1998.655982
J. Montiel-Nelson, V. Armas, R. Sarmiento, A. Núñez
A gallium arsenide automated layout generation system (OLYMPO) for SSI, MSI and LSI circuits used in GaAs VLSI design has been developed. We introduce a full-custom layout style, called RN-based cell model, that it is suited to generate low self-inductance circuit layouts of cells and macrocells. The cell compiler can be used as a cell library builder and it is embedded in a random logic macrocell and an iterative logic array generator. Experimental results demonstrate that OLYMPO generates complex and compact layouts and the synthesis process can be interactively used at the system design level.
{"title":"A cell and macrocell compiler for GaAs VLSI full-custom design","authors":"J. Montiel-Nelson, V. Armas, R. Sarmiento, A. Núñez","doi":"10.1109/DATE.1998.655982","DOIUrl":"https://doi.org/10.1109/DATE.1998.655982","url":null,"abstract":"A gallium arsenide automated layout generation system (OLYMPO) for SSI, MSI and LSI circuits used in GaAs VLSI design has been developed. We introduce a full-custom layout style, called RN-based cell model, that it is suited to generate low self-inductance circuit layouts of cells and macrocells. The cell compiler can be used as a cell library builder and it is embedded in a random logic macrocell and an iterative logic array generator. Experimental results demonstrate that OLYMPO generates complex and compact layouts and the synthesis process can be interactively used at the system design level.","PeriodicalId":179207,"journal":{"name":"Proceedings Design, Automation and Test in Europe","volume":"120 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116386467","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-02-23DOI: 10.1109/DATE.1998.655836
C. Grimm, K. Waldschmidt
The systematic top-down design of mixed-signal systems requires an abstract specification of the intended functions. However, hybrid systems are systems whose parts are specified using different time models. Specifications of hybrid systems are not purely functional as they also contain structural information. The structural information is introduced by partitioning the specification into blocks with a homogeneous time model. This often leads to inefficient implementations. In order to overcome this problem, a homogeneous representation for behavior of hybrid systems-KIR-is introduced. This representation makes it possible to represent behavior in all time models in a common way so that the separation in different modeling styles is no longer necessary. Rules for re-writing the KIR-graph are given which permit the description of the same behaviour in another time model.
混合信号系统的系统自顶向下设计需要对预期功能进行抽象说明。然而，混合系统是使用不同时间模型指定部件的系统。混合系统的规范不纯粹是功能性的，因为它们还包含结构信息。结构信息通过将规范划分为具有同构时间模型的块来引入。这通常会导致低效的实现。为了克服这一问题，引入了混合系统行为的齐次表示- ir -。这种表示使得以一种通用的方式表示所有时间模型中的行为成为可能，这样就不再需要在不同的建模风格中进行分离。给出了改写基尔图的规则，允许在另一个时间模型中描述相同的行为。
{"title":"Repartitioning and technology mapping of electronic hybrid systems","authors":"C. Grimm, K. Waldschmidt","doi":"10.1109/DATE.1998.655836","DOIUrl":"https://doi.org/10.1109/DATE.1998.655836","url":null,"abstract":"The systematic top-down design of mixed-signal systems requires an abstract specification of the intended functions. However, hybrid systems are systems whose parts are specified using different time models. Specifications of hybrid systems are not purely functional as they also contain structural information. The structural information is introduced by partitioning the specification into blocks with a homogeneous time model. This often leads to inefficient implementations. In order to overcome this problem, a homogeneous representation for behavior of hybrid systems-KIR-is introduced. This representation makes it possible to represent behavior in all time models in a common way so that the separation in different modeling styles is no longer necessary. Rules for re-writing the KIR-graph are given which permit the description of the same behaviour in another time model.","PeriodicalId":179207,"journal":{"name":"Proceedings Design, Automation and Test in Europe","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116344208","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-02-23DOI: 10.1109/DATE.1998.655930
Fulvio Corno, P. Prinetto, M. Reorda, M. Violante
Partial scan techniques have been widely accepted as an effective solution to improve sequential ATPG performance while keeping acceptable area and performance overheads. Several techniques for flip-flop selection based on structural analysis have been presented in the literature. In this paper we first propose a new testability measure based on the analysis of the circuit State Transition Graph (STG) through symbolic techniques. We then describe a scan flip flop selection algorithm exploiting this measure. We resort to the identification of several circuit macros to address large sequential circuits. When compared to other techniques, our approach shows good results, especially when it is used to optimize a set of flip-flops previously selected by means of structural analysis.
{"title":"Exploiting symbolic techniques for partial scan flip flop selection","authors":"Fulvio Corno, P. Prinetto, M. Reorda, M. Violante","doi":"10.1109/DATE.1998.655930","DOIUrl":"https://doi.org/10.1109/DATE.1998.655930","url":null,"abstract":"Partial scan techniques have been widely accepted as an effective solution to improve sequential ATPG performance while keeping acceptable area and performance overheads. Several techniques for flip-flop selection based on structural analysis have been presented in the literature. In this paper we first propose a new testability measure based on the analysis of the circuit State Transition Graph (STG) through symbolic techniques. We then describe a scan flip flop selection algorithm exploiting this measure. We resort to the identification of several circuit macros to address large sequential circuits. When compared to other techniques, our approach shows good results, especially when it is used to optimize a set of flip-flops previously selected by means of structural analysis.","PeriodicalId":179207,"journal":{"name":"Proceedings Design, Automation and Test in Europe","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133673005","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-02-23DOI: 10.1109/DATE.1998.655901
C. Chu, D. F. Wong
An interconnect joining a source and a sink is divided into fixed-length uniform-width wire segments, and some adjacent segments have buffers in between. The problem we considered is to simultaneously size the buffers and the segments so that the Elmore delay from the source to the sink is minimized. Previously, no polynomial time algorithm for the problem has been reported in the literature. In this paper, we present a polynomial time algorithm SBWS for the simultaneous buffer and wire sizing problem. SBWS is an iterative algorithm with guaranteed convergence to the optimal solution. It runs in quadratic time and uses constant memory for computation. Also, experimental results show that SBWS is extremely efficient in practice. For example, for an interconnect of 10 000 segments and buffers, the CPU time is only 0.127 s.
{"title":"A polynomial time optimal algorithm for simultaneous buffer and wire sizing","authors":"C. Chu, D. F. Wong","doi":"10.1109/DATE.1998.655901","DOIUrl":"https://doi.org/10.1109/DATE.1998.655901","url":null,"abstract":"An interconnect joining a source and a sink is divided into fixed-length uniform-width wire segments, and some adjacent segments have buffers in between. The problem we considered is to simultaneously size the buffers and the segments so that the Elmore delay from the source to the sink is minimized. Previously, no polynomial time algorithm for the problem has been reported in the literature. In this paper, we present a polynomial time algorithm SBWS for the simultaneous buffer and wire sizing problem. SBWS is an iterative algorithm with guaranteed convergence to the optimal solution. It runs in quadratic time and uses constant memory for computation. Also, experimental results show that SBWS is extremely efficient in practice. For example, for an interconnect of 10 000 segments and buffers, the CPU time is only 0.127 s.","PeriodicalId":179207,"journal":{"name":"Proceedings Design, Automation and Test in Europe","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116560420","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-02-23DOI: 10.1109/DATE.1998.655998
M. Nourani, C. Papachristou
We present a global design for test methodology for testing a core-based system in its entirety. This is achieved by introducing a "bypass" mode for each core by which the data can be transferred from a core input port to the output port without interfering with the core circuitry itself. The interconnections are thoroughly tested since they are used to propagate test data (patterns or signatures) in the system. The system is modeled as a directed weighted graph in which the core accessibility is solved as a shortest path problem.
{"title":"A bypass scheme for core-based system fault testing","authors":"M. Nourani, C. Papachristou","doi":"10.1109/DATE.1998.655998","DOIUrl":"https://doi.org/10.1109/DATE.1998.655998","url":null,"abstract":"We present a global design for test methodology for testing a core-based system in its entirety. This is achieved by introducing a \"bypass\" mode for each core by which the data can be transferred from a core input port to the output port without interfering with the core circuitry itself. The interconnections are thoroughly tested since they are used to propagate test data (patterns or signatures) in the system. The system is modeled as a directed weighted graph in which the core accessibility is solved as a shortest path problem.","PeriodicalId":179207,"journal":{"name":"Proceedings Design, Automation and Test in Europe","volume":"136 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116564355","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-02-23DOI: 10.1109/DATE.1998.655999
C. Metra, M. Favalli, B. Riccò
This paper presents a novel 1-out-of-n checker that, compared to the other implementations up to now presented, features the advantages of: (i) satisfying the TSC or SCD property with respect to all possible internal faults representative of realistic failures; (ii) presenting a single output line; (iii) requiring significantly lower area overhead.
{"title":"Highly testable and compact 1-out-of-n code checker with single output","authors":"C. Metra, M. Favalli, B. Riccò","doi":"10.1109/DATE.1998.655999","DOIUrl":"https://doi.org/10.1109/DATE.1998.655999","url":null,"abstract":"This paper presents a novel 1-out-of-n checker that, compared to the other implementations up to now presented, features the advantages of: (i) satisfying the TSC or SCD property with respect to all possible internal faults representative of realistic failures; (ii) presenting a single output line; (iii) requiring significantly lower area overhead.","PeriodicalId":179207,"journal":{"name":"Proceedings Design, Automation and Test in Europe","volume":"13 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132869729","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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