Pub Date : 1998-02-23DOI: 10.1109/DATE.1998.655914
H. Heineken, Wojciech Maly
Traditional VLSI design objectives are to minimize time-to-first-silicon while maximizing performance. Such objectives lead to designs which are not optimum from a manufacturability perspective. The objective of this paper is to illustrate the above claim by performing performance/manufacturability tradeoff analysis. The basis for such an analysis, in which the relationship between a product's clock frequency and wafer productivity is modeled, is described in detail. New applied yield models are discussed as well.
{"title":"Performance-manufacturability tradeoffs in IC design","authors":"H. Heineken, Wojciech Maly","doi":"10.1109/DATE.1998.655914","DOIUrl":"https://doi.org/10.1109/DATE.1998.655914","url":null,"abstract":"Traditional VLSI design objectives are to minimize time-to-first-silicon while maximizing performance. Such objectives lead to designs which are not optimum from a manufacturability perspective. The objective of this paper is to illustrate the above claim by performing performance/manufacturability tradeoff analysis. The basis for such an analysis, in which the relationship between a product's clock frequency and wafer productivity is modeled, is described in detail. New applied yield models are discussed as well.","PeriodicalId":179207,"journal":{"name":"Proceedings Design, Automation and Test in Europe","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131196458","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-02-23DOI: 10.1109/DATE.1998.655965
J. A. Prieto, A. Rueda, I. Grout, E. Peralías, J. Huertas, A. Richardson
This paper presents an approach towards realistic fault prediction in analog circuits. It exploits the Inductive Fault Analysis (IFA) methodology to generate explicit models able to give the probability of occurrence of faults associated with devices in an analog cell. This information intends to facilitate the integration of design and test phases in the development of an IC since it provides a realistic fault list for simulation before going to the final layout, and also makes possible layout optimization towards what we can call layout level design for testability.
{"title":"An approach to realistic fault prediction and layout design for testability in analog circuits","authors":"J. A. Prieto, A. Rueda, I. Grout, E. Peralías, J. Huertas, A. Richardson","doi":"10.1109/DATE.1998.655965","DOIUrl":"https://doi.org/10.1109/DATE.1998.655965","url":null,"abstract":"This paper presents an approach towards realistic fault prediction in analog circuits. It exploits the Inductive Fault Analysis (IFA) methodology to generate explicit models able to give the probability of occurrence of faults associated with devices in an analog cell. This information intends to facilitate the integration of design and test phases in the development of an IC since it provides a realistic fault list for simulation before going to the final layout, and also makes possible layout optimization towards what we can call layout level design for testability.","PeriodicalId":179207,"journal":{"name":"Proceedings Design, Automation and Test in Europe","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133131007","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-02-23DOI: 10.1109/DATE.1998.655917
I. Pomeranz, S. Reddy
We propose several compaction procedures for synchronous sequential circuits based on test vector restoration. Under a vector restoration procedure, all or most of the test vectors are first omitted from the test sequence. Test vectors are then restored one at a time or in subsequences only as necessary to restore the fault coverage of the original sequence. Techniques to speed-up the restoration process are investigated. These include limiting the test vectors initially omitted from the test sequence, consideration of several faults in parallel during restoration, and the use of a parallel fault simulator.
{"title":"Procedures for static compaction of test sequences for synchronous sequential circuits based on vector restoration","authors":"I. Pomeranz, S. Reddy","doi":"10.1109/DATE.1998.655917","DOIUrl":"https://doi.org/10.1109/DATE.1998.655917","url":null,"abstract":"We propose several compaction procedures for synchronous sequential circuits based on test vector restoration. Under a vector restoration procedure, all or most of the test vectors are first omitted from the test sequence. Test vectors are then restored one at a time or in subsequences only as necessary to restore the fault coverage of the original sequence. Techniques to speed-up the restoration process are investigated. These include limiting the test vectors initially omitted from the test sequence, consideration of several faults in parallel during restoration, and the use of a parallel fault simulator.","PeriodicalId":179207,"journal":{"name":"Proceedings Design, Automation and Test in Europe","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131120355","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-02-23DOI: 10.1109/DATE.1998.655919
Johnny Öberg, A. Hemani, Anshul Kumar
We present a grammar based specification method for hardware synthesis of data communication protocols in which the specification is independent of the port size. Instead, it is used during the synthesis process as a constraint. When the width of the output assignments exceed the chosen output port width, the assignments are split and scheduled over the available states. We present a solution to this problem and results of applying it to some relevant problems.
{"title":"Scheduling of outputs in grammar-based hardware synthesis of data communication protocols","authors":"Johnny Öberg, A. Hemani, Anshul Kumar","doi":"10.1109/DATE.1998.655919","DOIUrl":"https://doi.org/10.1109/DATE.1998.655919","url":null,"abstract":"We present a grammar based specification method for hardware synthesis of data communication protocols in which the specification is independent of the port size. Instead, it is used during the synthesis process as a constraint. When the width of the output assignments exceed the chosen output port width, the assignments are split and scheduled over the available states. We present a solution to this problem and results of applying it to some relevant problems.","PeriodicalId":179207,"journal":{"name":"Proceedings Design, Automation and Test in Europe","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133097352","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-02-23DOI: 10.1109/DATE.1998.655907
V. Székely, M. Rencz
Two different field solver tools have been developed in order to facilitate fast thermal and electro-static simulation of microsystem elements. The /spl mu/S-THERMANAL program is capable of the fast steady-state and dynamic simulation of suspended multilayered microsystem structures. The 2D-SUNRED program is the first version of a general field solver based an an original method, the successive node reduction. SUNRED offers a very fast and accurate substitute of FEM programs for the solution of the Poisson equation. Steady-state and dynamic simulation examples demonstrate the usability of the novel tool.
{"title":"Fast field solvers for thermal and electrostatic analysis","authors":"V. Székely, M. Rencz","doi":"10.1109/DATE.1998.655907","DOIUrl":"https://doi.org/10.1109/DATE.1998.655907","url":null,"abstract":"Two different field solver tools have been developed in order to facilitate fast thermal and electro-static simulation of microsystem elements. The /spl mu/S-THERMANAL program is capable of the fast steady-state and dynamic simulation of suspended multilayered microsystem structures. The 2D-SUNRED program is the first version of a general field solver based an an original method, the successive node reduction. SUNRED offers a very fast and accurate substitute of FEM programs for the solution of the Poisson equation. Steady-state and dynamic simulation examples demonstrate the usability of the novel tool.","PeriodicalId":179207,"journal":{"name":"Proceedings Design, Automation and Test in Europe","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133152970","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-02-23DOI: 10.1109/DATE.1998.655947
S. Vercauteren, D. Verkest, G. D. Jong, Bill Lin
This paper presents a new formal method for the efficient verification of concurrent systems that are modeled using a safe Petri net representation. Our method generalizes upon partial-order methods to explore concurrently enabled conflicting paths simultaneously. We show that our method can achieve an exponential reduction in algorithmic complexity without resorting to an implicit enumeration approach.
{"title":"Efficient verification using generalized partial order analysis","authors":"S. Vercauteren, D. Verkest, G. D. Jong, Bill Lin","doi":"10.1109/DATE.1998.655947","DOIUrl":"https://doi.org/10.1109/DATE.1998.655947","url":null,"abstract":"This paper presents a new formal method for the efficient verification of concurrent systems that are modeled using a safe Petri net representation. Our method generalizes upon partial-order methods to explore concurrently enabled conflicting paths simultaneously. We show that our method can achieve an exponential reduction in algorithmic complexity without resorting to an implicit enumeration approach.","PeriodicalId":179207,"journal":{"name":"Proceedings Design, Automation and Test in Europe","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121402580","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-02-23DOI: 10.1109/DATE.1998.655977
S. Olcoz, A. Castellvi, Maria Garcia, J. A. Gomez
Three navigation tools are presented to statically and interactively analyze soft-cores described in VHDL. These tools ease the adoption of mechanisms to perform reviews and audits procedures similar to those adopted in software development. These navigation tools help to better understand and reuse VHDL soft-cores. The three navigators are integrated in a VHDL-ICE environment to acquire design data management support.
{"title":"Static analysis tools for soft-core reviews and audits","authors":"S. Olcoz, A. Castellvi, Maria Garcia, J. A. Gomez","doi":"10.1109/DATE.1998.655977","DOIUrl":"https://doi.org/10.1109/DATE.1998.655977","url":null,"abstract":"Three navigation tools are presented to statically and interactively analyze soft-cores described in VHDL. These tools ease the adoption of mechanisms to perform reviews and audits procedures similar to those adopted in software development. These navigation tools help to better understand and reuse VHDL soft-cores. The three navigators are integrated in a VHDL-ICE environment to acquire design data management support.","PeriodicalId":179207,"journal":{"name":"Proceedings Design, Automation and Test in Europe","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123386555","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-02-23DOI: 10.1109/DATE.1998.655959
L. Benini, G. Micheli, D. Sciuto, E. Macii, C. Silvano
The power dissipated by system-level buses is the largest contribution to the global power of complex VLSI circuits. Therefore, the minimization of the switching activity at the I/O interfaces can provide significant savings on the overall power budget. This paper presents innovative encoding techniques suitable for minimizing the switching activity of system-level address buses. In particular, the schemes illustrated here target the reduction of the average number of bus line transitions per clock cycle. Experimental results, conducted on address streams generated by a real microprocessor, have demonstrated the effectiveness of the proposed methods.
{"title":"Address bus encoding techniques for system-level power optimization","authors":"L. Benini, G. Micheli, D. Sciuto, E. Macii, C. Silvano","doi":"10.1109/DATE.1998.655959","DOIUrl":"https://doi.org/10.1109/DATE.1998.655959","url":null,"abstract":"The power dissipated by system-level buses is the largest contribution to the global power of complex VLSI circuits. Therefore, the minimization of the switching activity at the I/O interfaces can provide significant savings on the overall power budget. This paper presents innovative encoding techniques suitable for minimizing the switching activity of system-level address buses. In particular, the schemes illustrated here target the reduction of the average number of bus line transitions per clock cycle. Experimental results, conducted on address streams generated by a real microprocessor, have demonstrated the effectiveness of the proposed methods.","PeriodicalId":179207,"journal":{"name":"Proceedings Design, Automation and Test in Europe","volume":"1118 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122933854","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-02-23DOI: 10.1109/DATE.1998.655869
G. Martin
System-chip design which starts at the RTL-level today has hit a plateau of productivity and re-use which can be characterised as a "Silicon Ceiling". Breaking through this plateau and moving to higher and more effective re-use of IP blocks and system-chip architectures demands a move to a new methodology: one in which the best aspects of today's RTL based methods are retained, but complemented by new levels of abstraction and the commensurate tools to allow designers to exploit the productivity inherent in these higher levels of abstraction. In addition, the need to quickly develop design derivatives, and to differentiate products based on standards, requires an increasing use of software IP. This paper describes today's situation, the requirements to move beyond it, and sketch the outlines of near-term possible and practical solutions.
{"title":"Design methodologies for system level IP","authors":"G. Martin","doi":"10.1109/DATE.1998.655869","DOIUrl":"https://doi.org/10.1109/DATE.1998.655869","url":null,"abstract":"System-chip design which starts at the RTL-level today has hit a plateau of productivity and re-use which can be characterised as a \"Silicon Ceiling\". Breaking through this plateau and moving to higher and more effective re-use of IP blocks and system-chip architectures demands a move to a new methodology: one in which the best aspects of today's RTL based methods are retained, but complemented by new levels of abstraction and the commensurate tools to allow designers to exploit the productivity inherent in these higher levels of abstraction. In addition, the need to quickly develop design derivatives, and to differentiate products based on standards, requires an increasing use of software IP. This paper describes today's situation, the requirements to move beyond it, and sketch the outlines of near-term possible and practical solutions.","PeriodicalId":179207,"journal":{"name":"Proceedings Design, Automation and Test in Europe","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125092057","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-02-23DOI: 10.1109/DATE.1998.655885
B. Mesman, M. Strik, A. Timmer, J. V. Meerbergen, J. Jess
Code generation methods for DSP applications are hampered by the combination of tight timing constraints imposed by the performance requirements of DSP algorithms, and resource constraints imposed by a hardware architecture. In this paper we present a method for register binding and instruction scheduling based on the exploitation and analysis of resource and timing constraints. The analysis identifies sequencing constraints between operations additional to the precedence constraints. Without the explicit modeling of these sequencing constraints, a scheduler is often not capable of finding a solution that satisfies the timing, resource and register constraints. The presented approach results in an efficient method of obtaining high quality instruction schedules with low register requirements.
{"title":"A constraint driven approach to loop pipelining and register binding","authors":"B. Mesman, M. Strik, A. Timmer, J. V. Meerbergen, J. Jess","doi":"10.1109/DATE.1998.655885","DOIUrl":"https://doi.org/10.1109/DATE.1998.655885","url":null,"abstract":"Code generation methods for DSP applications are hampered by the combination of tight timing constraints imposed by the performance requirements of DSP algorithms, and resource constraints imposed by a hardware architecture. In this paper we present a method for register binding and instruction scheduling based on the exploitation and analysis of resource and timing constraints. The analysis identifies sequencing constraints between operations additional to the precedence constraints. Without the explicit modeling of these sequencing constraints, a scheduler is often not capable of finding a solution that satisfies the timing, resource and register constraints. The presented approach results in an efficient method of obtaining high quality instruction schedules with low register requirements.","PeriodicalId":179207,"journal":{"name":"Proceedings Design, Automation and Test in Europe","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127428707","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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