Pub Date : 1998-02-23DOI: 10.1109/DATE.1998.655837
E. Moser, N. Mittwollen
After the IEEE ballot accepted the first draft language reference manual for VHDL-AMS (IEEE PAR 1076.1) in October 1997, we now can spend time and effort on applying the new arising methodology to real world problems outside the electronic domain. In automotive engineering we have system design problems dealing with hydraulic or mechanic components and their controlling units, for which we expect a major advantage by introducing unified modelling to all domains. With the Brite/EuRam-Project TOOLSYS (a joined effort of automotive industry and tool makers to apply VHDL-AMS as unified modelling language on mixed-domain applications) we prove the suitability as unified modelling and interchange language for real-world systems and components. First experiments with hydraulic components reveal numerical problems on analog circuit simulators. None of the available strategies for these particularly hard problems are included by the electronic simulator makers. With VHDL-AMS multi-domain modelling seems possible, now we need multi-domain simulation environments.
在1997年10月IEEE投票接受了VHDL-AMS (IEEE PAR 1076.1)的第一份语言参考手册草案之后，我们现在可以花时间和精力将新出现的方法应用于电子领域之外的现实世界问题。在汽车工程中，我们有处理液压或机械部件及其控制单元的系统设计问题，我们希望通过将统一建模引入所有领域来获得主要优势。通过Brite/EuRam-Project TOOLSYS(汽车工业和工具制造商的联合努力，将VHDL-AMS作为混合领域应用的统一建模语言)，我们证明了作为真实世界系统和组件的统一建模和交换语言的适用性。液压元件的首次实验揭示了模拟电路模拟器上的数值问题。对于这些特别困难的问题，电子模拟器制造商没有提供任何可用的策略。有了VHDL-AMS，多域建模似乎成为可能，现在我们需要多域仿真环境。
{"title":"VHDL-AMS: the missing link in system design. Experiments with unified modelling in automotive engineering","authors":"E. Moser, N. Mittwollen","doi":"10.1109/DATE.1998.655837","DOIUrl":"https://doi.org/10.1109/DATE.1998.655837","url":null,"abstract":"After the IEEE ballot accepted the first draft language reference manual for VHDL-AMS (IEEE PAR 1076.1) in October 1997, we now can spend time and effort on applying the new arising methodology to real world problems outside the electronic domain. In automotive engineering we have system design problems dealing with hydraulic or mechanic components and their controlling units, for which we expect a major advantage by introducing unified modelling to all domains. With the Brite/EuRam-Project TOOLSYS (a joined effort of automotive industry and tool makers to apply VHDL-AMS as unified modelling language on mixed-domain applications) we prove the suitability as unified modelling and interchange language for real-world systems and components. First experiments with hydraulic components reveal numerical problems on analog circuit simulators. None of the available strategies for these particularly hard problems are included by the electronic simulator makers. With VHDL-AMS multi-domain modelling seems possible, now we need multi-domain simulation environments.","PeriodicalId":179207,"journal":{"name":"Proceedings Design, Automation and Test in Europe","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129808160","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-02-23DOI: 10.1109/DATE.1998.655996
F. Nicoli
This paper introduces a denotational semantics of a behavioral subset of VHDL. This subset is restricted to basic data types only and does not allow for clauses in wait statement. We consider the full model of time and resolution, we give a precise definition of the simulation mechanism. Easy translation rules from VHDL to Boyer-Moore logic can be derived from that semantics.
{"title":"Denotational semantics of a behavioral subset of VHDL","authors":"F. Nicoli","doi":"10.1109/DATE.1998.655996","DOIUrl":"https://doi.org/10.1109/DATE.1998.655996","url":null,"abstract":"This paper introduces a denotational semantics of a behavioral subset of VHDL. This subset is restricted to basic data types only and does not allow for clauses in wait statement. We consider the full model of time and resolution, we give a precise definition of the simulation mechanism. Easy translation rules from VHDL to Boyer-Moore logic can be derived from that semantics.","PeriodicalId":179207,"journal":{"name":"Proceedings Design, Automation and Test in Europe","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128481968","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-02-23DOI: 10.1109/DATE.1998.655880
I. Page
This paper describes a vision in which future systems consisting of novel hardware and software components are designed and implemented by a single type of professional engineer. That professional has more in common with today's programmer than a hardware designer, although both of these existing bodies of professionals have a strong contribution to make to understanding, defining and bringing about this transformation in product creation.
{"title":"Design of future systems","authors":"I. Page","doi":"10.1109/DATE.1998.655880","DOIUrl":"https://doi.org/10.1109/DATE.1998.655880","url":null,"abstract":"This paper describes a vision in which future systems consisting of novel hardware and software components are designed and implemented by a single type of professional engineer. That professional has more in common with today's programmer than a hardware designer, although both of these existing bodies of professionals have a strong contribution to make to understanding, defining and bringing about this transformation in product creation.","PeriodicalId":179207,"journal":{"name":"Proceedings Design, Automation and Test in Europe","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129944521","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-02-23DOI: 10.1109/DATE.1998.655906
R. Neul, U. Becker, G. Lorenz, P. Schwarz, Jürgen Haase, S. Wünsche
For MEMS devices modern technologies are used to integrate very complex components and subsystems closely together. Due to mixed-domain problems as well as the occurring interactions between the closely coupled system components the design is a sophisticated process. The interactions between the MEMS components have to be analysed by system simulation already in an early design stage. In this paper a modeling approach is introduced that enables the incorporation of mechanical microsystem components into the system simulation using network and system simulators like SABER. The approach is based on multi-terminal models of basic mechanical elements and their composition to more complex microsystems. First results for a micromechanical resonator are presented.
{"title":"A modeling approach to include mechanical microsystem components into the system simulation","authors":"R. Neul, U. Becker, G. Lorenz, P. Schwarz, Jürgen Haase, S. Wünsche","doi":"10.1109/DATE.1998.655906","DOIUrl":"https://doi.org/10.1109/DATE.1998.655906","url":null,"abstract":"For MEMS devices modern technologies are used to integrate very complex components and subsystems closely together. Due to mixed-domain problems as well as the occurring interactions between the closely coupled system components the design is a sophisticated process. The interactions between the MEMS components have to be analysed by system simulation already in an early design stage. In this paper a modeling approach is introduced that enables the incorporation of mechanical microsystem components into the system simulation using network and system simulators like SABER. The approach is based on multi-terminal models of basic mechanical elements and their composition to more complex microsystems. First results for a micromechanical resonator are presented.","PeriodicalId":179207,"journal":{"name":"Proceedings Design, Automation and Test in Europe","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132854999","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-02-23DOI: 10.1109/DATE.1998.655890
T. Adler, Juergen Schaeuble
We present an interactive two layer router integrated in an analog IC design environment used in an SDL (schematic driven layout) design flow. Special features are its customizability, the treatment of arbitrary polygons and an advanced handling of source/target polygons in order to avoid net internal design rule violations during connection phase. A global routing algorithm is used to split the route into separate parts each routable in a single layer. After via placement a specialized maze router performs the advanced single layer routes in 90 or 45 degree mode. The resulting route can be modified by interactive via movement and rerouting of obsolete partial routes.
{"title":"An interactive router for analog IC design","authors":"T. Adler, Juergen Schaeuble","doi":"10.1109/DATE.1998.655890","DOIUrl":"https://doi.org/10.1109/DATE.1998.655890","url":null,"abstract":"We present an interactive two layer router integrated in an analog IC design environment used in an SDL (schematic driven layout) design flow. Special features are its customizability, the treatment of arbitrary polygons and an advanced handling of source/target polygons in order to avoid net internal design rule violations during connection phase. A global routing algorithm is used to split the route into separate parts each routable in a single layer. After via placement a specialized maze router performs the advanced single layer routes in 90 or 45 degree mode. The resulting route can be modified by interactive via movement and rerouting of obsolete partial routes.","PeriodicalId":179207,"journal":{"name":"Proceedings Design, Automation and Test in Europe","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114102541","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-02-23DOI: 10.1109/DATE.1998.655916
M. Hsiao, S. Chakradhar
We extend the subsequence removal technique to provide significantly higher static compaction for sequential circuits. We show that state relaxation techniques can be used to identify more or larger cycles in a test set. State relaxation creates more opportunities for subsequence removal and hence, results in better compaction. Relaxation of a state is possible since not all memory elements in a finite state machine have to be specified for a state transition. The proposed technique has several advantages: (1) test sets that could not be compacted by existing subsequence removal techniques can now be compacted, (2) the size of cycles in a test set can be significantly increased by state relaxation and removal of the larger sized cycles leads to better compaction, (3) only two fault simulation passes are required as compared to trial and re-trial methods that require multiple fault simulation passes, and (4) significantly higher compaction is achieved in short execution times as compared to known subsequence removal methods, Experiments on ISCAS89 sequential benchmark circuits and several synthesized circuits show that the proposed technique consistently results in significantly higher compaction in short execution times.
{"title":"State relaxation based subsequence removal for fast static compaction in sequential circuits","authors":"M. Hsiao, S. Chakradhar","doi":"10.1109/DATE.1998.655916","DOIUrl":"https://doi.org/10.1109/DATE.1998.655916","url":null,"abstract":"We extend the subsequence removal technique to provide significantly higher static compaction for sequential circuits. We show that state relaxation techniques can be used to identify more or larger cycles in a test set. State relaxation creates more opportunities for subsequence removal and hence, results in better compaction. Relaxation of a state is possible since not all memory elements in a finite state machine have to be specified for a state transition. The proposed technique has several advantages: (1) test sets that could not be compacted by existing subsequence removal techniques can now be compacted, (2) the size of cycles in a test set can be significantly increased by state relaxation and removal of the larger sized cycles leads to better compaction, (3) only two fault simulation passes are required as compared to trial and re-trial methods that require multiple fault simulation passes, and (4) significantly higher compaction is achieved in short execution times as compared to known subsequence removal methods, Experiments on ISCAS89 sequential benchmark circuits and several synthesized circuits show that the proposed technique consistently results in significantly higher compaction in short execution times.","PeriodicalId":179207,"journal":{"name":"Proceedings Design, Automation and Test in Europe","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121222420","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-02-23DOI: 10.1109/DATE.1998.655945
A. Bogliolo, L. Benini, G. Micheli
We propose a new approach to RT-level power modeling for combinational macros, that does not require simulation-based characterization. A pattern-dependent power model for a macro is analytically constructed using only structural information about its gate-level implementation. The approach has three main advantages over traditional techniques: (i) it provides models whose accuracy does not depend on input statistics, (ii) it offers a wide range of tradeoff between accuracy and complexity, and (iii) it enables the construction of pattern-dependent conservative upper bounds.
{"title":"Characterization-free behavioral power modeling","authors":"A. Bogliolo, L. Benini, G. Micheli","doi":"10.1109/DATE.1998.655945","DOIUrl":"https://doi.org/10.1109/DATE.1998.655945","url":null,"abstract":"We propose a new approach to RT-level power modeling for combinational macros, that does not require simulation-based characterization. A pattern-dependent power model for a macro is analytically constructed using only structural information about its gate-level implementation. The approach has three main advantages over traditional techniques: (i) it provides models whose accuracy does not depend on input statistics, (ii) it offers a wide range of tradeoff between accuracy and complexity, and (iii) it enables the construction of pattern-dependent conservative upper bounds.","PeriodicalId":179207,"journal":{"name":"Proceedings Design, Automation and Test in Europe","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122676749","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-02-23DOI: 10.1109/DATE.1998.655990
A. Prihozhy
This paper presents an approach to generating asynchronous schedules of various concurrency levels and describes novel net-based scheduling and allocation optimization techniques for asynchronous high-level synthesis. The asynchronous schedules are optimized through using the sets of concurrent variable and statement pairs. Experimental results and a comparison of the net-based techniques with the best sequential scheduling and allocation techniques are presented.
{"title":"Asynchronous scheduling and allocation","authors":"A. Prihozhy","doi":"10.1109/DATE.1998.655990","DOIUrl":"https://doi.org/10.1109/DATE.1998.655990","url":null,"abstract":"This paper presents an approach to generating asynchronous schedules of various concurrency levels and describes novel net-based scheduling and allocation optimization techniques for asynchronous high-level synthesis. The asynchronous schedules are optimized through using the sets of concurrent variable and statement pairs. Experimental results and a comparison of the net-based techniques with the best sequential scheduling and allocation techniques are presented.","PeriodicalId":179207,"journal":{"name":"Proceedings Design, Automation and Test in Europe","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127671987","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-02-23DOI: 10.1109/DATE.1998.655927
L. Hedrich, E. Barke
This paper presents an approach to formal verification of linear analog circuits with parameter tolerances. The method proves that an actual circuit fulfils a specification in a given frequency interval for all parameter variations. It is based on a curvature driven bound computation for value sets using interval arithmetic. Some examples demonstrate the feasibility of this approach.
{"title":"A formal approach to verification of linear analog circuits with parameter tolerances","authors":"L. Hedrich, E. Barke","doi":"10.1109/DATE.1998.655927","DOIUrl":"https://doi.org/10.1109/DATE.1998.655927","url":null,"abstract":"This paper presents an approach to formal verification of linear analog circuits with parameter tolerances. The method proves that an actual circuit fulfils a specification in a given frequency interval for all parameter variations. It is based on a curvature driven bound computation for value sets using interval arithmetic. Some examples demonstrate the feasibility of this approach.","PeriodicalId":179207,"journal":{"name":"Proceedings Design, Automation and Test in Europe","volume":"107 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134503062","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-02-23DOI: 10.1109/DATE.1998.655997
J. Mendias, R. Hermida
This paper presents a formal synthesis system which delegates the design space exploration to non-formal, and potentially incorrect, high level synthesis tools. With a quadratic complexity, our system obtains either a truly correct-by-construction design, since the formal design process constitutes itself the verification process, or demonstrates that the solution found by the conventional tool was incorrect.
{"title":"Correct high-level synthesis: a formal perspective","authors":"J. Mendias, R. Hermida","doi":"10.1109/DATE.1998.655997","DOIUrl":"https://doi.org/10.1109/DATE.1998.655997","url":null,"abstract":"This paper presents a formal synthesis system which delegates the design space exploration to non-formal, and potentially incorrect, high level synthesis tools. With a quadratic complexity, our system obtains either a truly correct-by-construction design, since the formal design process constitutes itself the verification process, or demonstrates that the solution found by the conventional tool was incorrect.","PeriodicalId":179207,"journal":{"name":"Proceedings Design, Automation and Test in Europe","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134267315","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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