Pub Date : 1998-02-23DOI: 10.1109/DATE.1998.655941
Christoph Scholl
Functional decomposition is an important technique in logic synthesis, especially for the design of lookup table based FPGA architectures. We present a method for functional decomposition with a novel concept for the exploitation of don't cares thereby combining two essential goals. The minimization of the number of decomposition functions in the current decomposition step and the extraction of common subfunctions for multi-output Boolean functions. The exploitation of symmetries of Boolean functions plays an important role in our algorithm as a means to minimize the number of decomposition functions not only for the current decomposition step but also for the (recursive) decomposition algorithm as a whole. Experimental results prove the effectiveness of our approach.
{"title":"Multi-output functional decomposition with exploitation of don't cares","authors":"Christoph Scholl","doi":"10.1109/DATE.1998.655941","DOIUrl":"https://doi.org/10.1109/DATE.1998.655941","url":null,"abstract":"Functional decomposition is an important technique in logic synthesis, especially for the design of lookup table based FPGA architectures. We present a method for functional decomposition with a novel concept for the exploitation of don't cares thereby combining two essential goals. The minimization of the number of decomposition functions in the current decomposition step and the extraction of common subfunctions for multi-output Boolean functions. The exploitation of symmetries of Boolean functions plays an important role in our algorithm as a means to minimize the number of decomposition functions not only for the current decomposition step but also for the (recursive) decomposition algorithm as a whole. Experimental results prove the effectiveness of our approach.","PeriodicalId":179207,"journal":{"name":"Proceedings Design, Automation and Test in Europe","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134473937","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-02-23DOI: 10.1109/DATE.1998.655838
I. Parulkar, S. Gupta, M. Breuer
Built-in self-test (BIST) techniques modify functional hardware to give a data path the capability to test itself. The modification of data path registers into registers (BIST resources) that can generate pseudo-random test patterns and/or compress test responses, incurs an area overhead penalty. We show how scheduling and module assignment in high-level synthesis affect BIST resource requirements of a data path. A scheduling and module assignment procedure is presented that produces schedules which, when used to synthesize data paths, result in a significant reduction in BIST area overhead and hence total area.
{"title":"Scheduling and module assignment for reducing BIST resources","authors":"I. Parulkar, S. Gupta, M. Breuer","doi":"10.1109/DATE.1998.655838","DOIUrl":"https://doi.org/10.1109/DATE.1998.655838","url":null,"abstract":"Built-in self-test (BIST) techniques modify functional hardware to give a data path the capability to test itself. The modification of data path registers into registers (BIST resources) that can generate pseudo-random test patterns and/or compress test responses, incurs an area overhead penalty. We show how scheduling and module assignment in high-level synthesis affect BIST resource requirements of a data path. A scheduling and module assignment procedure is presented that produces schedules which, when used to synthesize data paths, result in a significant reduction in BIST area overhead and hence total area.","PeriodicalId":179207,"journal":{"name":"Proceedings Design, Automation and Test in Europe","volume":"52 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134643099","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-02-23DOI: 10.1109/DATE.1998.655944
Fabrizio Ferrandi, F. Fummi, E. Macii, M. Poncino
This paper presents a methodology for power estimation of designs described at the behavioral-level as the interconnection of functional modules. The input/output behavior of each module is implicitly stored using BDDs, and the power consumed by the network is estimated using a novel and accurate entropy-based approach. As a demonstration example, we have used the proposed power estimation technique to evaluate and compare the effects of some architectural transformations applied to a reference design specification on the power dissipation of the corresponding implementations.
{"title":"Power estimation of behavioral descriptions","authors":"Fabrizio Ferrandi, F. Fummi, E. Macii, M. Poncino","doi":"10.1109/DATE.1998.655944","DOIUrl":"https://doi.org/10.1109/DATE.1998.655944","url":null,"abstract":"This paper presents a methodology for power estimation of designs described at the behavioral-level as the interconnection of functional modules. The input/output behavior of each module is implicitly stored using BDDs, and the power consumed by the network is estimated using a novel and accurate entropy-based approach. As a demonstration example, we have used the proposed power estimation technique to evaluate and compare the effects of some architectural transformations applied to a reference design specification on the power dissipation of the corresponding implementations.","PeriodicalId":179207,"journal":{"name":"Proceedings Design, Automation and Test in Europe","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133884364","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-02-23DOI: 10.1109/DATE.1998.655930
Fulvio Corno, P. Prinetto, M. Reorda, M. Violante
Partial scan techniques have been widely accepted as an effective solution to improve sequential ATPG performance while keeping acceptable area and performance overheads. Several techniques for flip-flop selection based on structural analysis have been presented in the literature. In this paper we first propose a new testability measure based on the analysis of the circuit State Transition Graph (STG) through symbolic techniques. We then describe a scan flip flop selection algorithm exploiting this measure. We resort to the identification of several circuit macros to address large sequential circuits. When compared to other techniques, our approach shows good results, especially when it is used to optimize a set of flip-flops previously selected by means of structural analysis.
{"title":"Exploiting symbolic techniques for partial scan flip flop selection","authors":"Fulvio Corno, P. Prinetto, M. Reorda, M. Violante","doi":"10.1109/DATE.1998.655930","DOIUrl":"https://doi.org/10.1109/DATE.1998.655930","url":null,"abstract":"Partial scan techniques have been widely accepted as an effective solution to improve sequential ATPG performance while keeping acceptable area and performance overheads. Several techniques for flip-flop selection based on structural analysis have been presented in the literature. In this paper we first propose a new testability measure based on the analysis of the circuit State Transition Graph (STG) through symbolic techniques. We then describe a scan flip flop selection algorithm exploiting this measure. We resort to the identification of several circuit macros to address large sequential circuits. When compared to other techniques, our approach shows good results, especially when it is used to optimize a set of flip-flops previously selected by means of structural analysis.","PeriodicalId":179207,"journal":{"name":"Proceedings Design, Automation and Test in Europe","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133673005","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-02-23DOI: 10.1109/DATE.1998.655999
C. Metra, M. Favalli, B. Riccò
This paper presents a novel 1-out-of-n checker that, compared to the other implementations up to now presented, features the advantages of: (i) satisfying the TSC or SCD property with respect to all possible internal faults representative of realistic failures; (ii) presenting a single output line; (iii) requiring significantly lower area overhead.
{"title":"Highly testable and compact 1-out-of-n code checker with single output","authors":"C. Metra, M. Favalli, B. Riccò","doi":"10.1109/DATE.1998.655999","DOIUrl":"https://doi.org/10.1109/DATE.1998.655999","url":null,"abstract":"This paper presents a novel 1-out-of-n checker that, compared to the other implementations up to now presented, features the advantages of: (i) satisfying the TSC or SCD property with respect to all possible internal faults representative of realistic failures; (ii) presenting a single output line; (iii) requiring significantly lower area overhead.","PeriodicalId":179207,"journal":{"name":"Proceedings Design, Automation and Test in Europe","volume":"13 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132869729","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-02-23DOI: 10.1109/DATE.1998.655912
Wojciech Maly, H. Heineken, J. Khare, P. Nag
This paper proposes a vision for a new research domain emerging on the interface between design and manufacturing of VLSI circuits. The key objective of this domain is the minimization of the mismatch between design and manufacturing which is rapidly growing with the increase in complexity of VLSI designs and IC technologies. This broad objective is partitioned into a number of specific tasks. Often, one of the most important tasks is the extraction of VLSI design attributes that may be relevant from a manufacturing efficiency standpoint. The second task is yield analysis performed to detect process and design attributes responsible for inadequate yield. This paper postulates both, an overall change in the design-manufacturing interface, as well as a methodology to address the growing design-manufacturing mismatch. Attributes of a number of tools needed for this purpose are discussed as well.
{"title":"Design-manufacturing interface. I. Vision [VLSI]","authors":"Wojciech Maly, H. Heineken, J. Khare, P. Nag","doi":"10.1109/DATE.1998.655912","DOIUrl":"https://doi.org/10.1109/DATE.1998.655912","url":null,"abstract":"This paper proposes a vision for a new research domain emerging on the interface between design and manufacturing of VLSI circuits. The key objective of this domain is the minimization of the mismatch between design and manufacturing which is rapidly growing with the increase in complexity of VLSI designs and IC technologies. This broad objective is partitioned into a number of specific tasks. Often, one of the most important tasks is the extraction of VLSI design attributes that may be relevant from a manufacturing efficiency standpoint. The second task is yield analysis performed to detect process and design attributes responsible for inadequate yield. This paper postulates both, an overall change in the design-manufacturing interface, as well as a methodology to address the growing design-manufacturing mismatch. Attributes of a number of tools needed for this purpose are discussed as well.","PeriodicalId":179207,"journal":{"name":"Proceedings Design, Automation and Test in Europe","volume":"56 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113993025","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-02-23DOI: 10.1109/DATE.1998.655864
M. Mrva
This paper presents a proposal for enabling VHDL to better support reuse and collaboration. The base idea is passing on the adequate information to partners working in an object-oriented hardware design environment. Appropriate subgoals for achieving this are: (a) an optimal mix of necessary abstraction and sufficient precision, (b) a formal description consisting of implementation constraints and knowledge requirements, and (c) the non-formal concept of mutual consideration. Several loans are made from (a) the software domain: Java interfaces, type models, and the request for habitability, (b) the VHDL Annotation Language. This is not an experience report, for the idea of adopting the mentioned software concepts to hardware design is new. It is rather a guided tour to some "panorama views". Although they may not seem related to each other at first glance, they turn out to altogether support a common goal: understanding and communicating VHDL-based designs better.
{"title":"Enhanced reuse and teamwork capabilities for an object-oriented extension of VHDL","authors":"M. Mrva","doi":"10.1109/DATE.1998.655864","DOIUrl":"https://doi.org/10.1109/DATE.1998.655864","url":null,"abstract":"This paper presents a proposal for enabling VHDL to better support reuse and collaboration. The base idea is passing on the adequate information to partners working in an object-oriented hardware design environment. Appropriate subgoals for achieving this are: (a) an optimal mix of necessary abstraction and sufficient precision, (b) a formal description consisting of implementation constraints and knowledge requirements, and (c) the non-formal concept of mutual consideration. Several loans are made from (a) the software domain: Java interfaces, type models, and the request for habitability, (b) the VHDL Annotation Language. This is not an experience report, for the idea of adopting the mentioned software concepts to hardware design is new. It is rather a guided tour to some \"panorama views\". Although they may not seem related to each other at first glance, they turn out to altogether support a common goal: understanding and communicating VHDL-based designs better.","PeriodicalId":179207,"journal":{"name":"Proceedings Design, Automation and Test in Europe","volume":"66 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121062506","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-02-23DOI: 10.1109/DATE.1998.655929
A. Lu, Guenter Stenz, F. Johannes
This paper presents a technology mapping approach for the standard cell technology, which takes into account both gate area and routing area so as to minimize the total chip area after layout. The routing area is estimated using two parameters available at the mapping stage; one is the fanout count of a gate, and the other is the "overlap of fanin level intervals". To estimate the routing area in terms of accurate fanout counts, an algorithm is proposed which solves the problem of dynamic fanout changes in the mapping process. This also enables us to calculate the gate area more accurately. Experimental results show that this approach provides an average reduction of 15% in the final chip area after placement and routing.
{"title":"Technology mapping for minimizing gate and routing area","authors":"A. Lu, Guenter Stenz, F. Johannes","doi":"10.1109/DATE.1998.655929","DOIUrl":"https://doi.org/10.1109/DATE.1998.655929","url":null,"abstract":"This paper presents a technology mapping approach for the standard cell technology, which takes into account both gate area and routing area so as to minimize the total chip area after layout. The routing area is estimated using two parameters available at the mapping stage; one is the fanout count of a gate, and the other is the \"overlap of fanin level intervals\". To estimate the routing area in terms of accurate fanout counts, an algorithm is proposed which solves the problem of dynamic fanout changes in the mapping process. This also enables us to calculate the gate area more accurately. Experimental results show that this approach provides an average reduction of 15% in the final chip area after placement and routing.","PeriodicalId":179207,"journal":{"name":"Proceedings Design, Automation and Test in Europe","volume":"192 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121106022","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-02-23DOI: 10.1109/DATE.1998.655901
C. Chu, D. F. Wong
An interconnect joining a source and a sink is divided into fixed-length uniform-width wire segments, and some adjacent segments have buffers in between. The problem we considered is to simultaneously size the buffers and the segments so that the Elmore delay from the source to the sink is minimized. Previously, no polynomial time algorithm for the problem has been reported in the literature. In this paper, we present a polynomial time algorithm SBWS for the simultaneous buffer and wire sizing problem. SBWS is an iterative algorithm with guaranteed convergence to the optimal solution. It runs in quadratic time and uses constant memory for computation. Also, experimental results show that SBWS is extremely efficient in practice. For example, for an interconnect of 10 000 segments and buffers, the CPU time is only 0.127 s.
{"title":"A polynomial time optimal algorithm for simultaneous buffer and wire sizing","authors":"C. Chu, D. F. Wong","doi":"10.1109/DATE.1998.655901","DOIUrl":"https://doi.org/10.1109/DATE.1998.655901","url":null,"abstract":"An interconnect joining a source and a sink is divided into fixed-length uniform-width wire segments, and some adjacent segments have buffers in between. The problem we considered is to simultaneously size the buffers and the segments so that the Elmore delay from the source to the sink is minimized. Previously, no polynomial time algorithm for the problem has been reported in the literature. In this paper, we present a polynomial time algorithm SBWS for the simultaneous buffer and wire sizing problem. SBWS is an iterative algorithm with guaranteed convergence to the optimal solution. It runs in quadratic time and uses constant memory for computation. Also, experimental results show that SBWS is extremely efficient in practice. For example, for an interconnect of 10 000 segments and buffers, the CPU time is only 0.127 s.","PeriodicalId":179207,"journal":{"name":"Proceedings Design, Automation and Test in Europe","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116560420","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-02-23DOI: 10.1109/DATE.1998.655998
M. Nourani, C. Papachristou
We present a global design for test methodology for testing a core-based system in its entirety. This is achieved by introducing a "bypass" mode for each core by which the data can be transferred from a core input port to the output port without interfering with the core circuitry itself. The interconnections are thoroughly tested since they are used to propagate test data (patterns or signatures) in the system. The system is modeled as a directed weighted graph in which the core accessibility is solved as a shortest path problem.
{"title":"A bypass scheme for core-based system fault testing","authors":"M. Nourani, C. Papachristou","doi":"10.1109/DATE.1998.655998","DOIUrl":"https://doi.org/10.1109/DATE.1998.655998","url":null,"abstract":"We present a global design for test methodology for testing a core-based system in its entirety. This is achieved by introducing a \"bypass\" mode for each core by which the data can be transferred from a core input port to the output port without interfering with the core circuitry itself. The interconnections are thoroughly tested since they are used to propagate test data (patterns or signatures) in the system. The system is modeled as a directed weighted graph in which the core accessibility is solved as a shortest path problem.","PeriodicalId":179207,"journal":{"name":"Proceedings Design, Automation and Test in Europe","volume":"136 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116564355","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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