Pub Date : 1998-02-23DOI: 10.1109/DATE.1998.655941
Christoph Scholl
Functional decomposition is an important technique in logic synthesis, especially for the design of lookup table based FPGA architectures. We present a method for functional decomposition with a novel concept for the exploitation of don't cares thereby combining two essential goals. The minimization of the number of decomposition functions in the current decomposition step and the extraction of common subfunctions for multi-output Boolean functions. The exploitation of symmetries of Boolean functions plays an important role in our algorithm as a means to minimize the number of decomposition functions not only for the current decomposition step but also for the (recursive) decomposition algorithm as a whole. Experimental results prove the effectiveness of our approach.
{"title":"Multi-output functional decomposition with exploitation of don't cares","authors":"Christoph Scholl","doi":"10.1109/DATE.1998.655941","DOIUrl":"https://doi.org/10.1109/DATE.1998.655941","url":null,"abstract":"Functional decomposition is an important technique in logic synthesis, especially for the design of lookup table based FPGA architectures. We present a method for functional decomposition with a novel concept for the exploitation of don't cares thereby combining two essential goals. The minimization of the number of decomposition functions in the current decomposition step and the extraction of common subfunctions for multi-output Boolean functions. The exploitation of symmetries of Boolean functions plays an important role in our algorithm as a means to minimize the number of decomposition functions not only for the current decomposition step but also for the (recursive) decomposition algorithm as a whole. Experimental results prove the effectiveness of our approach.","PeriodicalId":179207,"journal":{"name":"Proceedings Design, Automation and Test in Europe","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134473937","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-02-23DOI: 10.1109/DATE.1998.655838
I. Parulkar, S. Gupta, M. Breuer
Built-in self-test (BIST) techniques modify functional hardware to give a data path the capability to test itself. The modification of data path registers into registers (BIST resources) that can generate pseudo-random test patterns and/or compress test responses, incurs an area overhead penalty. We show how scheduling and module assignment in high-level synthesis affect BIST resource requirements of a data path. A scheduling and module assignment procedure is presented that produces schedules which, when used to synthesize data paths, result in a significant reduction in BIST area overhead and hence total area.
{"title":"Scheduling and module assignment for reducing BIST resources","authors":"I. Parulkar, S. Gupta, M. Breuer","doi":"10.1109/DATE.1998.655838","DOIUrl":"https://doi.org/10.1109/DATE.1998.655838","url":null,"abstract":"Built-in self-test (BIST) techniques modify functional hardware to give a data path the capability to test itself. The modification of data path registers into registers (BIST resources) that can generate pseudo-random test patterns and/or compress test responses, incurs an area overhead penalty. We show how scheduling and module assignment in high-level synthesis affect BIST resource requirements of a data path. A scheduling and module assignment procedure is presented that produces schedules which, when used to synthesize data paths, result in a significant reduction in BIST area overhead and hence total area.","PeriodicalId":179207,"journal":{"name":"Proceedings Design, Automation and Test in Europe","volume":"52 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134643099","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-02-23DOI: 10.1109/DATE.1998.655912
Wojciech Maly, H. Heineken, J. Khare, P. Nag
This paper proposes a vision for a new research domain emerging on the interface between design and manufacturing of VLSI circuits. The key objective of this domain is the minimization of the mismatch between design and manufacturing which is rapidly growing with the increase in complexity of VLSI designs and IC technologies. This broad objective is partitioned into a number of specific tasks. Often, one of the most important tasks is the extraction of VLSI design attributes that may be relevant from a manufacturing efficiency standpoint. The second task is yield analysis performed to detect process and design attributes responsible for inadequate yield. This paper postulates both, an overall change in the design-manufacturing interface, as well as a methodology to address the growing design-manufacturing mismatch. Attributes of a number of tools needed for this purpose are discussed as well.
{"title":"Design-manufacturing interface. I. Vision [VLSI]","authors":"Wojciech Maly, H. Heineken, J. Khare, P. Nag","doi":"10.1109/DATE.1998.655912","DOIUrl":"https://doi.org/10.1109/DATE.1998.655912","url":null,"abstract":"This paper proposes a vision for a new research domain emerging on the interface between design and manufacturing of VLSI circuits. The key objective of this domain is the minimization of the mismatch between design and manufacturing which is rapidly growing with the increase in complexity of VLSI designs and IC technologies. This broad objective is partitioned into a number of specific tasks. Often, one of the most important tasks is the extraction of VLSI design attributes that may be relevant from a manufacturing efficiency standpoint. The second task is yield analysis performed to detect process and design attributes responsible for inadequate yield. This paper postulates both, an overall change in the design-manufacturing interface, as well as a methodology to address the growing design-manufacturing mismatch. Attributes of a number of tools needed for this purpose are discussed as well.","PeriodicalId":179207,"journal":{"name":"Proceedings Design, Automation and Test in Europe","volume":"56 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113993025","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-02-23DOI: 10.1109/DATE.1998.655849
J. Coppens, D. Al-Khalili, C. Rozon
This paper presents an analysis process targeted for the verification of fault secure systems during their design phase. This process deals with a realistic set of micro-defects at the device level which are mapped into mutant and saboteur based VHDL fault models in the form of logical and/or performance degradation faults. Automatic defect injection and simulation are performed through a VHDL test bench. Extensive post processing analysis is performed to determine defect coverage, figure of merit for fault secureness, and MTTF.
{"title":"VHDL modelling and analysis of fault secure systems","authors":"J. Coppens, D. Al-Khalili, C. Rozon","doi":"10.1109/DATE.1998.655849","DOIUrl":"https://doi.org/10.1109/DATE.1998.655849","url":null,"abstract":"This paper presents an analysis process targeted for the verification of fault secure systems during their design phase. This process deals with a realistic set of micro-defects at the device level which are mapped into mutant and saboteur based VHDL fault models in the form of logical and/or performance degradation faults. Automatic defect injection and simulation are performed through a VHDL test bench. Extensive post processing analysis is performed to determine defect coverage, figure of merit for fault secureness, and MTTF.","PeriodicalId":179207,"journal":{"name":"Proceedings Design, Automation and Test in Europe","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114187427","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-02-23DOI: 10.1109/DATE.1998.655975
T. Müller-Wipperfürth, R. Hagelauer
This paper discusses issues of graphical modelling of Finite State Machines with Datapath (FSMDs). Tools supporting the graphical entry of state based systems are usable by intuition, but need to be based on an exact definition of semantics of graphical elements. This paper proposes to define semantics of graphical models based on the hardware description language VHDL.
{"title":"Graphical entry of FSMDs revisited: putting graphical models on a solid base","authors":"T. Müller-Wipperfürth, R. Hagelauer","doi":"10.1109/DATE.1998.655975","DOIUrl":"https://doi.org/10.1109/DATE.1998.655975","url":null,"abstract":"This paper discusses issues of graphical modelling of Finite State Machines with Datapath (FSMDs). Tools supporting the graphical entry of state based systems are usable by intuition, but need to be based on an exact definition of semantics of graphical elements. This paper proposes to define semantics of graphical models based on the hardware description language VHDL.","PeriodicalId":179207,"journal":{"name":"Proceedings Design, Automation and Test in Europe","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114652694","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-02-23DOI: 10.1109/DATE.1998.655872
S. Olcoz, Lorenzo Ayuda, Ivan Izaguirre, O. Peñalba
A new set of tools for teamwork, organization units, workspace and build management of VHDL-based reusable components, organized in libraries, accessible through an heterogeneous and distributed environment is presented. These tools support the collaborative and distributed development of systems-on-a-chip reusing VHDL components available through the intranets and the Internet. They must be used as a complementary support to the design tools (simulation, synthesis, etc.) already available in the market to enhance productivity, facilitating maintenance, improving efficiency and interoperability, and finally, capitalizing on the IP library components investment.
{"title":"VHDL teamwork, organization units and workspace management","authors":"S. Olcoz, Lorenzo Ayuda, Ivan Izaguirre, O. Peñalba","doi":"10.1109/DATE.1998.655872","DOIUrl":"https://doi.org/10.1109/DATE.1998.655872","url":null,"abstract":"A new set of tools for teamwork, organization units, workspace and build management of VHDL-based reusable components, organized in libraries, accessible through an heterogeneous and distributed environment is presented. These tools support the collaborative and distributed development of systems-on-a-chip reusing VHDL components available through the intranets and the Internet. They must be used as a complementary support to the design tools (simulation, synthesis, etc.) already available in the market to enhance productivity, facilitating maintenance, improving efficiency and interoperability, and finally, capitalizing on the IP library components investment.","PeriodicalId":179207,"journal":{"name":"Proceedings Design, Automation and Test in Europe","volume":"101 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114427065","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-02-23DOI: 10.1109/DATE.1998.655992
Subhasish Subhasish, H. Arts, P. Banerjee
This paper describes algebraic techniques that target low power consumption. A unique power cost function based on decomposed factored form representation of a Boolean expression is introduced to guide the structural transformations. Circuits synthesized by the SIS and POSE consume 54.5% and 10.4% more power than that obtained by our tool respectively.
{"title":"PowerShake: a low power driven clustering and factoring methodology for Boolean expressions","authors":"Subhasish Subhasish, H. Arts, P. Banerjee","doi":"10.1109/DATE.1998.655992","DOIUrl":"https://doi.org/10.1109/DATE.1998.655992","url":null,"abstract":"This paper describes algebraic techniques that target low power consumption. A unique power cost function based on decomposed factored form representation of a Boolean expression is introduced to guide the structural transformations. Circuits synthesized by the SIS and POSE consume 54.5% and 10.4% more power than that obtained by our tool respectively.","PeriodicalId":179207,"journal":{"name":"Proceedings Design, Automation and Test in Europe","volume":"30 5","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114480487","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-02-23DOI: 10.1109/DATE.1998.655841
C. Metra, M. Renovell, G. Mojoli, J. Portal, S. Pastore, J. Figueras, Y. Zorian, D. Salvi, G. Sechi
This paper presents a novel technique for testing Field Programmable Gate Arrays (FPGAs), suitable for use in the case of frequent FPGA reuse and rapid dynamic modifiability of the implemented function.
{"title":"Novel technique for testing FPGAs","authors":"C. Metra, M. Renovell, G. Mojoli, J. Portal, S. Pastore, J. Figueras, Y. Zorian, D. Salvi, G. Sechi","doi":"10.1109/DATE.1998.655841","DOIUrl":"https://doi.org/10.1109/DATE.1998.655841","url":null,"abstract":"This paper presents a novel technique for testing Field Programmable Gate Arrays (FPGAs), suitable for use in the case of frequent FPGA reuse and rapid dynamic modifiability of the implemented function.","PeriodicalId":179207,"journal":{"name":"Proceedings Design, Automation and Test in Europe","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114828148","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-02-23DOI: 10.1109/DATE.1998.655973
J. P. Calvez, Dominique Heller, F. Muller, O. Pasquier
This paper presents an innovative technique to efficiently develop hardware and software code generators. The specification model is first converted into its equivalent data structure. Target programs result from a set of transformation rules applied to the data structure. These rules are written in a textual form named Script. Moreover, transformations for a specific code generator are easier to describe because our solution uses a template of the required output as another input. The result is a meta-generator entirely written in Java. The concept and its implementation have been demonstrated by developing a C/WxWorks code generator, a behavioral VHDL generator, a synthesizable VHDL generator.
{"title":"A programmable multi-language generator for codesign","authors":"J. P. Calvez, Dominique Heller, F. Muller, O. Pasquier","doi":"10.1109/DATE.1998.655973","DOIUrl":"https://doi.org/10.1109/DATE.1998.655973","url":null,"abstract":"This paper presents an innovative technique to efficiently develop hardware and software code generators. The specification model is first converted into its equivalent data structure. Target programs result from a set of transformation rules applied to the data structure. These rules are written in a textual form named Script. Moreover, transformations for a specific code generator are easier to describe because our solution uses a template of the required output as another input. The result is a meta-generator entirely written in Java. The concept and its implementation have been demonstrated by developing a C/WxWorks code generator, a behavioral VHDL generator, a synthesizable VHDL generator.","PeriodicalId":179207,"journal":{"name":"Proceedings Design, Automation and Test in Europe","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124922742","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-02-23DOI: 10.1109/DATE.1998.656002
Jaime Velasco-Medina, T. Calin, M. Nicolaidis
A new test technique for linear analog circuits which employs current injection as input test stimulus is described. Our investigations have shown that current transitions resulting from a current injected on internal test points are significantly different for the fault free and faulty circuits. This can be used for fault detection purposes. In fact, the current injection as test input stimulus represents a powerful alternative to the test approaches based on conventional voltage input stimulus. The new approach allows one to improve the testability of various faults, which are difficult to detect or are untestable when using voltage-based test stimulus. In addition the technique has significant advantages for BIST purposes. The technique is illustrated by means of a modern opamp circuit and by considering catastrophic and gate-oxide-short (GOS) faults.
{"title":"Fault detection for linear analog circuits using current injection","authors":"Jaime Velasco-Medina, T. Calin, M. Nicolaidis","doi":"10.1109/DATE.1998.656002","DOIUrl":"https://doi.org/10.1109/DATE.1998.656002","url":null,"abstract":"A new test technique for linear analog circuits which employs current injection as input test stimulus is described. Our investigations have shown that current transitions resulting from a current injected on internal test points are significantly different for the fault free and faulty circuits. This can be used for fault detection purposes. In fact, the current injection as test input stimulus represents a powerful alternative to the test approaches based on conventional voltage input stimulus. The new approach allows one to improve the testability of various faults, which are difficult to detect or are untestable when using voltage-based test stimulus. In addition the technique has significant advantages for BIST purposes. The technique is illustrated by means of a modern opamp circuit and by considering catastrophic and gate-oxide-short (GOS) faults.","PeriodicalId":179207,"journal":{"name":"Proceedings Design, Automation and Test in Europe","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121584620","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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