Pub Date : 2011-12-01DOI: 10.1109/ESTIMedia.2011.6088526
H. Doan, Haris Javaid, S. Parameswaran
Parallel implementations of motion estimation for high definition videos typically exploit various forms of parallelism (GOP, frame-, slice- and macroblock-level) to deliver real-time throughput. Although parallel implementations deliver real-time throughput, they often suffer from limited flexibility and scalability due to the form of parallelism and architecture used. In this work, we use Group Of MacroBlocks (GOMB) and Intra-MB (IMB) parallelism with a multi-ASIP (Application Specific Instruction set Processor) architecture to provide a flexible and scalable platform for motion estimation of high definition videos. Multiple GOMBs are processed by the ASIPs in parallel (GOMB-level) where each ASIP is equipped with custom instructions to process the pixels of an MB in parallel (IMB-level). The system is flexible and scalable as the number of ASIPs (number of GOMBs) and custom instructions are not fixed, and are determined through design space exploration. We evaluated the multi-ASIP architecture in Tensilica's commercial design environment with varying number of ASIPs (up to nine), and compared hand-coded and automatically generated custom instructions. The results illustrate that systems with three and seven ASIPs delivered real-time throughput of 30 and 60 fps respectively for “pedestrian”, “rush hour” and “tractor” HD1080p video sequences. In addition, the results indicate that the multi-ASIP platform can be extended for even higher resolutions such as Ultra High Definition (UHD) due to its flexibility and scalability.
高清视频运动估计的并行实现通常利用各种形式的并行性(GOP、帧级、片级和宏块级)来提供实时吞吐量。尽管并行实现提供了实时吞吐量，但由于所使用的并行形式和体系结构，它们经常受到灵活性和可伸缩性的限制。在这项工作中，我们使用多asip(应用特定指令集处理器)架构的MacroBlocks Group (GOMB)和Intra-MB (IMB)并行性，为高清视频的运动估计提供了一个灵活和可扩展的平台。多个gomb由ASIP并行处理(gomb级)，其中每个ASIP都配备了自定义指令来并行处理一个MB的像素(imb级)。该系统具有灵活性和可扩展性，因为asip (gomb数量)和自定义指令的数量不是固定的，而是通过设计空间探索确定的。我们在Tensilica的商业设计环境中使用不同数量的asip(最多9个)评估了多asip架构，并比较了手工编码和自动生成的自定义指令。结果表明，对于“行人”、“高峰时间”和“拖拉机”HD1080p视频序列，具有3个和7个asip的系统分别提供了30和60 fps的实时吞吐量。此外，结果表明，由于其灵活性和可扩展性，多asip平台可以扩展到更高的分辨率，如超高清(UHD)。
{"title":"Multi-ASIP based parallel and scalable implementation of motion estimation kernel for high definition videos","authors":"H. Doan, Haris Javaid, S. Parameswaran","doi":"10.1109/ESTIMedia.2011.6088526","DOIUrl":"https://doi.org/10.1109/ESTIMedia.2011.6088526","url":null,"abstract":"Parallel implementations of motion estimation for high definition videos typically exploit various forms of parallelism (GOP, frame-, slice- and macroblock-level) to deliver real-time throughput. Although parallel implementations deliver real-time throughput, they often suffer from limited flexibility and scalability due to the form of parallelism and architecture used. In this work, we use Group Of MacroBlocks (GOMB) and Intra-MB (IMB) parallelism with a multi-ASIP (Application Specific Instruction set Processor) architecture to provide a flexible and scalable platform for motion estimation of high definition videos. Multiple GOMBs are processed by the ASIPs in parallel (GOMB-level) where each ASIP is equipped with custom instructions to process the pixels of an MB in parallel (IMB-level). The system is flexible and scalable as the number of ASIPs (number of GOMBs) and custom instructions are not fixed, and are determined through design space exploration. We evaluated the multi-ASIP architecture in Tensilica's commercial design environment with varying number of ASIPs (up to nine), and compared hand-coded and automatically generated custom instructions. The results illustrate that systems with three and seven ASIPs delivered real-time throughput of 30 and 60 fps respectively for “pedestrian”, “rush hour” and “tractor” HD1080p video sequences. In addition, the results indicate that the multi-ASIP platform can be extended for even higher resolutions such as Ultra High Definition (UHD) due to its flexibility and scalability.","PeriodicalId":180192,"journal":{"name":"2011 9th IEEE Symposium on Embedded Systems for Real-Time Multimedia","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114783590","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-01DOI: 10.1109/ESTIMedia.2011.6088518
E. Cannella, L. D. Gregorio, Leandro Fiorin, M. Lindwer, P. Meloni, Olaf Neugebauer, A. Pimentel
The MADNESS project aims at the definition of innovative system-level design methodologies for embedded MP-SoCs, extending the classic concept of design space exploration in multi-application domains to cope with high heterogeneity, technology scaling and system reliability. The main goal of the project is to provide a framework able to guide designers and researchers to the optimal composition of embedded MPSoC architectures, according to the requirements and the features of a given target application field. The proposed approach will tackle the new challenges, related to both architecture and design methodologies, arising with the technology scaling, the system reliability and the ever-growing computational needs of modern applications. The methodologies proposed with this project act at different levels of the design flow, enhancing the state-of-the art with novel features in system-level synthesis, architectural evaluation and prototyping. Support for fault resilience and efficient adaptive runtime management is introduced at hardware and middleware level, and considered by the system-level synthesis as one of the optimization factors to be taken into account. This paper presents the first stable results obtained in the MADNESS project, already demonstrating the effectiveness of the proposed methods.
{"title":"Towards an ESL design framework for adaptive and fault-tolerant MPSoCs: MADNESS or not?","authors":"E. Cannella, L. D. Gregorio, Leandro Fiorin, M. Lindwer, P. Meloni, Olaf Neugebauer, A. Pimentel","doi":"10.1109/ESTIMedia.2011.6088518","DOIUrl":"https://doi.org/10.1109/ESTIMedia.2011.6088518","url":null,"abstract":"The MADNESS project aims at the definition of innovative system-level design methodologies for embedded MP-SoCs, extending the classic concept of design space exploration in multi-application domains to cope with high heterogeneity, technology scaling and system reliability. The main goal of the project is to provide a framework able to guide designers and researchers to the optimal composition of embedded MPSoC architectures, according to the requirements and the features of a given target application field. The proposed approach will tackle the new challenges, related to both architecture and design methodologies, arising with the technology scaling, the system reliability and the ever-growing computational needs of modern applications. The methodologies proposed with this project act at different levels of the design flow, enhancing the state-of-the art with novel features in system-level synthesis, architectural evaluation and prototyping. Support for fault resilience and efficient adaptive runtime management is introduced at hardware and middleware level, and considered by the system-level synthesis as one of the optimization factors to be taken into account. This paper presents the first stable results obtained in the MADNESS project, already demonstrating the effectiveness of the proposed methods.","PeriodicalId":180192,"journal":{"name":"2011 9th IEEE Symposium on Embedded Systems for Real-Time Multimedia","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127929720","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-01DOI: 10.1109/ESTIMedia.2011.6088522
Yu-Hao Chang, Chi-Bang Kuan, Cheng-Yen Lin, Te-Feng Su, Chun-Ta Chen, J. Jang, S. Lai, Jenq-Kuen Lee
Applications on mobile devices are getting more complicated with the new wave of applications in the mobile devices. The computing power for embedded devices are increased with such trends, and embedded multi-core platform are in a position to help boost system performance. Software frameworks integrated the multi-core platforms are often needed to help boost the system performance and reduce programming complexity. In this paper, we present a software framework based on Android and multi-core embedded systems. In the framework, we integrate the compiler toolkit chain for multi-core programming environment which includes DSP C/C++ compilers, streaming RPC programming model, debugger, ESL simulator, and power management models. We also develop software framework for face detection, voice recognition, and mobile streaming management. Those frameworks are designed as multi-core programs and are used to illustrate the design flow for applications on embedded multi-core environments equipped with Android systems. We demonstrate our proposed mechanisms by implementing two applications, Face RMS and voice recognition. The proposed framework gives a case study to illustrate software framework and design flow for emerging RMS-based and voice recognition applications on embedded multi-core systems equipped with Android systems.
{"title":"Support of software framework for embedded multi-core systems with Android environments","authors":"Yu-Hao Chang, Chi-Bang Kuan, Cheng-Yen Lin, Te-Feng Su, Chun-Ta Chen, J. Jang, S. Lai, Jenq-Kuen Lee","doi":"10.1109/ESTIMedia.2011.6088522","DOIUrl":"https://doi.org/10.1109/ESTIMedia.2011.6088522","url":null,"abstract":"Applications on mobile devices are getting more complicated with the new wave of applications in the mobile devices. The computing power for embedded devices are increased with such trends, and embedded multi-core platform are in a position to help boost system performance. Software frameworks integrated the multi-core platforms are often needed to help boost the system performance and reduce programming complexity. In this paper, we present a software framework based on Android and multi-core embedded systems. In the framework, we integrate the compiler toolkit chain for multi-core programming environment which includes DSP C/C++ compilers, streaming RPC programming model, debugger, ESL simulator, and power management models. We also develop software framework for face detection, voice recognition, and mobile streaming management. Those frameworks are designed as multi-core programs and are used to illustrate the design flow for applications on embedded multi-core environments equipped with Android systems. We demonstrate our proposed mechanisms by implementing two applications, Face RMS and voice recognition. The proposed framework gives a case study to illustrate software framework and design flow for emerging RMS-based and voice recognition applications on embedded multi-core systems equipped with Android systems.","PeriodicalId":180192,"journal":{"name":"2011 9th IEEE Symposium on Embedded Systems for Real-Time Multimedia","volume":"153 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132395255","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-01DOI: 10.1109/ESTIMedia.2011.6088524
Li-Pin Chang, Yi-Hsun Huang, Chen-Yi Wen
Solid-state disks use arrays of flash-memory chips for data storage. They adopt multichannel architectures to exploit parallelism among flash operations. Under real disk workloads, a channel spends nearly the same amount of time on writing host data and collecting garbage. Thus, the key to the success of multichannel architectures is to achieve high parallelism among channel operations under these two kinds of activities. This study presents a channel management scheme that comprises a write-buffer design and two channel management policies. The proposed scheme is designed to be generic, and it is applicable to both hybrid mapping and page-level mapping. Our experimental results show that the proposed management scheme doubles the average number of write requests completed per second (e.g., write IOPS) of a baseline multichannel architecture. We also successfully implemented the proposed scheme in a real solid-state disk and demonstrated the feasibility of our approach.
{"title":"On the management of multichannel architectures of solid-state disks","authors":"Li-Pin Chang, Yi-Hsun Huang, Chen-Yi Wen","doi":"10.1109/ESTIMedia.2011.6088524","DOIUrl":"https://doi.org/10.1109/ESTIMedia.2011.6088524","url":null,"abstract":"Solid-state disks use arrays of flash-memory chips for data storage. They adopt multichannel architectures to exploit parallelism among flash operations. Under real disk workloads, a channel spends nearly the same amount of time on writing host data and collecting garbage. Thus, the key to the success of multichannel architectures is to achieve high parallelism among channel operations under these two kinds of activities. This study presents a channel management scheme that comprises a write-buffer design and two channel management policies. The proposed scheme is designed to be generic, and it is applicable to both hybrid mapping and page-level mapping. Our experimental results show that the proposed management scheme doubles the average number of write requests completed per second (e.g., write IOPS) of a baseline multichannel architecture. We also successfully implemented the proposed scheme in a real solid-state disk and demonstrated the feasibility of our approach.","PeriodicalId":180192,"journal":{"name":"2011 9th IEEE Symposium on Embedded Systems for Real-Time Multimedia","volume":"542 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116508823","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-01DOI: 10.1109/ESTIMedia.2011.6088525
F. Rattei, Philipp H. Kindt, Alma Pröbstl, S. Chakraborty
Vision-based automotive driver assistance systems have to cope with complex outdoor illumination conditions. Many applications for vehicle detection and tracking consider shadows caused by the sunlight as distracting effects and try to computationally compensate or disregard them. In this paper we suggest a shape-from-shadow approach which uses cast shadows as additional supporting information for vehicle model refinement and tracking. To take the position of the sun into account we only use sensor systems that mid-range vehicles are normally equipped with. Analysing shadows is a suitable method to support rear-view based vehicle tracking. A vehicle's shadow turned out to be a strong feature since it is possible to track a vehicle solely based on its shadow. Another benefit is that we are able to set up and refine three-dimensional shape models of vehicles driving ahead in the same lane. In selected situations it is possible to visually track two vehicles driving on the same lane one after another.
{"title":"Shadow-based vehicle model refinement and tracking in advanced automotive driver assistance systems","authors":"F. Rattei, Philipp H. Kindt, Alma Pröbstl, S. Chakraborty","doi":"10.1109/ESTIMedia.2011.6088525","DOIUrl":"https://doi.org/10.1109/ESTIMedia.2011.6088525","url":null,"abstract":"Vision-based automotive driver assistance systems have to cope with complex outdoor illumination conditions. Many applications for vehicle detection and tracking consider shadows caused by the sunlight as distracting effects and try to computationally compensate or disregard them. In this paper we suggest a shape-from-shadow approach which uses cast shadows as additional supporting information for vehicle model refinement and tracking. To take the position of the sun into account we only use sensor systems that mid-range vehicles are normally equipped with. Analysing shadows is a suitable method to support rear-view based vehicle tracking. A vehicle's shadow turned out to be a strong feature since it is possible to track a vehicle solely based on its shadow. Another benefit is that we are able to set up and refine three-dimensional shape models of vehicles driving ahead in the same lane. In selected situations it is possible to visually track two vehicles driving on the same lane one after another.","PeriodicalId":180192,"journal":{"name":"2011 9th IEEE Symposium on Embedded Systems for Real-Time Multimedia","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133995671","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-01DOI: 10.1109/ESTIMedia.2011.6088521
Jianhua Li, Liang Shi, C. Xue, Chengmo Yang, Yinlong Xu
Hybrid cache architectures have been proposed to mitigate the increasing on-chip power dissipation through the exploitation of the emerging non-volatile memories (NVMs). To overcome the high energy and long latency associated with write operations of NVMs, a small SRAM is typically incorporated into the hybrid cache for accommodating write-intensive cache blocks. How to efficiently manage this SRAM and manipulate the write operations are crucial to the performance of the hybrid cache. In this paper, we first present our observation that the intensity of write operations on different cache sets is usually non-uniform for real applications, such as multimedia, multi-programmed, multithreaded applications. The previously proposed hybrid cache schemes can not efficiently and symmetrically utilize the small SRAM to accommodate such widely-existing non-uniform writes on cache sets. Based on this observation, we propose a novel hybrid cache design, Dual Associative Hybrid Cache (denoted as DAHYC), as well as the corresponding cache management policy. By organizing the SRAM blocks in the hybrid cache as a semi-independent set-associative cache, several hybrid cache sets can efficiently share and cooperatively utilize their SRAM blocks, instead of exclusively utilizing the SRAM blocks in each cache set in previous hybrid cache schemes, to boost power-efficiency. Through prudently manipulating the locality information of SRAM blocks in both the NVM sets and the SRAM sets, the proposed cache management policy also delivers high-performance. Experimental results show that, compared with previous works, the DAHYC can reduce the dynamic power of the hybrid cache by 24.8% on average and up to 54% for SPEC2000 INT benchmarks, while at the same time improving the performance of the hybrid cache by 1.16% on average.
{"title":"Exploiting set-level write non-uniformity for energy-efficient NVM-based hybrid cache","authors":"Jianhua Li, Liang Shi, C. Xue, Chengmo Yang, Yinlong Xu","doi":"10.1109/ESTIMedia.2011.6088521","DOIUrl":"https://doi.org/10.1109/ESTIMedia.2011.6088521","url":null,"abstract":"Hybrid cache architectures have been proposed to mitigate the increasing on-chip power dissipation through the exploitation of the emerging non-volatile memories (NVMs). To overcome the high energy and long latency associated with write operations of NVMs, a small SRAM is typically incorporated into the hybrid cache for accommodating write-intensive cache blocks. How to efficiently manage this SRAM and manipulate the write operations are crucial to the performance of the hybrid cache. In this paper, we first present our observation that the intensity of write operations on different cache sets is usually non-uniform for real applications, such as multimedia, multi-programmed, multithreaded applications. The previously proposed hybrid cache schemes can not efficiently and symmetrically utilize the small SRAM to accommodate such widely-existing non-uniform writes on cache sets. Based on this observation, we propose a novel hybrid cache design, Dual Associative Hybrid Cache (denoted as DAHYC), as well as the corresponding cache management policy. By organizing the SRAM blocks in the hybrid cache as a semi-independent set-associative cache, several hybrid cache sets can efficiently share and cooperatively utilize their SRAM blocks, instead of exclusively utilizing the SRAM blocks in each cache set in previous hybrid cache schemes, to boost power-efficiency. Through prudently manipulating the locality information of SRAM blocks in both the NVM sets and the SRAM sets, the proposed cache management policy also delivers high-performance. Experimental results show that, compared with previous works, the DAHYC can reduce the dynamic power of the hybrid cache by 24.8% on average and up to 54% for SPEC2000 INT benchmarks, while at the same time improving the performance of the hybrid cache by 1.16% on average.","PeriodicalId":180192,"journal":{"name":"2011 9th IEEE Symposium on Embedded Systems for Real-Time Multimedia","volume":"166 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124654226","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-01DOI: 10.1109/ESTIMedia.2011.6088520
M. Westmijze, M. Bekooij, G. Smit, M. Schrijver
The real-time system research community has paid a lot of attention to the design of safety critical hard real-time systems for which the use of non-standard hardware and operating systems can be justified. However, stream processing applications like medical imaging systems are often not considered safety critical enough to justify the use of hard real-time techniques that would increase the cost of these systems significantly. Instead commercial off the shelf (COTS) hardware and OS are used, and techniques at the application level are employed to reduce the variation in the end-to-end latency of these imaging processing systems. In this paper, we study the effectiveness of a number of scheduling heuristics that are intended to reduce the latency and the jitter of stream processing applications that are executed on COTS multiprocessor systems. The proposed scheduling heuristics take the execution times of tasks into account as well as dependencies between the tasks, the data structures accessed by the tasks, and the memory hierarchy. Experiments were carried out on a quad core symmetric multiprocessing (SMP) Intel processor. These experiments show that the proposed heuristics can reduce the end-to-end latency with almost 60%, and reduce the variation in the latency with more than 90% when compared with a naive scheduling heuristic that does not consider execution times, dependencies and the memory hierarchy.
{"title":"Evaluation of scheduling heuristics for jitter reduction of real-time streaming applications on multi-core general purpose hardware","authors":"M. Westmijze, M. Bekooij, G. Smit, M. Schrijver","doi":"10.1109/ESTIMedia.2011.6088520","DOIUrl":"https://doi.org/10.1109/ESTIMedia.2011.6088520","url":null,"abstract":"The real-time system research community has paid a lot of attention to the design of safety critical hard real-time systems for which the use of non-standard hardware and operating systems can be justified. However, stream processing applications like medical imaging systems are often not considered safety critical enough to justify the use of hard real-time techniques that would increase the cost of these systems significantly. Instead commercial off the shelf (COTS) hardware and OS are used, and techniques at the application level are employed to reduce the variation in the end-to-end latency of these imaging processing systems. In this paper, we study the effectiveness of a number of scheduling heuristics that are intended to reduce the latency and the jitter of stream processing applications that are executed on COTS multiprocessor systems. The proposed scheduling heuristics take the execution times of tasks into account as well as dependencies between the tasks, the data structures accessed by the tasks, and the memory hierarchy. Experiments were carried out on a quad core symmetric multiprocessing (SMP) Intel processor. These experiments show that the proposed heuristics can reduce the end-to-end latency with almost 60%, and reduce the variation in the latency with more than 90% when compared with a naive scheduling heuristic that does not consider execution times, dependencies and the memory hierarchy.","PeriodicalId":180192,"journal":{"name":"2011 9th IEEE Symposium on Embedded Systems for Real-Time Multimedia","volume":"36 7","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114033484","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-01DOI: 10.1109/ESTIMedia.2011.6088527
Marcel Pockrandt, Paula Herber, S. Glesner
Transaction Level Modeling (TLM) is gaining more and more importance to quickly evaluate design alternatives in multimedia systems and other mixed HW/SW systems. However, the comprehensive and automated verification of TLM models is still a difficult challenge. In previous work, we presented an approach for model checking of SystemC/TLM designs based on a transformation into Uppaal timed automata. In this paper, we present an optimized version of our previously proposed transformation, and show its effectiveness with experimental results from an industrial case study. The key idea is to generate a Uppaal model that is especially tailored for being model checked. This significantly reduces the semantic state space and makes model checking considerably faster and less memory-consuming. We demonstrate this by comparing the verification times of both versions for our previously used case study, and by presenting results from a new and larger case study, namely a TLM implementation of the AMBA Advanced High-performance Bus (AHB). The AMBA bus is one of the most popular on-chip bus architectures in IP-based embedded SoCs, and it is used in many multimedia applications. The case study shows that with the proposed optimizations, our approach is applicable for industrial real world examples. The detection of a serious bug, namely a deadlock situation in a certain scenario, and also the verification of some important safety, liveness, and timing properties provide evidence for the usefulness of our approach.
{"title":"Model checking a SystemC/TLM design of the AMBA AHB protocol","authors":"Marcel Pockrandt, Paula Herber, S. Glesner","doi":"10.1109/ESTIMedia.2011.6088527","DOIUrl":"https://doi.org/10.1109/ESTIMedia.2011.6088527","url":null,"abstract":"Transaction Level Modeling (TLM) is gaining more and more importance to quickly evaluate design alternatives in multimedia systems and other mixed HW/SW systems. However, the comprehensive and automated verification of TLM models is still a difficult challenge. In previous work, we presented an approach for model checking of SystemC/TLM designs based on a transformation into Uppaal timed automata. In this paper, we present an optimized version of our previously proposed transformation, and show its effectiveness with experimental results from an industrial case study. The key idea is to generate a Uppaal model that is especially tailored for being model checked. This significantly reduces the semantic state space and makes model checking considerably faster and less memory-consuming. We demonstrate this by comparing the verification times of both versions for our previously used case study, and by presenting results from a new and larger case study, namely a TLM implementation of the AMBA Advanced High-performance Bus (AHB). The AMBA bus is one of the most popular on-chip bus architectures in IP-based embedded SoCs, and it is used in many multimedia applications. The case study shows that with the proposed optimizations, our approach is applicable for industrial real world examples. The detection of a serious bug, namely a deadlock situation in a certain scenario, and also the verification of some important safety, liveness, and timing properties provide evidence for the usefulness of our approach.","PeriodicalId":180192,"journal":{"name":"2011 9th IEEE Symposium on Embedded Systems for Real-Time Multimedia","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114775286","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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