Pub Date : 2017-07-01DOI: 10.1109/IVSW.2017.8031547
Evan Chavis, Harrison Davis, Yijun Hou, Matthew Hicks, Salessawi Ferede Yitbarek, T. Austin, V. Bertacco
In the continual battle between malware attacks and antivirus technologies, both sides strive to deploy their techniques at always lower layers in the software system stack. The goal is to monitor and control the software executing in the levels above their own deployment, to detect attacks or to defeat defenses. Recent antivirus solutions have gone even below the software, by enlisting hardware support. However, so far, they have only mimicked classic software techniques by monitoring software clues of an attack. As a result, malware can easily defeat them by employing metamorphic manifestation patterns. With this work, we propose a hardware-monitoring solution, SNIFFER, which tracks malware manifestations in system-level behavior, rather than code patterns, and it thus cannot be circumvented unless malware renounces its very nature, that is, to attack. SNIFFER leverages in-hardware feature monitoring, and uses machine learning to assess whether a system shows signs of an attack. Experiments with a virtual SNIFFER implementation, which supports 13 features and tests against five common network-based malicious behaviors, show that SNIFFER detects malware nearly 100% of the time, unless the malware aggressively throttle its attack. Our experiments also highlight the need for machine-learning classifiers employing a range of diverse system features, as many of the tested malware require multiple, seemingly disconnected, features for accurate detection.
{"title":"SNIFFER: A high-accuracy malware detector for enterprise-based systems","authors":"Evan Chavis, Harrison Davis, Yijun Hou, Matthew Hicks, Salessawi Ferede Yitbarek, T. Austin, V. Bertacco","doi":"10.1109/IVSW.2017.8031547","DOIUrl":"https://doi.org/10.1109/IVSW.2017.8031547","url":null,"abstract":"In the continual battle between malware attacks and antivirus technologies, both sides strive to deploy their techniques at always lower layers in the software system stack. The goal is to monitor and control the software executing in the levels above their own deployment, to detect attacks or to defeat defenses. Recent antivirus solutions have gone even below the software, by enlisting hardware support. However, so far, they have only mimicked classic software techniques by monitoring software clues of an attack. As a result, malware can easily defeat them by employing metamorphic manifestation patterns. With this work, we propose a hardware-monitoring solution, SNIFFER, which tracks malware manifestations in system-level behavior, rather than code patterns, and it thus cannot be circumvented unless malware renounces its very nature, that is, to attack. SNIFFER leverages in-hardware feature monitoring, and uses machine learning to assess whether a system shows signs of an attack. Experiments with a virtual SNIFFER implementation, which supports 13 features and tests against five common network-based malicious behaviors, show that SNIFFER detects malware nearly 100% of the time, unless the malware aggressively throttle its attack. Our experiments also highlight the need for machine-learning classifiers employing a range of diverse system features, as many of the tested malware require multiple, seemingly disconnected, features for accurate detection.","PeriodicalId":184196,"journal":{"name":"2017 IEEE 2nd International Verification and Security Workshop (IVSW)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131345376","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-07-01DOI: 10.1109/IVSW.2017.8031554
Ryan Berryhill, Neil Veira, A. Veneris, Zissis Poulos
Formal verification is one of the fastest growing fields in verification. The Boolean satisfiability-based unbounded model checking algorithm of IC3 has become widely applied in industry and is frequently used as a subroutine in other formal verification algorithms, such as FAIR and IICTL. Any improvement to IC3 can therefore yield substantial benefits in many areas of formal verification. Towards that end, this paper introduces the notion of a support graph, which is applied in IC3. Techniques are presented to compute the support graph by modifying the satisfiability queries used in IC3 at the cost of a modest increase in runtime. It is used to increase the re-use of information across runs of the model checker, thereby improving runtime performance in incremental model checking. It can also be applied within a single run of the model checker to avoid unnecessary queries to the satisfiability solver and accelerate the discovery of a proof. Experiments are presented on HWMCC'15 circuits demonstrating the benefits of the presented approaches.
{"title":"Learning lemma support graphs in Quip and IC3","authors":"Ryan Berryhill, Neil Veira, A. Veneris, Zissis Poulos","doi":"10.1109/IVSW.2017.8031554","DOIUrl":"https://doi.org/10.1109/IVSW.2017.8031554","url":null,"abstract":"Formal verification is one of the fastest growing fields in verification. The Boolean satisfiability-based unbounded model checking algorithm of IC3 has become widely applied in industry and is frequently used as a subroutine in other formal verification algorithms, such as FAIR and IICTL. Any improvement to IC3 can therefore yield substantial benefits in many areas of formal verification. Towards that end, this paper introduces the notion of a support graph, which is applied in IC3. Techniques are presented to compute the support graph by modifying the satisfiability queries used in IC3 at the cost of a modest increase in runtime. It is used to increase the re-use of information across runs of the model checker, thereby improving runtime performance in incremental model checking. It can also be applied within a single run of the model checker to avoid unnecessary queries to the satisfiability solver and accelerate the discovery of a proof. Experiments are presented on HWMCC'15 circuits demonstrating the benefits of the presented approaches.","PeriodicalId":184196,"journal":{"name":"2017 IEEE 2nd International Verification and Security Workshop (IVSW)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128432327","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-07-01DOI: 10.1109/IVSW.2017.8031539
Mohd Syafiq Mispan, Basel Halak, Mark Zwolinski
Building lightweight security for low-cost pervasive devices is a major challenge considering the design requirements of a small footprint and low power consumption. Physical Unclonable Functions (PUFs) have emerged as a promising technology to provide a low-cost authentication for such devices. By exploiting intrinsic manufacturing process variations, PUFs are able to generate unique and apparently random chip identifiers. Strong-PUFs represent a variant of PUFs that have been suggested for lightweight authentication applications. Unfortunately, many of the Strong-PUFs have been shown to be susceptible to modelling attacks (i.e., using machine learning techniques) in which an adversary has access to challenge and response pairs. In this study, we propose an obfuscation technique during post-processing of Strong-PUF responses to increase the resilience against machine learning attacks. We conduct machine learning experiments using Support Vector Machines and Artificial Neural Networks on two Strong-PUFs: a 32-bit Arbiter-PUF and a 2-XOR 32-bit Arbiter-PUF. The predictability of the 32-bit Arbiter-PUF is reduced to ≈ 70% by using an obfuscation technique. Combining the obfuscation technique with 2-XOR 32-bit Arbiter-PUF helps to reduce the predictability to ≈ 64%. More reduction in predictability has been observed in an XOR Arbiter-PUF because this PUF architecture has a good uniformity. The area overhead with an obfuscation technique consumes only 788 and 1080 gate equivalents for the 32-bit Arbiter-PUF and 2-XOR 32-bit Arbiter-PUF, respectively.
{"title":"Lightweight obfuscation techniques for modeling attacks resistant PUFs","authors":"Mohd Syafiq Mispan, Basel Halak, Mark Zwolinski","doi":"10.1109/IVSW.2017.8031539","DOIUrl":"https://doi.org/10.1109/IVSW.2017.8031539","url":null,"abstract":"Building lightweight security for low-cost pervasive devices is a major challenge considering the design requirements of a small footprint and low power consumption. Physical Unclonable Functions (PUFs) have emerged as a promising technology to provide a low-cost authentication for such devices. By exploiting intrinsic manufacturing process variations, PUFs are able to generate unique and apparently random chip identifiers. Strong-PUFs represent a variant of PUFs that have been suggested for lightweight authentication applications. Unfortunately, many of the Strong-PUFs have been shown to be susceptible to modelling attacks (i.e., using machine learning techniques) in which an adversary has access to challenge and response pairs. In this study, we propose an obfuscation technique during post-processing of Strong-PUF responses to increase the resilience against machine learning attacks. We conduct machine learning experiments using Support Vector Machines and Artificial Neural Networks on two Strong-PUFs: a 32-bit Arbiter-PUF and a 2-XOR 32-bit Arbiter-PUF. The predictability of the 32-bit Arbiter-PUF is reduced to ≈ 70% by using an obfuscation technique. Combining the obfuscation technique with 2-XOR 32-bit Arbiter-PUF helps to reduce the predictability to ≈ 64%. More reduction in predictability has been observed in an XOR Arbiter-PUF because this PUF architecture has a good uniformity. The area overhead with an obfuscation technique consumes only 788 and 1080 gate equivalents for the 32-bit Arbiter-PUF and 2-XOR 32-bit Arbiter-PUF, respectively.","PeriodicalId":184196,"journal":{"name":"2017 IEEE 2nd International Verification and Security Workshop (IVSW)","volume":"116 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124719065","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-07-01DOI: 10.1109/IVSW.2017.8031555
E. Fabiani, Loïc Lagadec, M. B. Hammouda, C. Teodorov
ICs are subject to many causes of malfunction such as aging or aggressive environment, while avoiding unwanted behavior of critical applications is a key issue. Monitoring is a cornerstone of safety policies, as it supports triggering counter measures on demand. High Level Synthesis (HLS) allows to easily implement applications in hardware, and some HLS compliant solutions have been reported. These solutions monitor applications through asserting properties to variables. This paper extends this approach by proposing causal assertions, dedicated to monitoring the evolution of variables over time. Results demonstrate significant gains in term of reactivity and error coverage rate, while keeping the overhead low.
{"title":"Asserting causal properties in High Level Synthesis","authors":"E. Fabiani, Loïc Lagadec, M. B. Hammouda, C. Teodorov","doi":"10.1109/IVSW.2017.8031555","DOIUrl":"https://doi.org/10.1109/IVSW.2017.8031555","url":null,"abstract":"ICs are subject to many causes of malfunction such as aging or aggressive environment, while avoiding unwanted behavior of critical applications is a key issue. Monitoring is a cornerstone of safety policies, as it supports triggering counter measures on demand. High Level Synthesis (HLS) allows to easily implement applications in hardware, and some HLS compliant solutions have been reported. These solutions monitor applications through asserting properties to variables. This paper extends this approach by proposing causal assertions, dedicated to monitoring the evolution of variables over time. Results demonstrate significant gains in term of reactivity and error coverage rate, while keeping the overhead low.","PeriodicalId":184196,"journal":{"name":"2017 IEEE 2nd International Verification and Security Workshop (IVSW)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132884385","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-07-01DOI: 10.1109/IVSW.2017.8031557
Karen Horovitz, Meha Kainth, Ryan Kenny
In previous generations of Intel FPGAs, we employed design separation through the use of LogicLock in Cyclone IIILS and Arria V devices. In the past, this meant separation of design elements as well as designated protected design boundaries in different ‘Logic Lock’ regions. Though separated logically, these regions have the same protection and risk if the key is revealed. Today, using Partition-Based Security, we can encrypt these regions with different keys thus fully supporting separation and allowing secure, encrypted regions of the FPGA fabric to exist. We demonstrate partition-based security using an Intel FPGA Arria 10 SoC Development Kit with two partial reconfiguration regions encrypted with two different keys.
{"title":"Protecting partial regions in FPGA bitstreams","authors":"Karen Horovitz, Meha Kainth, Ryan Kenny","doi":"10.1109/IVSW.2017.8031557","DOIUrl":"https://doi.org/10.1109/IVSW.2017.8031557","url":null,"abstract":"In previous generations of Intel FPGAs, we employed design separation through the use of LogicLock in Cyclone IIILS and Arria V devices. In the past, this meant separation of design elements as well as designated protected design boundaries in different ‘Logic Lock’ regions. Though separated logically, these regions have the same protection and risk if the key is revealed. Today, using Partition-Based Security, we can encrypt these regions with different keys thus fully supporting separation and allowing secure, encrypted regions of the FPGA fabric to exist. We demonstrate partition-based security using an Intel FPGA Arria 10 SoC Development Kit with two partial reconfiguration regions encrypted with two different keys.","PeriodicalId":184196,"journal":{"name":"2017 IEEE 2nd International Verification and Security Workshop (IVSW)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123295799","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-07-01DOI: 10.1109/IVSW.2017.8031540
R. Parker
We describe a minimum entropy justification for the metastable latch based nondeterministic random bit generator (NRBG) also known as an entropy source (ES). The NRBG, used for on-die generation of cryptographic keys in SOCs, is comprised of a CMOS latch with a continuously running offset cancellation loop. The offset cancellation allows for the resolution required to sample device noise at the expense of introducing serial correlation in the output data. Because the NRBG is embedded within SP 800-90 A/B/C and FIPs 140-2 compliant systems, it is critical that the loss of entropy due to serial correlation be known and bounded, and that there is a mechanism to detect loss of entropy during manufacturing test as well as normal operation. We demonstrate that a simplified one-dimensional stochastic model of the comparator in conjunction with a birth-death Markov chain model of the offset cancellation can be used to derive the minimum entropy of the NRBG and the probability of bit patterns used by entropy quality health test circuits. The result of this work compares excellently to measured data from an advanced FinFET process.
{"title":"Entropy justification for metastability based nondeterministic random bit generator","authors":"R. Parker","doi":"10.1109/IVSW.2017.8031540","DOIUrl":"https://doi.org/10.1109/IVSW.2017.8031540","url":null,"abstract":"We describe a minimum entropy justification for the metastable latch based nondeterministic random bit generator (NRBG) also known as an entropy source (ES). The NRBG, used for on-die generation of cryptographic keys in SOCs, is comprised of a CMOS latch with a continuously running offset cancellation loop. The offset cancellation allows for the resolution required to sample device noise at the expense of introducing serial correlation in the output data. Because the NRBG is embedded within SP 800-90 A/B/C and FIPs 140-2 compliant systems, it is critical that the loss of entropy due to serial correlation be known and bounded, and that there is a mechanism to detect loss of entropy during manufacturing test as well as normal operation. We demonstrate that a simplified one-dimensional stochastic model of the comparator in conjunction with a birth-death Markov chain model of the offset cancellation can be used to derive the minimum entropy of the NRBG and the probability of bit patterns used by entropy quality health test circuits. The result of this work compares excellently to measured data from an advanced FinFET process.","PeriodicalId":184196,"journal":{"name":"2017 IEEE 2nd International Verification and Security Workshop (IVSW)","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123607946","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-07-01DOI: 10.1109/IVSW.2017.8031558
Debapriya Basu Roy, S. Bhasin, I. Nikolic, Debdeep Mukhopadhyay
Modern FPGAs, due to its many advanced features, have become a popular implementation platform for various applications like aerospace, defence, automotive, cryptography and many more. Additionally, modern FPGAs are equipped with high performance hard-IPs which has reduced the performance gap between ASIC and FPGAs significantly. Dynamically Reconfigurable Look-up-Tables (RLUT) is an advanced feature of modern FPGAs whose content can be updated internally, even during run-time without requiring any bit-stream update. These RLUTs can be used to develop stealthy hardware Trojans with zero overhead payload designs. This phenomenon when combined with an efficient triggering methodology, can lead to the insertion of covert back-doors in cryptographic applications. Furthermore, RLUTs can be deployed for developing customizable S-Box and lightweight S-Box masking schemes. This lightweight S-Box masking scheme when combined with other non-efficient side channel countermeasures (like shuffling) can generate lightweight and efficient side channel countermeasure for lightweight cryptographic applications. Additionally, RLUTs can also be applied to solve long standing problem of FPGA based IP protection. FPGA vendors are making serious efforts for IP protection leading to standardization schemes like IEEE P1735. However, efficient techniques to prevent unauthorized overuse of IP still remain an open question. In this work, we have developed an efficient IP licensing scheme by combining RLUTs with physically unclonable functions (PUFs) and a lightweight cryptographic application. This work summarizes applications of RLUTs for different applications related with FPGA security. It shows applicability of RLUTs for security application on FPGA and its applicability on FPGA security by development of IP licensing protocols
{"title":"Opening pandora's box: Implication of RLUT on secure FPGA applications and IP security","authors":"Debapriya Basu Roy, S. Bhasin, I. Nikolic, Debdeep Mukhopadhyay","doi":"10.1109/IVSW.2017.8031558","DOIUrl":"https://doi.org/10.1109/IVSW.2017.8031558","url":null,"abstract":"Modern FPGAs, due to its many advanced features, have become a popular implementation platform for various applications like aerospace, defence, automotive, cryptography and many more. Additionally, modern FPGAs are equipped with high performance hard-IPs which has reduced the performance gap between ASIC and FPGAs significantly. Dynamically Reconfigurable Look-up-Tables (RLUT) is an advanced feature of modern FPGAs whose content can be updated internally, even during run-time without requiring any bit-stream update. These RLUTs can be used to develop stealthy hardware Trojans with zero overhead payload designs. This phenomenon when combined with an efficient triggering methodology, can lead to the insertion of covert back-doors in cryptographic applications. Furthermore, RLUTs can be deployed for developing customizable S-Box and lightweight S-Box masking schemes. This lightweight S-Box masking scheme when combined with other non-efficient side channel countermeasures (like shuffling) can generate lightweight and efficient side channel countermeasure for lightweight cryptographic applications. Additionally, RLUTs can also be applied to solve long standing problem of FPGA based IP protection. FPGA vendors are making serious efforts for IP protection leading to standardization schemes like IEEE P1735. However, efficient techniques to prevent unauthorized overuse of IP still remain an open question. In this work, we have developed an efficient IP licensing scheme by combining RLUTs with physically unclonable functions (PUFs) and a lightweight cryptographic application. This work summarizes applications of RLUTs for different applications related with FPGA security. It shows applicability of RLUTs for security application on FPGA and its applicability on FPGA security by development of IP licensing protocols","PeriodicalId":184196,"journal":{"name":"2017 IEEE 2nd International Verification and Security Workshop (IVSW)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126392522","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-07-01DOI: 10.1109/IVSW.2017.8031553
B. Kaminska, J. Patel, Hao Jiang
New concepts for hardware security and 3D packaging/alignment are presented. The autonomous nano-structures can be inserted in any unused spaces on the silicon wafer or other medium, and can be divided on multiple layers for security, authentication, key function, and process control.
{"title":"Secure authentication of electronic systems with autonomous optical nano-devices","authors":"B. Kaminska, J. Patel, Hao Jiang","doi":"10.1109/IVSW.2017.8031553","DOIUrl":"https://doi.org/10.1109/IVSW.2017.8031553","url":null,"abstract":"New concepts for hardware security and 3D packaging/alignment are presented. The autonomous nano-structures can be inserted in any unused spaces on the silicon wafer or other medium, and can be divided on multiple layers for security, authentication, key function, and process control.","PeriodicalId":184196,"journal":{"name":"2017 IEEE 2nd International Verification and Security Workshop (IVSW)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121911550","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-07-01DOI: 10.1109/IVSW.2017.8031559
Jo Vliegen, Oscar Reparaz, N. Mentens
In this paper, we push the limits in maximizing the throughput of side-channel-protected AES-GCM implementations on an FPGA. We present a fully unrolled and pipelined architecture that uses a Boolean masking countermeasure (specifically, threshold implementation) for first-order DPA resistance. Using a high-end Virtex-7 device, we obtain a throughput of 15.24 Gbit/s. Since masked implementations require a stream of random bits for each execution, a high-throughput masked implementation requires a high-throughput pseudorandom number generator as well. This work determines how fast random numbers should be generated in order for ultra-high throughput, threshold-protected AES-GCM implementations to be feasible on FPGAs.
{"title":"Maximizing the throughput of threshold-protected AES-GCM implementations on FPGA","authors":"Jo Vliegen, Oscar Reparaz, N. Mentens","doi":"10.1109/IVSW.2017.8031559","DOIUrl":"https://doi.org/10.1109/IVSW.2017.8031559","url":null,"abstract":"In this paper, we push the limits in maximizing the throughput of side-channel-protected AES-GCM implementations on an FPGA. We present a fully unrolled and pipelined architecture that uses a Boolean masking countermeasure (specifically, threshold implementation) for first-order DPA resistance. Using a high-end Virtex-7 device, we obtain a throughput of 15.24 Gbit/s. Since masked implementations require a stream of random bits for each execution, a high-throughput masked implementation requires a high-throughput pseudorandom number generator as well. This work determines how fast random numbers should be generated in order for ultra-high throughput, threshold-protected AES-GCM implementations to be feasible on FPGAs.","PeriodicalId":184196,"journal":{"name":"2017 IEEE 2nd International Verification and Security Workshop (IVSW)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130438815","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-07-01DOI: 10.1109/IVSW.2017.8031549
Eli Weintraub
Organizations are exposed to various cyber-attacks. When a component is exploited, the overall computed damage is impacted by the number of components the network includes. This work is focuses on estimating the Target Distribution characteristic of an attacked network. According existing security assessment models, Target Distribution is assessed by using ordinal values based on users' intuitive knowledge. This work is aimed at defining a formula which enables measuring quantitatively the attacked components' distribution. The proposed formula is based on the real-time configuration of the system. Using the proposed measure, firms can quantify damages, allocate appropriate budgets to actual real risks and build their configuration while taking in consideration the risks impacted by components' distribution. The formula is demonstrated as part of a security continuous monitoring system.
{"title":"Estimating Target Distribution in security assessment models","authors":"Eli Weintraub","doi":"10.1109/IVSW.2017.8031549","DOIUrl":"https://doi.org/10.1109/IVSW.2017.8031549","url":null,"abstract":"Organizations are exposed to various cyber-attacks. When a component is exploited, the overall computed damage is impacted by the number of components the network includes. This work is focuses on estimating the Target Distribution characteristic of an attacked network. According existing security assessment models, Target Distribution is assessed by using ordinal values based on users' intuitive knowledge. This work is aimed at defining a formula which enables measuring quantitatively the attacked components' distribution. The proposed formula is based on the real-time configuration of the system. Using the proposed measure, firms can quantify damages, allocate appropriate budgets to actual real risks and build their configuration while taking in consideration the risks impacted by components' distribution. The formula is demonstrated as part of a security continuous monitoring system.","PeriodicalId":184196,"journal":{"name":"2017 IEEE 2nd International Verification and Security Workshop (IVSW)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132196051","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：