Pub Date : 2017-07-01DOI: 10.1109/IVSW.2017.8031548
E. Woo, Mark Zwolinski, Basel Halak
As technology scaling reaches nanometre scales, the error rate due to variations in temperature and voltage, single event effects and component degradation increases, making components less reliable. In order to ensure a system continues to function correctly while facing known reliability issues, it is imperative that the system should have the means to detect the occurrence of errors due to the presence of faults. A system that behaves normally (no error detected in the system) exhibits a profile, and any deviations from this profile indicate that there is an anomaly in the system. In this paper, we propose to use hardware performance counters (HPCs) to measure events that occur during the execution of the program. We explore the various counters available which could be use to identify the anomalous behaviour in the system and develop a methodology to observe the anomalies using HPCs by creating a fault-free pattern and observing any subsequent changes in that pattern. We evaluate the proposed technique using GemFI, an architectural simulator based on Gem5 with additional fault injection capabilities. We compare the results obtained at the end of the execution with data collected during a time interval. Our results show that HPCs can be used to identify anomalous behaviour in a system that would lead to failure.
{"title":"Hardware performance counters for system reliability monitoring","authors":"E. Woo, Mark Zwolinski, Basel Halak","doi":"10.1109/IVSW.2017.8031548","DOIUrl":"https://doi.org/10.1109/IVSW.2017.8031548","url":null,"abstract":"As technology scaling reaches nanometre scales, the error rate due to variations in temperature and voltage, single event effects and component degradation increases, making components less reliable. In order to ensure a system continues to function correctly while facing known reliability issues, it is imperative that the system should have the means to detect the occurrence of errors due to the presence of faults. A system that behaves normally (no error detected in the system) exhibits a profile, and any deviations from this profile indicate that there is an anomaly in the system. In this paper, we propose to use hardware performance counters (HPCs) to measure events that occur during the execution of the program. We explore the various counters available which could be use to identify the anomalous behaviour in the system and develop a methodology to observe the anomalies using HPCs by creating a fault-free pattern and observing any subsequent changes in that pattern. We evaluate the proposed technique using GemFI, an architectural simulator based on Gem5 with additional fault injection capabilities. We compare the results obtained at the end of the execution with data collected during a time interval. Our results show that HPCs can be used to identify anomalous behaviour in a system that would lead to failure.","PeriodicalId":184196,"journal":{"name":"2017 IEEE 2nd International Verification and Security Workshop (IVSW)","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132232052","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-07-01DOI: 10.1109/IVSW.2017.8031544
G. D. Natale, M. Flottes, Sophie Dupuis, B. Rouzeyre
Many techniques have been proposed in literature to cope with transient, permanent and malicious faults in computing systems. Among these techniques for reliability improvement and fault tolerance, Control Flow Checking allows covering any fault affecting the part of the storing elements containing the executable program, as well as all the hardware components handling the program itself and its flow. In [1] the authors proposed a low-overhead solution implementing hardware based control flow monitoring technique. They suggested that control flow error detection could be also used as a solution for enhancing the security of a computing system, preventing the insertion of malicious code in an application. In this paper we present a technique to map a malicious program into another one without structure violation and thus bypassing the control flow detection method.
{"title":"Hacking the Control Flow error detection mechanism","authors":"G. D. Natale, M. Flottes, Sophie Dupuis, B. Rouzeyre","doi":"10.1109/IVSW.2017.8031544","DOIUrl":"https://doi.org/10.1109/IVSW.2017.8031544","url":null,"abstract":"Many techniques have been proposed in literature to cope with transient, permanent and malicious faults in computing systems. Among these techniques for reliability improvement and fault tolerance, Control Flow Checking allows covering any fault affecting the part of the storing elements containing the executable program, as well as all the hardware components handling the program itself and its flow. In [1] the authors proposed a low-overhead solution implementing hardware based control flow monitoring technique. They suggested that control flow error detection could be also used as a solution for enhancing the security of a computing system, preventing the insertion of malicious code in an application. In this paper we present a technique to map a malicious program into another one without structure violation and thus bypassing the control flow detection method.","PeriodicalId":184196,"journal":{"name":"2017 IEEE 2nd International Verification and Security Workshop (IVSW)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131321402","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-07-01DOI: 10.1109/IVSW.2017.8031538
S. Aftabjahani, A. Das
The state of art secure digital computing systems heavily rely on secure hardware as the Trusted Computing Base to build upon the chain of trust for trusted computing. Attack Protection Blocks are added to the hardware to prevent an adversary from bypassing the security provided by hardware using various side channel, voltage, frequency, temperature, and other attacks. However, attackers can target the security protection features by designing experiments to understand the underlying power distribution network and its possible weaknesses. This can be used to temporarily turn off or damage the protection features by manipulation of the digital and analog voltage lines if over- and/or under- voltage protection for protection blocks is not present. Usually, in designs, the necessity of such protection has been overlooked just by the assumption that the probability of bypassing the protection without losing the functionality of the system is low. In this context, we present a robust system design approach which will enable the system to transition to a security safe (instead of unsafe) failure mode by increasing resilience of protection blocks against over- and under- voltage attacks. We show by probabilistic modeling why such attacks are possible and why our mitigation approach works.
{"title":"Robust secure design by increasing the resilience of Attack Protection Blocks","authors":"S. Aftabjahani, A. Das","doi":"10.1109/IVSW.2017.8031538","DOIUrl":"https://doi.org/10.1109/IVSW.2017.8031538","url":null,"abstract":"The state of art secure digital computing systems heavily rely on secure hardware as the Trusted Computing Base to build upon the chain of trust for trusted computing. Attack Protection Blocks are added to the hardware to prevent an adversary from bypassing the security provided by hardware using various side channel, voltage, frequency, temperature, and other attacks. However, attackers can target the security protection features by designing experiments to understand the underlying power distribution network and its possible weaknesses. This can be used to temporarily turn off or damage the protection features by manipulation of the digital and analog voltage lines if over- and/or under- voltage protection for protection blocks is not present. Usually, in designs, the necessity of such protection has been overlooked just by the assumption that the probability of bypassing the protection without losing the functionality of the system is low. In this context, we present a robust system design approach which will enable the system to transition to a security safe (instead of unsafe) failure mode by increasing resilience of protection blocks against over- and under- voltage attacks. We show by probabilistic modeling why such attacks are possible and why our mitigation approach works.","PeriodicalId":184196,"journal":{"name":"2017 IEEE 2nd International Verification and Security Workshop (IVSW)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115626466","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-07-01DOI: 10.1109/IVSW.2017.8031560
Ugo Mureddu, O. Petura, Nathalie Bochard, L. Bossuet, V. Fischer
With the scaling down of electronic devices and the boom of wireless communications, more and more smart devices are interconnected in what we call the Internet of Things. Connecting devices of everyday use can greatly improve our comfort, but it can also introduce unprecedented security problems. With billions of devices connected there is a huge risk of unauthorized use. In this context, Physical Unclonable Functions (PUFs) are a promising solution since they extract device intrinsic fingerprint that can be used for hardware identification and authentication. Here we present the first fully functional implementation of Oscillator based PUFs on Flash based FPGA. The implementation is presented for the Ring Oscillator based PUF and the Transient Effect Ring Oscillatory based PUF. After explaining those two PUF principles, we give all the necessary design practices to follow to obtain an efficient PUF implementation on Flash FPGA. Finally, we present the characterization of the PUFs and compare it to previous work. To the best of our knowledge, it is the first work which deals with the implementation of Oscillator based PUF on Flash FPGAs. Moreover, all design files are available online to ensure repeatability.
{"title":"Efficient design of Oscillator based Physical Unclonable Functions on Flash FPGAs","authors":"Ugo Mureddu, O. Petura, Nathalie Bochard, L. Bossuet, V. Fischer","doi":"10.1109/IVSW.2017.8031560","DOIUrl":"https://doi.org/10.1109/IVSW.2017.8031560","url":null,"abstract":"With the scaling down of electronic devices and the boom of wireless communications, more and more smart devices are interconnected in what we call the Internet of Things. Connecting devices of everyday use can greatly improve our comfort, but it can also introduce unprecedented security problems. With billions of devices connected there is a huge risk of unauthorized use. In this context, Physical Unclonable Functions (PUFs) are a promising solution since they extract device intrinsic fingerprint that can be used for hardware identification and authentication. Here we present the first fully functional implementation of Oscillator based PUFs on Flash based FPGA. The implementation is presented for the Ring Oscillator based PUF and the Transient Effect Ring Oscillatory based PUF. After explaining those two PUF principles, we give all the necessary design practices to follow to obtain an efficient PUF implementation on Flash FPGA. Finally, we present the characterization of the PUFs and compare it to previous work. To the best of our knowledge, it is the first work which deals with the implementation of Oscillator based PUF on Flash FPGAs. Moreover, all design files are available online to ensure repeatability.","PeriodicalId":184196,"journal":{"name":"2017 IEEE 2nd International Verification and Security Workshop (IVSW)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129483486","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-17DOI: 10.1109/IVSW.2017.8031552
E. Vatajelu, G. D. Natale, P. Prinetto
Physically Unclonable Functions (PUFs) are emerging cryptographic primitives used to implement low-cost device authentication and secure secret key generation. While several solutions exist for classical CMOS devices, novel proposals have been recently presented which exploit emerging technologies like magnetic memories. The Spin-Transfer-Torque Magnetic Random Access Memory (STT-MRAM) is a promising choice for future PUFs due to the high variability affecting the electrical resistance of the Magnetic Tunnel Junction (MTJ) device in anti-parallel magnetization. Some papers showed that these devices could guarantee high levels of both unclonability and reliability. However, 100% reliability is not yet obtained in those proposals. In this paper we present an effective method to identify the unreliable cells in a PUF implementation. This information is then used to create a zero bit-error-rate PUF scheme.
{"title":"Zero bit-error-rate weak PUF based on Spin-Transfer-Torque MRAM memories","authors":"E. Vatajelu, G. D. Natale, P. Prinetto","doi":"10.1109/IVSW.2017.8031552","DOIUrl":"https://doi.org/10.1109/IVSW.2017.8031552","url":null,"abstract":"Physically Unclonable Functions (PUFs) are emerging cryptographic primitives used to implement low-cost device authentication and secure secret key generation. While several solutions exist for classical CMOS devices, novel proposals have been recently presented which exploit emerging technologies like magnetic memories. The Spin-Transfer-Torque Magnetic Random Access Memory (STT-MRAM) is a promising choice for future PUFs due to the high variability affecting the electrical resistance of the Magnetic Tunnel Junction (MTJ) device in anti-parallel magnetization. Some papers showed that these devices could guarantee high levels of both unclonability and reliability. However, 100% reliability is not yet obtained in those proposals. In this paper we present an effective method to identify the unreliable cells in a PUF implementation. This information is then used to create a zero bit-error-rate PUF scheme.","PeriodicalId":184196,"journal":{"name":"2017 IEEE 2nd International Verification and Security Workshop (IVSW)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115986545","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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