Pub Date : 1997-11-13DOI: 10.1109/ICCAD.1997.643594
Tzuhao Chen, I. Hajj
In this paper we describe GOLDENGATE-a bridging fault simulator for cell-based digital VLSI circuits with the following features: 1. It targets both combinational and sequential circuits. 2. It simulates general (routing, adjacency, and intra-cell) realistic bridging faults efficiently through a table-based scheme. The pre-computed table contains accurate cell output voltage and I/sub DDQ/ values obtained through electrical-level simulations. 3. It simulates both feedback and nonfeedback bridging faults (BFs) efficiently through a cycling event-driven technique. 4. It allows mixed voltage and I/sub DDQ/ simulation to support a fully hybrid test scheme where mixed logic and I/sub DDQ/ sensings are allowed. The experimental results show that GOLDENGATE is both accurate and fast.
{"title":"GOLDENGATE: a fast and accurate bridging fault simulator under a hybrid logic/I/sub DDQ/ testing environment","authors":"Tzuhao Chen, I. Hajj","doi":"10.1109/ICCAD.1997.643594","DOIUrl":"https://doi.org/10.1109/ICCAD.1997.643594","url":null,"abstract":"In this paper we describe GOLDENGATE-a bridging fault simulator for cell-based digital VLSI circuits with the following features: 1. It targets both combinational and sequential circuits. 2. It simulates general (routing, adjacency, and intra-cell) realistic bridging faults efficiently through a table-based scheme. The pre-computed table contains accurate cell output voltage and I/sub DDQ/ values obtained through electrical-level simulations. 3. It simulates both feedback and nonfeedback bridging faults (BFs) efficiently through a cycling event-driven technique. 4. It allows mixed voltage and I/sub DDQ/ simulation to support a fully hybrid test scheme where mixed logic and I/sub DDQ/ sensings are allowed. The experimental results show that GOLDENGATE is both accurate and fast.","PeriodicalId":187521,"journal":{"name":"1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127401195","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-11-13DOI: 10.1109/ICCAD.1997.643538
S. Raje, R. Bergamaschi
Resource sharing is one of the main tasks in high-level synthesis, and although many algorithms have addressed the problem there are still several limitations which restrict the generality and applicability of current algorithms. Most clique-partitioning-based algorithms use local and inaccurate cost-functions which result in inefficient results. This paper presents algorithms for the resource sharing problem on registers and functional units, and shows how they overcome the limitations of existing algorithms. The main characteristics of this work are: interleaved register and functional unit merging in a global clique partitioning based framework, accurate merging cost estimation, accurate interconnect cost estimation, relative control cost taken into account and efficient false loop elimination. The results obtained show significant improvements in the delay of designs, while also minimizing area, specially for large designs with many sharing possibilities.
{"title":"Generalized resource sharing","authors":"S. Raje, R. Bergamaschi","doi":"10.1109/ICCAD.1997.643538","DOIUrl":"https://doi.org/10.1109/ICCAD.1997.643538","url":null,"abstract":"Resource sharing is one of the main tasks in high-level synthesis, and although many algorithms have addressed the problem there are still several limitations which restrict the generality and applicability of current algorithms. Most clique-partitioning-based algorithms use local and inaccurate cost-functions which result in inefficient results. This paper presents algorithms for the resource sharing problem on registers and functional units, and shows how they overcome the limitations of existing algorithms. The main characteristics of this work are: interleaved register and functional unit merging in a global clique partitioning based framework, accurate merging cost estimation, accurate interconnect cost estimation, relative control cost taken into account and efficient false loop elimination. The results obtained show significant improvements in the delay of designs, while also minimizing area, specially for large designs with many sharing possibilities.","PeriodicalId":187521,"journal":{"name":"1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116643218","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-11-13DOI: 10.1109/ICCAD.1997.643595
S. Venkataraman, W. Fuchs
A deductive technique is presented that uses voltage testing for the diagnosis of single bridging faults between two gate input or output lines and is applicable to combinational or full-scan sequential circuits. For defects in this class of faults the method is accurate by construction while making no assumptions about the logic-level wired-AND/OR behaviour. A path-trace procedure starting from failing outputs deduces potential lines associated with the bridge. The information obtained from the path-trace from failing outputs is combined using an intersection graph to make further deductions. All candidate faults are implicitly represented, thereby obviating the need to enumerate faults and hence allowing the exploration of the space of all faults. Results are provided for all large ISCAS89 benchmark circuits.
{"title":"A deductive technique for diagnosis of bridging faults","authors":"S. Venkataraman, W. Fuchs","doi":"10.1109/ICCAD.1997.643595","DOIUrl":"https://doi.org/10.1109/ICCAD.1997.643595","url":null,"abstract":"A deductive technique is presented that uses voltage testing for the diagnosis of single bridging faults between two gate input or output lines and is applicable to combinational or full-scan sequential circuits. For defects in this class of faults the method is accurate by construction while making no assumptions about the logic-level wired-AND/OR behaviour. A path-trace procedure starting from failing outputs deduces potential lines associated with the bridge. The information obtained from the path-trace from failing outputs is combined using an intersection graph to make further deductions. All candidate faults are implicitly represented, thereby obviating the need to enumerate faults and hence allowing the exploration of the space of all faults. Results are provided for all large ISCAS89 benchmark circuits.","PeriodicalId":187521,"journal":{"name":"1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121856995","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-11-13DOI: 10.1109/ICCAD.1997.643574
Kapur, Long
Integral equation techniques are often used to extract models of integrated circuit structures. This extraction involves solving a dense system of linear equations, and using direct solution methods is prohibitive for large problems. In this paper, we present IES/sup 3/ (pronounced "ice cube"), a fast Integral Equation Solver for three-dimensional problems with arbitrary kernels. Extraction methods based on IES/sup 3/ are substantially more efficient than existing multipole-based approaches.
{"title":"IES/sup 3/: a fast integral equation solver for efficient 3-dimensional extraction","authors":"Kapur, Long","doi":"10.1109/ICCAD.1997.643574","DOIUrl":"https://doi.org/10.1109/ICCAD.1997.643574","url":null,"abstract":"Integral equation techniques are often used to extract models of integrated circuit structures. This extraction involves solving a dense system of linear equations, and using direct solution methods is prohibitive for large problems. In this paper, we present IES/sup 3/ (pronounced \"ice cube\"), a fast Integral Equation Solver for three-dimensional problems with arbitrary kernels. Extraction methods based on IES/sup 3/ are substantially more efficient than existing multipole-based approaches.","PeriodicalId":187521,"journal":{"name":"1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)","volume":"23 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126948791","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-11-13DOI: 10.1109/ICCAD.1997.643565
A. Narayan, Adrian J. Isles, J. Jain, R. Brayton, A. Sangiovanni-Vincentelli
We address the problem of finite state machine (FSM) traversal, a key step in most sequential verification and synthesis algorithms. We propose the use of partitioned ROBDDs to reduce the memory explosion problem associated with symbolic state space exploration techniques. In our technique, the reachable state set is represented as a partitioned ROBDD (A. Narayan et al., 1996). Different partitions of the Boolean space are allowed to have different variable orderings and only one partition needs to be in memory at any given time. We show the effectiveness of our approach on a set of ISCAS89 benchmark circuits. Our techniques result in a significant reduction in total memory utilization. For a given memory limit, partitioned ROBDD based method can complete traversal for many circuits for which monolithic ROBDDs fail. For circuits where both partitioned ROBDDs as well as monolithic ROBDDs cannot complete traversal, partitioned ROBDDs can reach a significantly larger set of states.
我们解决了有限状态机(FSM)遍历的问题，这是大多数顺序验证和合成算法的关键步骤。我们建议使用分区的robdd来减少与符号状态空间探索技术相关的内存爆炸问题。在我们的技术中，可达状态集被表示为分区的ROBDD (a . Narayan et al.， 1996)。允许布尔空间的不同分区具有不同的变量顺序，并且在任何给定时间只需要一个分区在内存中。我们在一组ISCAS89基准电路上展示了我们的方法的有效性。我们的技术显著降低了总内存利用率。在给定的内存限制下，基于分区ROBDD的方法可以完成对许多单片ROBDD无法完成的电路的遍历。对于分割的robdd和单片的robdd都不能完成遍历的电路，分割的robdd可以达到更大的状态集。
{"title":"Reachability analysis using partitioned-ROBDDs","authors":"A. Narayan, Adrian J. Isles, J. Jain, R. Brayton, A. Sangiovanni-Vincentelli","doi":"10.1109/ICCAD.1997.643565","DOIUrl":"https://doi.org/10.1109/ICCAD.1997.643565","url":null,"abstract":"We address the problem of finite state machine (FSM) traversal, a key step in most sequential verification and synthesis algorithms. We propose the use of partitioned ROBDDs to reduce the memory explosion problem associated with symbolic state space exploration techniques. In our technique, the reachable state set is represented as a partitioned ROBDD (A. Narayan et al., 1996). Different partitions of the Boolean space are allowed to have different variable orderings and only one partition needs to be in memory at any given time. We show the effectiveness of our approach on a set of ISCAS89 benchmark circuits. Our techniques result in a significant reduction in total memory utilization. For a given memory limit, partitioned ROBDD based method can complete traversal for many circuits for which monolithic ROBDDs fail. For circuits where both partitioned ROBDDs as well as monolithic ROBDDs cannot complete traversal, partitioned ROBDDs can reach a significantly larger set of states.","PeriodicalId":187521,"journal":{"name":"1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128906841","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-11-13DOI: 10.1109/ICCAD.1997.643576
R. Gharpurey, S. Hosur
A semi-analytical technique for computation of the frequency-behavior of silicon substrates is demonstrated. The technique uses a boundary element approach, that utilizes the complex substrate Green Function and the two-dimensional Fast Fourier Transform. The resultant dense system matrix is sparsified by application of orthogonal transform operators on the matrix representing the system. Three transform operators are evaluated for this purpose- the Discrete Cosine Transform (DCT), the Discrete Wavelet Transform (DWT) and the Discrete Hadamard Transform (DHT). The application of any one of these operators provides a rigorous sparsification technique, which significantly reduces the computation time. The Green Function is computed in the two layers at the top of the substrate. This is done so that contacts in the oxide layer can be included in the substrate model, along with contacts in the silicon substrate. Hence, substrate loss terms in metal interconnect lines and in line-to-line interaction models, can be evaluated using this technique. Extraction of a simple circuit-simulator compatible model from frequency-domain data is discussed.
{"title":"Transform domain techniques for efficient extraction of substrate parasitics","authors":"R. Gharpurey, S. Hosur","doi":"10.1109/ICCAD.1997.643576","DOIUrl":"https://doi.org/10.1109/ICCAD.1997.643576","url":null,"abstract":"A semi-analytical technique for computation of the frequency-behavior of silicon substrates is demonstrated. The technique uses a boundary element approach, that utilizes the complex substrate Green Function and the two-dimensional Fast Fourier Transform. The resultant dense system matrix is sparsified by application of orthogonal transform operators on the matrix representing the system. Three transform operators are evaluated for this purpose- the Discrete Cosine Transform (DCT), the Discrete Wavelet Transform (DWT) and the Discrete Hadamard Transform (DHT). The application of any one of these operators provides a rigorous sparsification technique, which significantly reduces the computation time. The Green Function is computed in the two layers at the top of the substrate. This is done so that contacts in the oxide layer can be included in the substrate model, along with contacts in the silicon substrate. Hence, substrate loss terms in metal interconnect lines and in line-to-line interaction models, can be evaluated using this technique. Extraction of a simple circuit-simulator compatible model from frequency-domain data is discussed.","PeriodicalId":187521,"journal":{"name":"1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129295374","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-11-13DOI: 10.1109/ICCAD.1997.643564
P. Variyam, A. Chatterjee
The problem of testing analog components continues to be the bottleneck in reducing the time-to-market of mixed-signal ICs. We present a test generation algorithm for implicit functional testing of linear analog circuits using transient response sampling. Each specification of the circuit under test (CUT) imposes bounds on individual parametric deviations under the single fault assumption. These bounds are mapped on to "acceptable" ranges of measurements of the transient response of the CUT at various sample points using time domain sensitivity calculations. Any circuit that "passes" the applied test is also guaranteed to meet its specifications. The simplicity of the test waveform, reduced test generation time and test time show that this testing method is a good alternative to existing testing schemes.
{"title":"Test generation for comprehensive testing of linear analog circuits using transient response sampling","authors":"P. Variyam, A. Chatterjee","doi":"10.1109/ICCAD.1997.643564","DOIUrl":"https://doi.org/10.1109/ICCAD.1997.643564","url":null,"abstract":"The problem of testing analog components continues to be the bottleneck in reducing the time-to-market of mixed-signal ICs. We present a test generation algorithm for implicit functional testing of linear analog circuits using transient response sampling. Each specification of the circuit under test (CUT) imposes bounds on individual parametric deviations under the single fault assumption. These bounds are mapped on to \"acceptable\" ranges of measurements of the transient response of the CUT at various sample points using time domain sensitivity calculations. Any circuit that \"passes\" the applied test is also guaranteed to meet its specifications. The simplicity of the test waveform, reduced test generation time and test time show that this testing method is a good alternative to existing testing schemes.","PeriodicalId":187521,"journal":{"name":"1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130164290","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-11-13DOI: 10.1109/ICCAD.1997.643601
V. Mooney, G. Micheli
We present a tool that performs real time analysis and priority assignment for software tasks in a mixed hardware software system with a custom run time scheduler. The tasks in hardware and software have precedence constraints, resource constraints, relative timing constraints, and a rate constraint. A dynamic programming formulation assigns the static priorities such that a hard real time rate constraint can be predictably met. We describe the task control/data flow extraction, runtime scheduler implementation, real time analysis and priority scheduler template. We show how our approach fits into an overall tool flow and target architecture. Finally, we conclude with a sample application of the system to a design example.
{"title":"Real time analysis and priority scheduler generation for hardware-software systems with a synthesized run-time system","authors":"V. Mooney, G. Micheli","doi":"10.1109/ICCAD.1997.643601","DOIUrl":"https://doi.org/10.1109/ICCAD.1997.643601","url":null,"abstract":"We present a tool that performs real time analysis and priority assignment for software tasks in a mixed hardware software system with a custom run time scheduler. The tasks in hardware and software have precedence constraints, resource constraints, relative timing constraints, and a rate constraint. A dynamic programming formulation assigns the static priorities such that a hard real time rate constraint can be predictably met. We describe the task control/data flow extraction, runtime scheduler implementation, real time analysis and priority scheduler template. We show how our approach fits into an overall tool flow and target architecture. Finally, we conclude with a sample application of the system to a design example.","PeriodicalId":187521,"journal":{"name":"1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130957913","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Forward model checking is an efficient symbolic model checking method for verifying realistic properties of sequential circuits and protocols. We present the techniques that modify the order of state traversal on forward model checking, and that dramatically improve average CPU time for finding design errors. A failing property has to be checked again and again to analyze the bug until it is corrected. The techniques, therefore, can have significant impacts on actual verification tasks. We use a modified regular//spl omega/-regular expression to represent a set of illegal state transition sequences of an FSM. It makes the problem clear and gives us a sense of depth-first traversal, not on the state space, but on the property.
{"title":"Forward model checking techniques oriented to buggy designs","authors":"H. Iwashita, T. Nakata","doi":"10.5555/266388.266515","DOIUrl":"https://doi.org/10.5555/266388.266515","url":null,"abstract":"Forward model checking is an efficient symbolic model checking method for verifying realistic properties of sequential circuits and protocols. We present the techniques that modify the order of state traversal on forward model checking, and that dramatically improve average CPU time for finding design errors. A failing property has to be checked again and again to analyze the bug until it is corrected. The techniques, therefore, can have significant impacts on actual verification tasks. We use a modified regular//spl omega/-regular expression to represent a set of illegal state transition sequences of an FSM. It makes the problem clear and gives us a sense of depth-first traversal, not on the state space, but on the property.","PeriodicalId":187521,"journal":{"name":"1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127101075","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-11-13DOI: 10.1109/ICCAD.1997.643600
R. Ernst, W. Ye
Formal program running time verification is an important issue in system design required for performance optimization under "first-time-right" design constraints and for real time system verification. Simulation based approaches or simple instruction counting are not appropriate and risky for more complex architectures in particular with data dependent execution paths. Formal analysis techniques have suffered from loose timing bounds leading to significant performance penalties when strictly adhered to. We present an approach which combines simulation and formal techniques in a safe way to improve analysis precision and tighten the timing bounds. Using a set of processor parameters, it is adaptable to arbitrary processor architectures. The results show an unprecedented analysis precision allowing us to reduce performance overhead for provably correct system or interface timing.
{"title":"Embedded program timing analysis based on path clustering and architecture classification","authors":"R. Ernst, W. Ye","doi":"10.1109/ICCAD.1997.643600","DOIUrl":"https://doi.org/10.1109/ICCAD.1997.643600","url":null,"abstract":"Formal program running time verification is an important issue in system design required for performance optimization under \"first-time-right\" design constraints and for real time system verification. Simulation based approaches or simple instruction counting are not appropriate and risky for more complex architectures in particular with data dependent execution paths. Formal analysis techniques have suffered from loose timing bounds leading to significant performance penalties when strictly adhered to. We present an approach which combines simulation and formal techniques in a safe way to improve analysis precision and tighten the timing bounds. Using a set of processor parameters, it is adaptable to arbitrary processor architectures. The results show an unprecedented analysis precision allowing us to reduce performance overhead for provably correct system or interface timing.","PeriodicalId":187521,"journal":{"name":"1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116557568","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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