首页 > 最新文献

1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)最新文献

英文 中文
OPTIMIST: state minimization for optimal 2-level logic implementation 乐观主义者:状态最小化的最佳2级逻辑实现
Pub Date : 1997-11-13 DOI: 10.1109/ICCAD.1997.643536
Robert M. Fuhrer, S. Nowick
We present a novel method for state minimization of incompletely-specified finite state machines. Where classic methods simply minimize the number of states, ours directly addresses the implementation's logic complexity, and produces an exactly optimal implementation under input encoding. The method incorporates optimal "state mapping", i.e., the process of reducing the symbolic next-state relation which results from state splitting to an optimal conforming symbolic function. Further, it offers a number of convenient sites for applying heuristics to reduce time and space complexity, and is amenable to implementation based on implicit representations. Although our method currently makes use of an input encoding model, we believe it can be extended smoothly to encompass output encoding as well.
提出了一种求解不完全限定有限状态机状态最小化的新方法。经典方法只是简单地最小化状态的数量,而我们的方法直接解决了实现的逻辑复杂性,并在输入编码下产生了精确的最佳实现。该方法结合了最优“状态映射”,即将状态分裂产生的下一状态关系符号化简为最优符合性符号函数的过程。此外,它提供了许多方便的站点来应用启发式,以减少时间和空间复杂性,并且可以基于隐式表示实现。虽然我们的方法目前使用的是输入编码模型,但我们相信它也可以平滑地扩展到包含输出编码。
{"title":"OPTIMIST: state minimization for optimal 2-level logic implementation","authors":"Robert M. Fuhrer, S. Nowick","doi":"10.1109/ICCAD.1997.643536","DOIUrl":"https://doi.org/10.1109/ICCAD.1997.643536","url":null,"abstract":"We present a novel method for state minimization of incompletely-specified finite state machines. Where classic methods simply minimize the number of states, ours directly addresses the implementation's logic complexity, and produces an exactly optimal implementation under input encoding. The method incorporates optimal \"state mapping\", i.e., the process of reducing the symbolic next-state relation which results from state splitting to an optimal conforming symbolic function. Further, it offers a number of convenient sites for applying heuristics to reduce time and space complexity, and is amenable to implementation based on implicit representations. Although our method currently makes use of an input encoding model, we believe it can be extended smoothly to encompass output encoding as well.","PeriodicalId":187521,"journal":{"name":"1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133144700","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
EDA and the network EDA与网络
M. Spiller, A. Newton
Digital computer networks are playing an increasingly important role in the evaluation, distribution, integration and management of EDA systems. Tools, libraries, design data, and a variety of both design and manufacturing services are accessible today via networks. Networks are also playing a central role in the integration of system design teams, teams that involve a variety of both business and technical disciplines as well as widely distributed geographical locations. Throughout the history of EDA, the architectures used to integrate and distribute computation and interaction have played a central role in the overall design methodology and so have had a major, indirect impact on the choice of the most effective tools, algorithms, and data structures. In this paper, a number of the factors involved in the choice of a suitable architecture for EDA integration are reviewed and a number of ongoing developments and challenges are presented.
数字计算机网络在EDA系统的评估、分布、集成和管理中发挥着越来越重要的作用。今天,工具、库、设计数据以及各种设计和制造服务都可以通过网络访问。网络也在系统设计团队的集成中扮演中心角色,这些团队包括各种商业和技术学科以及广泛分布的地理位置。在EDA的整个历史中,用于集成和分发计算和交互的体系结构在整个设计方法中发挥了核心作用,因此对最有效的工具、算法和数据结构的选择产生了重大的间接影响。在本文中,回顾了为EDA集成选择合适的体系结构所涉及的一些因素,并提出了一些正在进行的发展和挑战。
{"title":"EDA and the network","authors":"M. Spiller, A. Newton","doi":"10.1145/266388.266532","DOIUrl":"https://doi.org/10.1145/266388.266532","url":null,"abstract":"Digital computer networks are playing an increasingly important role in the evaluation, distribution, integration and management of EDA systems. Tools, libraries, design data, and a variety of both design and manufacturing services are accessible today via networks. Networks are also playing a central role in the integration of system design teams, teams that involve a variety of both business and technical disciplines as well as widely distributed geographical locations. Throughout the history of EDA, the architectures used to integrate and distribute computation and interaction have played a central role in the overall design methodology and so have had a major, indirect impact on the choice of the most effective tools, algorithms, and data structures. In this paper, a number of the factors involved in the choice of a suitable architecture for EDA integration are reviewed and a number of ongoing developments and challenges are presented.","PeriodicalId":187521,"journal":{"name":"1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124358098","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
MOGAC: a multiobjective genetic algorithm for the co-synthesis of hardware-software embedded systems MOGAC:一种用于嵌入式系统软硬件协同合成的多目标遗传算法
Pub Date : 1997-11-13 DOI: 10.1109/ICCAD.1997.643589
R. Dick, N. Jha
We present a hardware-software co-synthesis system, called MOGAC, that partitions and schedules embedded system specifications consisting of multiple periodic task graphs. MOGAC synthesizes real-time heterogeneous distributed architectures using an adaptive multiobjective genetic algorithm that can escape local minima. Price and power consumption are optimized while hard real-time constraints are met. MOGAC places no limit on the number of hardware or software processing elements in the architectures it synthesizes. Our general model for bus and point-to-point communication links allows a number of link types to be used in an architecture. Application-specific integrated circuits consisting of multiple processing elements are modeled. Heuristics are used to tackle multi-rate systems, as well as systems containing task graphs whose hyperperiods are large relative to their periods. The application of a multiobjective optimization strategy allows a single co-synthesis run to produce multiple designs which trade off different architectural features. Experimental results indicate that MOGAC has advantages over previous work in terms of solution quality and running time.
我们提出了一个软硬件协同合成系统,称为MOGAC,它可以划分和调度由多个周期任务图组成的嵌入式系统规范。MOGAC采用一种可避免局部最小值的自适应多目标遗传算法综合了实时异构分布式体系结构。在满足硬实时约束的情况下,优化了价格和功耗。MOGAC对它所合成的体系结构中的硬件或软件处理元素的数量没有限制。我们的总线和点对点通信链路的通用模型允许在体系结构中使用许多链路类型。对由多个处理元件组成的专用集成电路进行了建模。启发式用于处理多速率系统,以及包含超周期相对于其周期较大的任务图的系统。多目标优化策略的应用允许单次协同综合运行产生多种设计,这些设计权衡了不同的建筑特征。实验结果表明,MOGAC算法在求解质量和运行时间上都优于以往的算法。
{"title":"MOGAC: a multiobjective genetic algorithm for the co-synthesis of hardware-software embedded systems","authors":"R. Dick, N. Jha","doi":"10.1109/ICCAD.1997.643589","DOIUrl":"https://doi.org/10.1109/ICCAD.1997.643589","url":null,"abstract":"We present a hardware-software co-synthesis system, called MOGAC, that partitions and schedules embedded system specifications consisting of multiple periodic task graphs. MOGAC synthesizes real-time heterogeneous distributed architectures using an adaptive multiobjective genetic algorithm that can escape local minima. Price and power consumption are optimized while hard real-time constraints are met. MOGAC places no limit on the number of hardware or software processing elements in the architectures it synthesizes. Our general model for bus and point-to-point communication links allows a number of link types to be used in an architecture. Application-specific integrated circuits consisting of multiple processing elements are modeled. Heuristics are used to tackle multi-rate systems, as well as systems containing task graphs whose hyperperiods are large relative to their periods. The application of a multiobjective optimization strategy allows a single co-synthesis run to produce multiple designs which trade off different architectural features. Experimental results indicate that MOGAC has advantages over previous work in terms of solution quality and running time.","PeriodicalId":187521,"journal":{"name":"1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117098397","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 315
NRG: global and detailed placement NRG:全球和详细的安置
Pub Date : 1997-11-13 DOI: 10.1109/ICCAD.1997.643590
M. Sarrafzadeh, Maogang Wang
We present a new approach to the placement problem. The proposed approach consists of analyzing the input circuit and deciding on a two-dimensional global grid for that particular input. After determination of the grid size, the placement is carried out in three steps: global placement, detailed placement, and final optimization. We show that the output of the global placement can also serve as a fast and accurate predictor. Current implementation is based on simulated annealing. We have put all algorithms together in a placement package called NRG (pronounced N-er-G). In addition to area minimization, NRG can perform timing-driven placement. Experimental results are strong. We improve TimberWolf's results (version 1.2) by about 5%. Our predictor can estimate the wavelength within 10-20% accuracy offering 2-20x speedup compared with the actual placement algorithm.
我们提出了一种解决安置问题的新方法。所提出的方法包括分析输入电路并确定特定输入的二维全局网格。确定网格大小后,分全局布局、详细布局和最终优化三步进行布局。我们表明,全局布局的输出也可以作为一个快速和准确的预测器。目前的实现是基于模拟退火的。我们把所有的算法放在一个名为NRG(发音为N-er-G)的放置包中。除了面积最小化之外,NRG还可以执行定时驱动的布局。实验结果是强有力的。我们将TimberWolf的结果(1.2版本)改进了大约5%。我们的预测器可以在10-20%的精度内估计波长,与实际的放置算法相比,提供2-20倍的加速。
{"title":"NRG: global and detailed placement","authors":"M. Sarrafzadeh, Maogang Wang","doi":"10.1109/ICCAD.1997.643590","DOIUrl":"https://doi.org/10.1109/ICCAD.1997.643590","url":null,"abstract":"We present a new approach to the placement problem. The proposed approach consists of analyzing the input circuit and deciding on a two-dimensional global grid for that particular input. After determination of the grid size, the placement is carried out in three steps: global placement, detailed placement, and final optimization. We show that the output of the global placement can also serve as a fast and accurate predictor. Current implementation is based on simulated annealing. We have put all algorithms together in a placement package called NRG (pronounced N-er-G). In addition to area minimization, NRG can perform timing-driven placement. Experimental results are strong. We improve TimberWolf's results (version 1.2) by about 5%. Our predictor can estimate the wavelength within 10-20% accuracy offering 2-20x speedup compared with the actual placement algorithm.","PeriodicalId":187521,"journal":{"name":"1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123935192","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 65
Application-driven synthesis of core-based systems 基于核心系统的应用驱动综合
Pub Date : 1997-11-13 DOI: 10.1109/ICCAD.1997.643382
D. Kirovski, Chunho Lee, M. Potkonjak, W. Mangione-Smith
We developed a new hierarchical modular approach for synthesis of area-minimal core-based data-intensive systems. The optimization approach employs a novel global least-constraining most-constrained heuristic to minimize the instruction cache misses for a given application, instruction cache size and organization. Based on this performance optimization technique, we constructed a strategy to search for a minimal area processor core, and an instruction and data cache which satisfy the performance characteristics of a set of target applications. The synthesis platform integrates the existing modeling, profiling, and simulation tools with the developed system-level synthesis tools. The effectiveness of the approach is demonstrated on a variety of modern real-life multimedia and communication applications.
我们开发了一种新的分层模块化方法,用于合成基于最小面积核心的数据密集型系统。该优化方法采用了一种新颖的全局最小约束最约束启发式算法,以最小化给定应用程序、指令缓存大小和组织的指令缓存缺失。基于这种性能优化技术,我们构建了一种搜索最小面积处理器核心的策略,以及满足一组目标应用性能特征的指令和数据缓存。综合平台将现有的建模、分析和仿真工具与开发的系统级综合工具集成在一起。该方法的有效性在各种现代现实生活中的多媒体和通信应用中得到了验证。
{"title":"Application-driven synthesis of core-based systems","authors":"D. Kirovski, Chunho Lee, M. Potkonjak, W. Mangione-Smith","doi":"10.1109/ICCAD.1997.643382","DOIUrl":"https://doi.org/10.1109/ICCAD.1997.643382","url":null,"abstract":"We developed a new hierarchical modular approach for synthesis of area-minimal core-based data-intensive systems. The optimization approach employs a novel global least-constraining most-constrained heuristic to minimize the instruction cache misses for a given application, instruction cache size and organization. Based on this performance optimization technique, we constructed a strategy to search for a minimal area processor core, and an instruction and data cache which satisfy the performance characteristics of a set of target applications. The synthesis platform integrates the existing modeling, profiling, and simulation tools with the developed system-level synthesis tools. The effectiveness of the approach is demonstrated on a variety of modern real-life multimedia and communication applications.","PeriodicalId":187521,"journal":{"name":"1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129521286","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 31
A signature based approach to regularity extraction 一种基于签名的规则提取方法
Pub Date : 1997-11-13 DOI: 10.1109/ICCAD.1997.643592
S. Arikati, R. Varadarajan
Regularity extraction is an important step in the design flow of datapath-dominated circuits. This paper outlines a new method that automatically extracts regular structures from the netlist. The method is general enough to handle two types of designs: designs with structured cluster information for a portion of the datapath components that are identified at the HDL level; and designs with no such structured cluster information. The method analyzes the circuit connectivity and uses signature based approaches to recognize regularity.
规则提取是数据路径控制电路设计流程中的重要步骤。本文提出了一种从网表中自动提取规则结构的新方法。该方法足够通用,可以处理两种类型的设计:具有结构化集群信息的设计,用于在HDL级别识别的部分数据路径组件;以及没有这种结构化集群信息的设计。该方法分析电路的连通性,并使用基于签名的方法来识别规则性。
{"title":"A signature based approach to regularity extraction","authors":"S. Arikati, R. Varadarajan","doi":"10.1109/ICCAD.1997.643592","DOIUrl":"https://doi.org/10.1109/ICCAD.1997.643592","url":null,"abstract":"Regularity extraction is an important step in the design flow of datapath-dominated circuits. This paper outlines a new method that automatically extracts regular structures from the netlist. The method is general enough to handle two types of designs: designs with structured cluster information for a portion of the datapath components that are identified at the HDL level; and designs with no such structured cluster information. The method analyzes the circuit connectivity and uses signature based approaches to recognize regularity.","PeriodicalId":187521,"journal":{"name":"1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127439777","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 35
Optimizing computations in a transposed direct form realization of Floating-Point LTI-FIR systems 浮点LTI-FIR系统的转置直接形式实现优化计算
Pub Date : 1997-11-13 DOI: 10.1109/ICCAD.1997.643386
N. Sankarayya, K. Roy, D. Bhattacharya
The inherent computational redundancy in discrete-time LTI-FIR system response computations in Digital Signal Processing have been exploited in a variety of ways to minimize the computational complexity. We present an improved algorithm-level computational optimization that uses sorted recursive differences between coefficients representing the system transfer function with a Floating-Point number representation to extract maximum benefits from this redundancy. A can be applied to any LTI-FIR system and there is no deterioration in accuracy compared 20 directly using the coefficients. The results for several practical FIR systems show that there is a significant reduction in the computational complexity, hence power consumed, using this technique.
在数字信号处理中,离散时间LTI-FIR系统响应计算中固有的计算冗余已被多种方法用来最小化计算复杂度。我们提出了一种改进的算法级计算优化,该优化使用表示系统传递函数的系数之间的排序递归差异与浮点数表示,以从这种冗余中提取最大利益。A可以应用于任何LTI-FIR系统,与直接使用系数20相比,精度没有下降。对几个实际FIR系统的结果表明,使用该技术可以显著降低计算复杂度,从而降低功耗。
{"title":"Optimizing computations in a transposed direct form realization of Floating-Point LTI-FIR systems","authors":"N. Sankarayya, K. Roy, D. Bhattacharya","doi":"10.1109/ICCAD.1997.643386","DOIUrl":"https://doi.org/10.1109/ICCAD.1997.643386","url":null,"abstract":"The inherent computational redundancy in discrete-time LTI-FIR system response computations in Digital Signal Processing have been exploited in a variety of ways to minimize the computational complexity. We present an improved algorithm-level computational optimization that uses sorted recursive differences between coefficients representing the system transfer function with a Floating-Point number representation to extract maximum benefits from this redundancy. A can be applied to any LTI-FIR system and there is no deterioration in accuracy compared 20 directly using the coefficients. The results for several practical FIR systems show that there is a significant reduction in the computational complexity, hence power consumed, using this technique.","PeriodicalId":187521,"journal":{"name":"1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127194970","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Functional simulation using binary decision diagrams 使用二元决策图的功能仿真
Pub Date : 1997-11-13 DOI: 10.1109/ICCAD.1997.643253
Christoph Scholl, R. Drechsler, B. Becker
In many verification techniques, fast functional evaluation of a Boolean network is needed. We investigate the idea of using binary decision diagrams (BDDs) for functional simulation. The area-time trade-off that results from different minimization techniques of the BDD is discussed. We propose new minimization methods based on dynamic reordering that allow smaller representations with (nearly) no runtime penalty.
在许多验证技术中,需要对布尔网络进行快速的功能评估。我们研究了使用二元决策图(bdd)进行功能仿真的思想。讨论了不同的BDD最小化技术导致的面积-时间权衡。我们提出了新的基于动态重新排序的最小化方法,允许更小的表示(几乎)没有运行时间损失。
{"title":"Functional simulation using binary decision diagrams","authors":"Christoph Scholl, R. Drechsler, B. Becker","doi":"10.1109/ICCAD.1997.643253","DOIUrl":"https://doi.org/10.1109/ICCAD.1997.643253","url":null,"abstract":"In many verification techniques, fast functional evaluation of a Boolean network is needed. We investigate the idea of using binary decision diagrams (BDDs) for functional simulation. The area-time trade-off that results from different minimization techniques of the BDD is discussed. We propose new minimization methods based on dynamic reordering that allow smaller representations with (nearly) no runtime penalty.","PeriodicalId":187521,"journal":{"name":"1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127220873","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 38
Replication for logic bipartitioning 逻辑双分区的复制
Pub Date : 1997-11-13 DOI: 10.1109/ICCAD.1997.643542
Morgan Enos, S. Hauck, M. Sarrafzadeh
Logic replication, the duplication of logic in order to limit communication between partitions, is an effective part of a complete partitioning solution. In this paper we seek a better understanding of the important issues in logic replication. By developing new optimizations to existing algorithms we are able to significantly improve the quality of these techniques, achieving up to 12.5% better results than the best existing replication techniques. When integrated into our already state-of-the-art partitioner we improve overall cutsizes by 37.8%, while requiring the duplication of at most 7% of the logic.
逻辑复制,即为了限制分区之间的通信而进行的逻辑复制,是完整分区解决方案的有效组成部分。在本文中,我们试图更好地理解逻辑复制中的重要问题。通过对现有算法开发新的优化,我们能够显著提高这些技术的质量,比现有最好的复制技术提高12.5%。当集成到我们最先进的分区器中时,我们将总体裁剪尺寸提高了37.8%,而最多只需要重复7%的逻辑。
{"title":"Replication for logic bipartitioning","authors":"Morgan Enos, S. Hauck, M. Sarrafzadeh","doi":"10.1109/ICCAD.1997.643542","DOIUrl":"https://doi.org/10.1109/ICCAD.1997.643542","url":null,"abstract":"Logic replication, the duplication of logic in order to limit communication between partitions, is an effective part of a complete partitioning solution. In this paper we seek a better understanding of the important issues in logic replication. By developing new optimizations to existing algorithms we are able to significantly improve the quality of these techniques, achieving up to 12.5% better results than the best existing replication techniques. When integrated into our already state-of-the-art partitioner we improve overall cutsizes by 37.8%, while requiring the duplication of at most 7% of the logic.","PeriodicalId":187521,"journal":{"name":"1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125669785","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Circuit optimization via adjoint Lagrangians 伴随拉格朗日算子的电路优化
Pub Date : 1997-11-13 DOI: 10.1109/ICCAD.1997.643532
A. Conn, R. Haring, C. Visweswariah, C. Wu
The circuit tuning problem is best approached by means of gradient-based nonlinear optimization algorithms. For large circuits, gradient computation can be the bottleneck in the optimization procedure. Traditionally, when the number of measurements is large relative to the number of tunable parameters, the direct method is used to repeatedly solve the associated sensitivity circuit to obtain all the necessary gradients. Likewise, when the parameters outnumber the measurements, the adjoint method is employed to solve the adjoint circuit repeatedly for each measurement to compute the sensitivities. In this paper we propose the adjoint Lagrangian method, which computes all the gradients necessary for augmented-Lagrangian-based optimization in a single adjoint analysis. After the nominal simulation of the circuit has been carried out, the gradients of the merit function are expressed as the gradients of a weighted sum of circuit measurements. The weights are dependent on the nominal solution and on optimizer quantities such as Lagrange multipliers. By suitably choosing the excitations of the adjoint circuit, the gradients of the merit function are computed via a single adjoint analysis, irrespective of the number of measurements and the number of parameters of the optimization. This procedure requires close integration between the nonlinear optimization software and the circuit simulation program.
电路调谐问题的最佳解决方法是基于梯度的非线性优化算法。对于大型电路,梯度计算是优化过程中的瓶颈。传统上,当测量次数相对于可调参数的数量较大时,采用直接法反复求解相关的灵敏度电路以获得所有必要的梯度。同样,当参数超过测量值时,采用伴随法对每次测量重复求解伴随电路以计算灵敏度。本文提出了伴随拉格朗日方法,该方法在单个伴随分析中计算基于增强拉格朗日优化所需的所有梯度。在对电路进行标称仿真之后,将优点函数的梯度表示为电路测量值加权和的梯度。权重依赖于标称解和拉格朗日乘数等优化量。通过适当地选择伴随电路的激励,无论测量次数和优化参数的数量如何,都可以通过单次伴随分析计算出优点函数的梯度。这一过程需要非线性优化软件和电路仿真程序的紧密结合。
{"title":"Circuit optimization via adjoint Lagrangians","authors":"A. Conn, R. Haring, C. Visweswariah, C. Wu","doi":"10.1109/ICCAD.1997.643532","DOIUrl":"https://doi.org/10.1109/ICCAD.1997.643532","url":null,"abstract":"The circuit tuning problem is best approached by means of gradient-based nonlinear optimization algorithms. For large circuits, gradient computation can be the bottleneck in the optimization procedure. Traditionally, when the number of measurements is large relative to the number of tunable parameters, the direct method is used to repeatedly solve the associated sensitivity circuit to obtain all the necessary gradients. Likewise, when the parameters outnumber the measurements, the adjoint method is employed to solve the adjoint circuit repeatedly for each measurement to compute the sensitivities. In this paper we propose the adjoint Lagrangian method, which computes all the gradients necessary for augmented-Lagrangian-based optimization in a single adjoint analysis. After the nominal simulation of the circuit has been carried out, the gradients of the merit function are expressed as the gradients of a weighted sum of circuit measurements. The weights are dependent on the nominal solution and on optimizer quantities such as Lagrange multipliers. By suitably choosing the excitations of the adjoint circuit, the gradients of the merit function are computed via a single adjoint analysis, irrespective of the number of measurements and the number of parameters of the optimization. This procedure requires close integration between the nonlinear optimization software and the circuit simulation program.","PeriodicalId":187521,"journal":{"name":"1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127872981","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
期刊
1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)
全部 Acc. Chem. Res. ACS Applied Bio Materials ACS Appl. Electron. Mater. ACS Appl. Energy Mater. ACS Appl. Mater. Interfaces ACS Appl. Nano Mater. ACS Appl. Polym. Mater. ACS BIOMATER-SCI ENG ACS Catal. ACS Cent. Sci. ACS Chem. Biol. ACS Chemical Health & Safety ACS Chem. Neurosci. ACS Comb. Sci. ACS Earth Space Chem. ACS Energy Lett. ACS Infect. Dis. ACS Macro Lett. ACS Mater. Lett. ACS Med. Chem. Lett. ACS Nano ACS Omega ACS Photonics ACS Sens. ACS Sustainable Chem. Eng. ACS Synth. Biol. Anal. Chem. BIOCHEMISTRY-US Bioconjugate Chem. BIOMACROMOLECULES Chem. Res. Toxicol. Chem. Rev. Chem. Mater. CRYST GROWTH DES ENERG FUEL Environ. Sci. Technol. Environ. Sci. Technol. Lett. Eur. J. Inorg. Chem. IND ENG CHEM RES Inorg. Chem. J. Agric. Food. Chem. J. Chem. Eng. Data J. Chem. Educ. J. Chem. Inf. Model. J. Chem. Theory Comput. J. Med. Chem. J. Nat. Prod. J PROTEOME RES J. Am. Chem. Soc. LANGMUIR MACROMOLECULES Mol. Pharmaceutics Nano Lett. Org. Lett. ORG PROCESS RES DEV ORGANOMETALLICS J. Org. Chem. J. Phys. Chem. J. Phys. Chem. A J. Phys. Chem. B J. Phys. Chem. C J. Phys. Chem. Lett. Analyst Anal. Methods Biomater. Sci. Catal. Sci. Technol. Chem. Commun. Chem. Soc. Rev. CHEM EDUC RES PRACT CRYSTENGCOMM Dalton Trans. Energy Environ. Sci. ENVIRON SCI-NANO ENVIRON SCI-PROC IMP ENVIRON SCI-WAT RES Faraday Discuss. Food Funct. Green Chem. Inorg. Chem. Front. Integr. Biol. J. Anal. At. Spectrom. J. Mater. Chem. A J. Mater. Chem. B J. Mater. Chem. C Lab Chip Mater. Chem. Front. Mater. Horiz. MEDCHEMCOMM Metallomics Mol. Biosyst. Mol. Syst. Des. Eng. Nanoscale Nanoscale Horiz. Nat. Prod. Rep. New J. Chem. Org. Biomol. Chem. Org. Chem. Front. PHOTOCH PHOTOBIO SCI PCCP Polym. Chem.
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1